Member, Technical Staff jobs at Synopsys - 31 jobs

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Memory Architect, Technical Director to join Rambus Labs in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Memory Architect, Technical Director, the candidate will be reporting to the Director/Fellow of the architecture research group in Rambus Labs. This is a Full-Time position. Do you like to work in an environment where your contributions and innovations are valued and recognized? Where you get to make an impact on the future of memory architecture? Then come and join Rambus Labs, the R&D center of Rambus. The Memory Architecture Research Group within Rambus Labs is looking for an experienced Memory Systems Architect to work with our team to develop breakthrough solutions for future computing challenges. You will be responsible for researching and architecting memory subsystems for data centers and AI/ML applications. You'll work closely with the most senior research team members in a role that collaborates across the company and that helps define the roadmap for corporate investment in this area. Rambus has a stimulating work culture and a strong technical ladder that attracts the best minds in the industry. The Memory Architect will join a team of memory system thought leaders investigating, architecting, and developing intellectual property across the memory and storage hierarchy. The Memory Architecture Research group has the responsibility for projecting market and technology trends 5+ years in the future, identifying key roadblocks and disruptive opportunities ahead of the industry, and architecting solutions that can lead to significant future revenue streams. With a focus on solving technical challenges in the enterprise/datacenter markets, candidates can expect the work to be intellectually challenging, with a strong emphasis on research quality that leads to substantial innovations in memory architecture Responsibilities * Research, architect, and analyze/model innovative memory device and memory system architectures that address performance and power challenges faced by the enterprise/datacenter and AI markets. * Track key industry and technology trends, develop technology roadmaps that help guide our future research initiatives. * Propose new memory products and features, and work with the appropriate product groups to prototype and commercialize. * Lead/participate in critical initiatives within Rambus Labs. * Develop intellectual property and file patents where appropriate. * Attend relevant technical and industry conferences, publish/present relevant work. * Engage with partners and potential customers to understand market needs and industry trends. Qualifications PhD with 10+ years of experience. Advanced degrees are preferred OR BSEE/MS or similar technical degree with 15+ years of industry experience Skills * Experience with DRAM-based memory system architectures with a track record of developing innovative solutions is required * Knowledge of memory standards (DDRx, LPDDRx, LRDIMM, etc.) is required * Knowledge of server architectures and their memory systems is required * Knowledge of memory controller architecture and functionality is required * Strong written and verbal communication skills are required * Experience with performance modeling/analysis of memory subsystems is strongly desired * Familiarity with current data center system configurations, applications, and performance limitations is strongly desired * A track record of developing intellectual property is strongly desired * Knowledge of emerging memories (RRAM, MRAM, PCM) is a desired * Knowledge of serial link protocols (PCIe, SATA etc.) is desired * Knowledge of server software architectures (MMU, VM, Operating Systems, Firmware, etc.) in the memory system domain is desired About Rambus With over 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership. The US salary range for this full-time position is $169,300 to $314,300. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. #LI-BD1 #LI-HYBRID

Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Memory Architect, Technical Director to join Rambus Labs in San Jose, California. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Memory Architect, Technical Director, the candidate will be reporting to the Director/Fellow of the architecture research group in Rambus Labs. This is a Full-Time position. Do you like to work in an environment where your contributions and innovations are valued and recognized? Where you get to make an impact on the future of memory architecture? Then come and join Rambus Labs, the R&D center of Rambus. The Memory Architecture Research Group within Rambus Labs is looking for an experienced Memory Systems Architect to work with our team to develop breakthrough solutions for future computing challenges. You will be responsible for researching and architecting memory subsystems for data centers and AI/ML applications. You'll work closely with the most senior research team members in a role that collaborates across the company and that helps define the roadmap for corporate investment in this area. Rambus has a stimulating work culture and a strong technical ladder that attracts the best minds in the industry. The Memory Architect will join a team of memory system thought leaders investigating, architecting, and developing intellectual property across the memory and storage hierarchy. The Memory Architecture Research group has the responsibility for projecting market and technology trends 5+ years in the future, identifying key roadblocks and disruptive opportunities ahead of the industry, and architecting solutions that can lead to significant future revenue streams. With a focus on solving technical challenges in the enterprise/datacenter markets, candidates can expect the work to be intellectually challenging, with a strong emphasis on research quality that leads to substantial innovations in memory architecture Responsibilities Research, architect, and analyze/model innovative memory device and memory system architectures that address performance and power challenges faced by the enterprise/datacenter and AI markets. Track key industry and technology trends, develop technology roadmaps that help guide our future research initiatives. Propose new memory products and features, and work with the appropriate product groups to prototype and commercialize. Lead/participate in critical initiatives within Rambus Labs. Develop intellectual property and file patents where appropriate. Attend relevant technical and industry conferences, publish/present relevant work. Engage with partners and potential customers to understand market needs and industry trends. Qualifications PhD with 10+ years of experience. Advanced degrees are preferred OR BSEE/MS or similar technical degree with 15+ years of industry experience Skills Experience with DRAM-based memory system architectures with a track record of developing innovative solutions is Knowledge of memory standards (DDRx, LPDDRx, LRDIMM, etc.) is Knowledge of server architectures and their memory systems is Knowledge of memory controller architecture and functionality is Strong written and verbal communication skills are Experience with performance modeling/analysis of memory subsystems is strongly desired Familiarity with current data center system configurations, applications, and performance limitations is strongly desired A track record of developing intellectual property is strongly desired Knowledge of emerging memories (RRAM, MRAM, PCM) is a desired Knowledge of serial link protocols (PCIe, SATA etc.) is desired Knowledge of server software architectures (MMU, VM, Operating Systems, Firmware, etc.) in the memory system domain is desired About Rambus With over 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future. Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program and gym membership. The US salary range for this full-time position is $169,300 to $314,300. Our salary ranges are determined by role, level and location. The successful candidate's starting pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics. Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application. For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/. #LI-BD1 #LI-HYBRID

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Principal AI/ML Software Engineer About the Role As a Principal AI/ML Software Engineer, you are a recognized expert who drives ML technology strategy and innovation across the organization. This role involves developing novel ML solutions for the most complex problems, influencing organization-wide technical decisions, and leading cross-functional initiatives. You will define the technical vision for AI/ML, guide organizational practices, and serve as a technical authority while building and leading high-performing teams that push the boundaries of what's possible with ML technology. Key Responsibilities Drive ML technology strategy and innovation across the entire organization Lead cross-functional ML initiatives that transform business capabilities Develop novel ML solutions for the most complex and challenging problems Define technical vision and architectural frameworks for AI/ML initiatives Influence organization-wide technical decisions and technology adoption Guide organization-wide ML practices, standards, and innovation roadmap Build and lead high-performing teams that deliver breakthrough ML solutions Must Have Skills Distinguished ML/AI Expertise: Recognized authority in machine learning with comprehensive knowledge across multiple domains Advanced System Architecture: Ability to architect enterprise-scale ML systems that integrate with complex technology ecosystems Technical Vision and Strategy: Capacity to develop and articulate long-term technical vision that aligns with business strategy Cross-Functional Leadership: Proven ability to lead and influence across organizational boundaries at executive levels Research and Innovation: Track record of applying cutting-edge ML research and driving innovation that creates competitive advantage Thought Leadership: Demonstrated ability to establish thought leadership within the organization and the broader industry Preferred Education and Experience Master's or PhD in Computer Science, AI/ML, or related field 12+ years of relevant experience in machine learning engineering and leadership Proven track record of technical leadership in ML/AI with industry recognition Significant contributions to the field through publications, patents, or innovative solutions Why You'll Love Working at ADI At Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology. We offer a supportive environment focused on professional growth, competitive compensation and benefits, work-life balance, and the opportunity to work on cutting-edge projects that make a real impact on the world. Your expertise will shape the future of technology, and you'll be supported by a culture that values continuous advancement and professional growth. Join us and help create the technologies that bridge the physical and digital worlds, making a tangible difference in how people live, work, and connect. For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $170,775 to $256,163. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Staff Robotic Simulation Software Engineer Analog Devices (ADI) is launching an exciting new initiative - the Emerging Tech Hub - a physical space where customers, partners, and academic collaborators can rapidly prototype solutions tailored to their unique challenges. We are seeking a highly skilled and motivated Robotics Engineer with expertise in developing and testing AI-driven robotic applications using NVIDIA Isaac Sim. The ideal candidate will be responsible for designing and implementing simulation environments to generate and train AI/ML models for robot control and perception. A strong background in integrating data from vision, force/torque, and tactile sensors is essential. This role involves working at the intersection of robotics, AI, and high-fidelity simulation. Responsibilities include: Simulation Development: Design, implement, and maintain complex, photorealistic, and physically accurate robotic simulation environments within Isaac Sim (built on Omniverse). Develop custom assets, scripts, and world layouts to represent diverse operational scenarios for robot training. Sensor Integration & Data Generation: Configure and utilize virtual sensors within Isaac Sim, specifically vision (e.g., RGB-D, LiDAR), force/torque (F/T), and tactile sensors, ensuring accurate data output for training. Develop pipelines for large-scale, automated synthetic data generation and annotation from the simulation for AI model training. AI/ML Model Development & Training: Integrate and test AI/ML models (e.g., reinforcement learning, imitation learning, deep learning for perception) with the simulated robot system. Utilize Isaac Sim's tools (e.g., Omniverse Replicator) to manage domain randomization and simulate edge cases to improve model robustness. Robot Control & Validation: Develop and implement low-level and high-level robot control algorithms within the simulation. Validate the performance of trained AI models in simulation before deployment on physical hardware. Collaboration & Documentation: Collaborate closely with hardware, software, and AI research teams. Document development processes, simulation parameters, and AI training methodologies. Qualifications: Education: Bachelor's or Master's degree in Robotics, Computer Science, Electrical Engineering, or a related technical field. Experience: 3+ years of professional experience in robotics software development. Isaac Sim Expertise: Proven hands-on experience developing sophisticated simulation environments and synthetic data generation pipelines using NVIDIA Isaac Sim (or a comparable platform like Gazebo/ROS, V-REP, or MuJoCo, with a strong willingness to transition). Programming: Strong proficiency in Python and experience with C++ is a plus. Robotics Frameworks: Experience with the Robot Operating System (ROS). Sensor Knowledge: Deep understanding of data processing and calibration for robotic sensors, particularly: Vision: Camera models, point clouds, computer vision techniques. Force/Torque: Interpretation of F/T sensor data for compliant control or contact detection. Tactile: Experience integrating data from various tactile sensing modalities. AI/ML Fundamentals: Familiarity with machine learning concepts, especially in the context of robot perception and control (e.g., PyTorch, TensorFlow). For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $144,038 to $216,056. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage + The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. + Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. + The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success + Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests + You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day The Cadence Protium team is looking for talented software engineer to join and contribute to our Protium compiler TDM route development. You'll have a great opportunity to make a difference by applying your engineering and leadership skills to optimize the compiler for compile time, fclk performance and memory efficiency. Requirements + BS with a minimum of 10 years of experience in engineering, computer science or related field. OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience + Strong understanding of data structures, algorithms, and databases. + Demonstrated proficiency in C++, gdb debugging, and general software development skills The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will be a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis of the most advanced custom digital and mixed-signal circuits built for communication, IOT and AI markets. Must haves: + 8+ years of experience in development of EDA tools and one or more of transistor level timing, power, noise, aging, reliability, and emir analysis + Hardcore C++ Knowledge - Linux + Proficiency designing data structures, algorithms, and software engineering principles + Industry experience developing and maintaining C++ based applications on a Unix or Linux environment Requirements: + Experience with quality and software processes + Proficiency designing data structures, algorithms, and software engineering principles + Proficiency in analyzing transistor or gate level schematics + The preferred candidate is expected to have a BS in CS/EE/CE Nice to haves: + Experience in development of circuit simulation or library characterization programs + High level understanding of SPICE simulation transistor models + Experience with distributed programming, database design, and cloud APIs for distributed computing Your work will be focused on: + Enhancing and expanding the existing tools' architecture to cover timing analysis + Creating new frameworks for analysis of effects dominant at n5 and below + Using machine learning technology to bring order of magnitude speed / capacity / usability improvements over existing solutions The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence has a 30+ year history of applying leading edge optimization and analysis algorithms to extremely complex problems in semiconductor and electronic design, verification, and analysis. With its Sigrity platform, Cadence is the leader in providing software for IC package physical design and for analyzing power integrity, signal integrity and design stage electromagnetic interference. The Sigrity R&D team is looking for a talented software engineer who is ready to make a significant impact to the success of the Sigrity product line and to Cadence as a whole. Requirements for our ideal candidate: + MS in EE, CS, math, or related degree + 7 years of experience or PhD + 4 years + Strong background on computational electromagnetics, circuit theory and C++ + Experience developing and maintaining field solver + Experience developing software, preferably in the EDA domain + Knowledge of SI, PI, EMI and EMC + Strong debugging and analytical skills to resolve complex software issues + Explore artificial intelligence (AI) techniques to enhance the speed and capacity of field solver for handling complex, next-generation designs + Enthusiastic, highly motivated, and able to work collaboratively The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence's Genus Synthesis Solution product. Genus is a complete product that encompasses logic synthesis and physical design. The product breadth means we are looking for skilled and motivated candidates with backgrounds in logic synthesis, word-level synthesis, static timing analysis, computer architecture, verification, RTL compilation, placement, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in this space. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the Genus software product. The successful candidate will possess the following combination of education and experience:- MS in Computer Science or Electrical Engineering, PhD is preferred with 6+ years of work experience- Proficient in C/C++- Excellent programming and software engineering skills- Experience with UNIX and/or LINUX platforms is preferred- Strong knowledge of Tcl is preferred- Experience with multithreaded and/or distributed programming is preferred- Prior experience with large software development projects is highly recommended- Prior experience with timing analysis software development projects is highly recommended - Strong ability to learn- Strong analysis and problem solving skills- Good communication skill is preferred as the development team is distributed Most importantly, we are looking for hard working, innovative engineers who enjoy working with a great team in a high-performance culture. The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence - One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day The Cadence Protium team is looking for talented software engineer to join and contribute to our Protium compiler TDM route development. You'll have a great opportunity to make a difference by applying your engineering and leadership skills to optimize the compiler for compile time, fclk performance and memory efficiency. Requirements BS with a minimum of 10 years of experience in engineering, computer science or related field. OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience Strong understanding of data structures, algorithms, and databases. Demonstrated proficiency in C++, gdb debugging, and general software development skills The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will be a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis of the most advanced custom digital and mixed-signal circuits built for communication, IOT and AI markets. Must haves: 8+ years of experience in development of EDA tools and one or more of transistor level timing, power, noise, aging, reliability, and emir analysis Hardcore C++ Knowledge - Linux Proficiency designing data structures, algorithms, and software engineering principles Industry experience developing and maintaining C++ based applications on a Unix or Linux environment Requirements: Experience with quality and software processes Proficiency designing data structures, algorithms, and software engineering principles Proficiency in analyzing transistor or gate level schematics The preferred candidate is expected to have a BS in CS/EE/CE Nice to haves: Experience in development of circuit simulation or library characterization programs High level understanding of SPICE simulation transistor models Experience with distributed programming, database design, and cloud APIs for distributed computing Your work will be focused on: Enhancing and expanding the existing tools' architecture to cover timing analysis Creating new frameworks for analysis of effects dominant at n5 and below Using machine learning technology to bring order of magnitude speed / capacity / usability improvements over existing solutions The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence has a 30+ year history of applying leading edge optimization and analysis algorithms to extremely complex problems in semiconductor and electronic design, verification, and analysis. With its Sigrity platform, Cadence is the leader in providing software for IC package physical design and for analyzing power integrity, signal integrity and design stage electromagnetic interference. The Sigrity R&D team is looking for a talented software engineer who is ready to make a significant impact to the success of the Sigrity product line and to Cadence as a whole. Requirements for our ideal candidate: MS in EE, CS, math, or related degree + 7 years of experience or PhD + 4 years Strong background on computational electromagnetics, circuit theory and C++ Experience developing and maintaining field solver Experience developing software, preferably in the EDA domain Knowledge of SI, PI, EMI and EMC Strong debugging and analytical skills to resolve complex software issues Explore artificial intelligence (AI) techniques to enhance the speed and capacity of field solver for handling complex, next-generation designs Enthusiastic, highly motivated, and able to work collaboratively The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Job Description Cadence Design Systems is looking for a highly motivated software engineer to work as a member of the R&D staff on Cadence's Genus Synthesis Solution product. Genus is a complete product that encompasses logic synthesis and physical design. The product breadth means we are looking for skilled and motivated candidates with backgrounds in logic synthesis, word-level synthesis, static timing analysis, computer architecture, verification, RTL compilation, placement, power analysis, routing, extraction, and optimization. You will be part of a team responsible for creating the innovative technologies required for technology leadership in this space. Development responsibilities include designing, developing, troubleshooting, debugging and supporting the Genus software product. The successful candidate will possess the following combination of education and experience: • MS in Computer Science or Electrical Engineering, PhD is preferred with 6+ years of work experience • Proficient in C/C++ • Excellent programming and software engineering skills • Experience with UNIX and/or LINUX platforms is preferred • Strong knowledge of Tcl is preferred • Experience with multithreaded and/or distributed programming is preferred • Prior experience with large software development projects is highly recommended • Prior experience with timing analysis software development projects is highly recommended • Strong ability to learn • Strong analysis and problem solving skills • Good communication skill is preferred as the development team is distributed Most importantly, we are looking for hard working, innovative engineers who enjoy working with a great team in a high-performance culture. The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Principal Software Engineer - Low-Power Verification (Palladium & Protium) We are seeking a highly skilled Senior Software Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this role, you will drive innovations that improve the debuggability, performance, and scalability of multi-billion-gate UPF (Unified Power Format) designs across modular compilation flows (2-state and 4-state). Key Responsibilities + Design, develop, and optimize low-power verification software for Palladium and Protium. + Improve UPF design debuggability within the IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state). + Enhance compiled streaming probes and accelerate waveform generation for large-scale designs. + Collaborate closely with R&D, Product Engineering (PE), and Application Engineering (AE) to deploy UPF solutions across diverse flows, including: + AVIP + UPF + 2/4-state + UVMA + UPF + 2/4-state + MC + UPF + Dielets + UPF + Consolidate and unify UPF software across Palladium and Protium platforms. + Contribute to major initiatives such as: + MC + PPC flow with UPF 4-state + UPF compilation time optimization + Full Vision UPF probe integration + SAGE UPF debug with Verisium Qualifications + Bachelor's degree in Computer Science or Electrical Engineering with 7+ years of relevant experience,OR a Master's degree with 5+ years,OR a PhD with 1+ year of industry experience. Required Skills + Strong proficiency in object-oriented design and C++ development. + Experience with standard C/C++ libraries and the C++ STL. + Demonstrated ability to build high-performance software for large-scale data processing. + Scripting experience in Perl, Tcl/Tk, and/or Python. + Familiarity with IEEE 1801 and UPF implementation. + Experience with Verilog, SystemVerilog, and VHDL. The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We seek a graduate researcher-practitioner in applied mathematics/statistics to advance algorithms for electronic circuit simulation, Monte Carlo yield analysis, and optimization. You will work cross-functionally to turn deep math into production-grade technology. Qualifications Graduate degree in applied mathematics, statistics, or a closely related field (CS with strong math focus). Demonstrated ability to conduct literature reviews, translate theory to practice, and deliver innovative results in real-world settings. Core Expertise Statistical inference: significance testing (p-values, confidence intervals), Bayesian statistics, design of experiments, Monte Carlo methods (random sampling, density estimation). Rare-event and reliability analysis (a plus): importance sampling, subset simulation, cross-entropy methods, extreme value/tail modeling, yield estimation. Surrogate modeling and Uncertainty Quantification (a plus): Gaussian processes, polynomial chaos, sparse grids, variance reduction. Applied Mathematics (any of the following is a plus) Optimization: linear, nonlinear, convex, integer, stochastic, variational; robust/multi-objective; derivative-free/global methods (e.g., CMA-ES, Bayesian optimization). Numerical analysis: numerical linear algebra (sparse/Krylov/preconditioning), stiff ODE/DAE solvers, approximation, quadrature; model reduction (POD/MOR). Differential equations: ODE/PDE/SDE, dynamical systems. Probability and statistics: stochastic processes, inference, uncertainty quantification. Data science: statistical learning, optimization for ML, dimensionality reduction. Familiarity with Machine Learning (preferred) Classical ML: regression (linear/logistic), regularization (ridge/lasso), classification (SVM, kNN), ensembles (trees, random forests, boosting). Contemporary AI (a plus): graph neural networks, transformers, reinforcement/transfer learning, representation learning, active learning. Software and Systems (Not needed but any of the following is a plus) Programming proficiency in Python and/or C++ is a plus (NumPy/SciPy, PyTorch/JAX, performance optimization, clean APIs). Strong computer science background is a plus (data structures, algorithms, version control, testing, CI/CD). HPC/parallel computing (a plus): MPI, CUDA, distributed workflows. Any prior Experience in the following areas is a plus Scientific computing in one or more areas: computational electromagnetics, fluid/thermal/molecular dynamics, computational physics, or electrical circuit simulation. Electronic design automation (EDA): SPICE/Spectre/Verilog-A, netlists, PVT/Monte Carlo flows, yield/parametric corners. Responsibilities Research, design, and validate algorithms for circuit simulation, rare-event estimation, and optimization. Quantify accuracy/speed vs. baselines; perform rigorous statistical analyses. Build robust, maintainable implementations and integrate with production toolchains. Good Team Player as well as collaborate with cross-functional teams and document methods and results clearly. The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Principal Software Engineer - Low-Power Verification (Palladium & Protium) We are seeking a highly skilled Senior Software Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this role, you will drive innovations that improve the debuggability, performance, and scalability of multi-billion-gate UPF (Unified Power Format) designs across modular compilation flows (2-state and 4-state). Key Responsibilities Design, develop, and optimize low-power verification software for Palladium and Protium. Improve UPF design debuggability within the IXCOM Modular Compiler and Parallel Partition Compiler (2-state and 4-state). Enhance compiled streaming probes and accelerate waveform generation for large-scale designs. Collaborate closely with R&D, Product Engineering (PE), and Application Engineering (AE) to deploy UPF solutions across diverse flows, including: AVIP + UPF + 2/4-state UVMA + UPF + 2/4-state MC + UPF Dielets + UPF Consolidate and unify UPF software across Palladium and Protium platforms. Contribute to major initiatives such as: MC + PPC flow with UPF 4-state UPF compilation time optimization Full Vision UPF probe integration SAGE UPF debug with Verisium Qualifications Bachelor's degree in Computer Science or Electrical Engineering with 7+ years of relevant experience, OR a Master's degree with 5+ years, OR a PhD with 1+ year of industry experience. Required Skills Strong proficiency in object-oriented design and C++ development. Experience with standard C/C++ libraries and the C++ STL. Demonstrated ability to build high-performance software for large-scale data processing. Scripting experience in Perl, Tcl/Tk, and/or Python. Familiarity with IEEE 1801 and UPF implementation. Experience with Verilog, SystemVerilog, and VHDL. The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Senior Principal Software Engineer Location: IMEC Campus, Leuven, Belgium Reports to: Software Engineering Group Director Job Overview: + Research, design, and develop Electronic Design Automation (EDA) software. + Contribute to the development of advanced routing engine, tackling complex challenges in IC design + Opportunity to explore specialized routing techniques for the most advanced integrated circuit designs + Support Imec on-site with leading edge process node development Job Responsibilities: + Design and implement enhancements to the Nanoroute routing engine. + Address routing challenges specific to advanced technology nodes. + Investigate and prototype special routing methodologies for next-generation ICs. + Collaborate cross-functionally with other engineering teams to ensure seamless integration and performance. + Contribute to architectural decisions and long-term technical strategy. Job Qualifications: + Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 5+ years of industry experience, OR + M.S. in the same fields with 9+ years of industry experience. + Strong proficiency in C/C++ and data structures/algorithms. + Solid understanding of EDA tools and IC physical design concepts. + Experience with signal routing algorithms or related optimization techniques is a plus. Additional Skills/Preferences: + Excellent problem-solving and communication skills. + Ability to thrive in a fast-paced, collaborative environment. Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. Travel: Some travel to California, USA, to work with wider Cadence R&D team We're doing work that matters. Help us solve what others can't. Additional Jobs (************************************************* Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. + Read the policy(opens in a new tab) (******************************************************************************************************************************** We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** . E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (************************************************************************************************************************** Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Principal AI Software Engineer THE ROLE: In this team you will be building the technology used to accelerate the latest AI models addressing the areas such as vision models, speech recognition, working with the leading engineers in AMD's CPU, GPU and Adaptable Compute teams THE PERSON: In this role you will be leading development activities and writing some of the key components of the software involved in AI/ML frameworks such as PyTorch, TensorFlow, TVM, MLIR. You are someone that has insight into performance optimizations. KEY RESPONSIBILITIES: Develop the latest algorithms, software, and architectures for AI acceleration. In this role you will be a technology leader and provide expertise to help AMD build the best AI acceleration solutions in the industry. PREFERRED EXPERIENCE: Knowledge of AI frameworks like TensorFlow, PyTorch, TVM, MLIR Understanding of AI application stacks including OpenCV, OpenCL, OpenVX, etc. Expertise with Deep Neural network architectures like CNN, RNN, Transformer Knowledge of Acceleration platforms like GPU, TPU, APU, FPGAs. Years Experience in Software Development Years in Machine Learning ACADEMIC CREDENTIALS: M.S. or Ph.D LOCATION: San Jose, Ca. #LI-JT1 Requisition Number: 153131 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for an influential software engineer who is passionate about improving the performance of key applications and benchmarks. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: * Conduct research and development of novel algorithms for logic synthesis and optimization * Deliver multi-fold improvements in quality of results (QOR), runtime, and memory. * Evaluate new FPGA architecture features and their impact on existing implementation tools. * Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture * Design and develop new groundbreaking AMD technologies * Debug/fix existing issues and research alternative, more efficient ways to accomplish the same work * Develop technical relationships with peers and partners PREFERRED EXPERIENCE: * In-depth knowledge of Data Structure and Algorithms * Solid programming skills in C++ * Solid foundation in software engineering, with strong analytical and debugging skills * Experience in architecting and implementing high performance Logic Synthesis engines or other EDA tools * Experience in working with multi-threaded / multi-process programs ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent LOCATION: San Jose, CA #LI-CJ3 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Senior Staff Software Engineer - NPU Compiler Solutions THE ROLE: AMD is looking for an influential software engineer who is passionate about improving the performance of key applications and benchmarks. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: * Contributing to the architecture and design of the MLIR-centric NPU compiler platform. * Develop and integrate solutions to efficiently deploy algorithms on spatial compute devices, such as NPUs. * Work with cross functional teams to identify problems and create solutions. * Work with management team on project planning activities. PREFERRED EXPERIENCE: * Strong C/C++ systems programming (modern C++), Python for tooling/prototyping. * Hands-on MLIR experience: Dialect design (ops/types/attributes/interface), Pass pipelines, (pattern rewrites, canonicalization/legalization). Proficiency with core dialects: Linalg/Tensor, Affine, SCF, Vector. * Accelerator compiler experience: GPU/NPU/AI engines or similar spatial devices; memory hierarchies, streams, scratchpads, NoC-aware optimization. * Auto-optimization: practical experience building or integrating auto-tiling, auto-scheduling, and auto-tuning systems. * Operator fusion and graph-level optimization for DSP&ML workloads (CNNs, transformers, FFT), layout/dtype transforms, quantization-aware workflows. * Solid understanding of heterogeneous runtime models, concurrency, synchronization, and performance profiling. NICE TO HAVE: * Polyhedral/affine analysis, dependence analysis, bank/conflict modeling, memory placement strategies. * Open-source contributions to LLVM/MLIR or peer-reviewed publications in compilers/ML systems. * ML compiler stacks: IREE, TVM, XLA, Glow, Halide; auto-schedulers/tuners integration. * Expertise in Linux kernel/driver development for multi-processor heterogeneous systems. * Knowledge of Acceleration platforms like GPU, TPU, APU, FPGAs. ACADEMIC CREDENTIALS: * Master's or PhD in Electrical Engineering, Computer Science, or related field. LOCATION: * San Jose This role is not eligible for visa sponsorship. #LI-GW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.