Senior Applications Engineer jobs at Synopsys - 348 jobs
Principal Memory Interface Applications Engineer
Synopsys, Inc. 4.4
Senior applications engineer job at Synopsys
Category Engineering Hire Type Employee Job ID 13854 Base Salary Range $184000-$276000 Remote Eligible No Date Posted 21/12/2025 Location Note: While we prefer hire for this role to work out of our Sunnyvale campus, we will also consider hiring for this role to work out of our offices located in Austin, Ottawa as well as in Boxborough*
We Are:
At Synopsys, we drive the innovations that shape how we live and connect. Our technology powers the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead the way in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to help shape the future through continuous innovation in chip design and IP integration.
You Are:
You are a highly experienced engineer with 8+ years in the semiconductor industry, specializing in Memory Interface IP (DDR, LPDDR, HBM) or other high-speed Interface IPs (PCIe, Ethernet, UCIe, and beyond). You possess a deep understanding of AMBA bus architectures, including AXI, and are proficient in backend engineering, lab/debug, and silicon bring-up processes. Your technical expertise is complemented by a proven ability to communicate complex concepts clearly and effectively, whether presenting to customers, collaborating with global teams, or authoring comprehensive documentation. You are organized, adaptable, and thrive in dynamic environments where multiple projects and priorities demand your attention. With a Bachelor's or Master's degree in Electronics Engineering (VLSI specialization preferred), you are committed to staying at the forefront of evolving memory protocols such as DDR5, LPDDR6, MRDIMM2, and HBM4. You are ready to travel up to 15% to provide expert support to customers worldwide. Above all, you are driven by a passion for technology, a commitment to continuous learning, and a desire to make a tangible impact on the future of silicon innovation.
What You'll Be Doing:
* Supporting post-sales integration and silicon bring-up of Memory Interface PHY IPs (HBM, DDR, LPDDR) and Controller IPs, ensuring seamless customer adoption and deployment.
* Delivering insightful technical presentations and hands-on training sessions to both internal teams and external customers.
* Creating clear, detailed documentation and user collateral to facilitate customer understanding and product usability.
* Collaborating closely with internal engineering teams and customer counterparts to troubleshoot, debug, and resolve integration challenges.
* Staying current with the latest memory protocols and standards (e.g., DDR5, LPDDR6, MRDIMM2, HBM4), driving technical excellence and innovation.
* Advocating for product usability and adoption, gathering feedback to inform future improvements and ensure Synopsys memory solutions remain best-in-class.
The Impact You Will Have:
* Enhance customer experience and project success through expert guidance and support.
* Facilitate smooth integration of Synopsys Memory Interface IPs, reducing time-to-market for cutting-edge silicon products.
* Improve product documentation and usability, making complex solutions accessible to a global customer base.
* Strengthen Synopsys' leadership position in the Memory Interface IP market through technical excellence and customer-centricity.
* Deliver valuable feedback to engineering and product teams, driving continuous improvement and innovation.
* Drive technology adoption by enabling customers to leverage advanced memory protocols for next-generation applications.
What You'll Need:
* Direct experience with Memory Interface PHY IPs (HBM, DDR, LPDDR) and Controller IPs integration and bring-up.
* Solid knowledge of AMBA/AXI bus interfaces, floor-planning, and backend engineering for ASIC design.
* Proficiency with Linux, Verilog/VHDL, and modern ASIC design flows.
* Bachelor's or Master's degree in Electronics Engineering (VLSI focus strongly preferred).
* Demonstrated skills in lab/debug and silicon bring-up, including hands-on experience with hardware and test equipment.
Who You Are:
* Excellent communicator, able to convey technical information clearly to diverse audiences.
* Collaborative team player, comfortable working across global teams and cultures.
* Efficient and organized, skilled at managing multiple projects and priorities.
* Detail-oriented and adaptable, thriving in fast-paced and evolving environments.
* Proactive problem solver, eager to tackle new challenges and drive results.
The Team You'll Be A Part Of:
Join a global, high-performing team of engineers dedicated to customer success and product excellence in DDR and Memory Interface IP solutions. You'll work alongside industry leaders, collaborating on innovative projects that push the boundaries of silicon technology and enable next-generation applications worldwide.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Travel:
Up to 15% travel required for customer support and collaboration.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.
$184k-276k yearly 28d ago
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Lead Power Module Design Engineer
Analog Devices, Inc. 4.6
San Jose, CA jobs
A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities.
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$108k-143k yearly est. 3d ago
Senior Physical IC Design Engineer: RTL to Tape-out
Broadcom Inc. 4.8
San Jose, CA jobs
A leading technology company is seeking a Physical IC Design Engineer in San Jose, California. The role involves executing various physical design tasks and requires a bachelor's degree in Electrical or Electronics Engineering with over 12 years of relevant experience. Strong scripting skills and expertise in EDA tools are essential. The position offers a competitive salary range of $141,300 - $226,000 along with comprehensive benefits including health insurance, 401(K) matching and more.
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$141.3k-226k yearly 4d ago
Senior Product Engineer, Manufacturing & IC Yield
Analog Devices, Inc. 4.6
San Jose, CA jobs
A leading semiconductor company in San Jose seeks a SeniorEngineer in Product Engineering to manage new product introductions and production support. Candidates should have a Master's degree in Electrical Engineering and two years of relevant experience. Responsibilities include interfacing with manufacturing, conducting failure analyses, and implementing process improvements. This role offers competitive pay and benefits, including healthcare coverage and a performance-based bonus.
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$98k-129k yearly est. 2d ago
Senior Physical IC Design Engineer - Onsite in San Jose
Broadcom Inc. 4.8
San Jose, CA jobs
A leading technology company in San Jose is looking for a Physical IC Design Engineer to drive next-gen AI and ML ecosystems. The role requires 8+ years of experience and a Bachelor's degree in Electrical or Electronics Engineering. Responsibilities include execution of Physical Design, Synthesis, and collaborating with IC Design engineers. This position has a salary range of $120,000 - $192,000 and offers a comprehensive benefits package including health plans, 401(K) matching, and paid leave.
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$120k-192k yearly 17h ago
Senior Physical IC Design Engineer: RTL to Tape-Out
Broadcom Inc. 4.8
San Jose, CA jobs
A leading semiconductor company in San Jose is seeking a Physical IC Design Engineer to drive next-generation AI and ML ecosystems through PCIe Switch Products. This role requires a strong background in Physical Design, including execution of design, verification, and timing closure. The ideal candidate must have a Bachelor's degree in Electrical or Electronics Engineering and at least 8 years of experience. The position offers a competitive salary range of $120,000 to $192,000, along with comprehensive benefits.
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$120k-192k yearly 4d ago
Senior Physical IC Design Engineer: RTL-to-Tapeout, On-site
Broadcom Inc. 4.8
San Jose, CA jobs
A leading technology firm located in San Jose is seeking a Physical IC Design Engineer to drive innovation in Artificial Intelligence and Machine Learning through their products. This position focuses on executing the physical design and verification of chip architectures. Candidates should possess a Bachelor's degree in Electrical Engineering or Electronics Engineering and have over 8 years of relevant experience. The role offers a competitive salary ranging from $120,000 to $192,000, plus various benefits including medical and retirement plans.
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$120k-192k yearly 17h ago
Senior Power Module Design Engineer - San Jose
Analog Devices, Inc. 4.6
San Jose, CA jobs
A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth.
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$96k-127k yearly est. 2d ago
Senior Physical IC Design Engineer - RTL to Tape-Out
Broadcom Inc. 4.8
San Jose, CA jobs
A leading semiconductor company in San Jose is seeking an experienced Physical IC Design Engineer to join their Data Center Solutions Group. You will drive advancements in AI/ML ecosystems and manage data centers. The ideal candidate will have over 12 years of experience in physical design and proficiency in TCL/PERL scripting. A Bachelor's degree in Electrical or Electronics Engineering is required. This position offers a competitive salary and comprehensive benefits package, including health insurance and 401(k) matching.
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$127k-161k yearly est. 17h ago
Senior Physical Design Engineer - 2.5D/3D ICs
Broadcom Inc. 4.8
San Jose, CA jobs
A leading technology firm in San Jose is seeking a Physical Design Engineer to focus on the implementation and optimization of IC layouts for advanced technologies. The ideal candidate has extensive experience in physical layout, strong scripting skills in TCL and Python, and a solid background in electrical engineering. This role offers a competitive salary, bonus potential, and comprehensive benefits.
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$127k-161k yearly est. 4d ago
Senior FPGA Design & Validation Engineer
Advanced Micro Devices 4.9
Santa Clara, CA jobs
A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity.
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$126k-160k yearly est. 2d ago
Senior FPGA Design Engineer
Advanced Micro Devices 4.9
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
The Role
This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities.
The Person
Strong analytical and problem solving skills with a pronounced attention to detail
Strong communication, mentoring and leadership skills
Self-driven, Methodical and attention to detail in troubleshooting and problem-solving
Can work well with cross functional teams
Excellent verbal and written communication skills
Responsibility
Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.)
Create RTL designs using Verilog/SystemVerilog for high-performance applications
Perform FPGA prototype design, implementation, and bring‑up activities
Create comprehensive design documentation, specifications, and technical reports
Perform timing analysis, closure, and optimization using Vivado tools
Conduct board-level bring‑up and system integration testing
Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment
Validate FPGA designs against specifications and performance requirements
Independently troubleshoot and resolve challenging technical issues
Work closely with hardware, software, and systems engineering teams
Participate in design reviews and technical discussions
Communicate project status, risks, and technical challenges to stakeholders
Preferred Skill Set & Experience
Extensive experience in field of FPGA hardware prototyping
Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc
Experience with Xilinx Versal ACAP or UltraScale+ devices
Knowledge of FPGA synthesis tools and methodologies
Familiarity with Python/TCL scripting for design automation
Knowledge of FPGA-based system architecture and hardware/software co‑design
Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers)
Fluent in System Verilog and a familiarity with simulation and debug
Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus
EDUCATION
BS (or higher) degree in Electrical or Computer Engineering desired
LOCATION
Santa Clara, CA
This role is not eligible for visa sponsorship.
#LI‑SC3
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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$126k-160k yearly est. 2d ago
Lead DFT Design Engineer for SoC/ASIC
Cadence Design Systems 4.7
San Jose, CA jobs
A leading electronic design automation company in California seeks an experienced SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) methodologies. The ideal candidate will have substantial expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the ability to work collaboratively in a cross-functional team environment. This is a fantastic opportunity to contribute to essential technology projects.
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$124k-165k yearly est. 3d ago
Senior Silicon Design Engineer
Advanced Micro Devices 4.9
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.
Together, we advance your career.
THE ROLE
We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems.
THE PERSON
You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon.
KEY RESPONSIBILITIES
Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors.
Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design.
Specify architecture requirements, conduct early-stage analysis, and create detailed specifications.
Drive PPA optimization and ensure scalability across roadmap and custom devices.
Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure.
Analyze trade-offs for performance, power, reliability, and manufacturability.
Influence strategies for security, safety, and reliability across CPF domains.
Strong communication and leadership skills to influence cross-functional teams.
PREFERRED EXPERIENCE
Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators.
Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management.
Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS.
Experience with low-power design techniques, boot/reset flows, and power management.
Knowledge of design methodologies, advanced process technologies, and associated challenges.
Proficiency in modeling and automation using Python, SystemC, or similar languages.
ACADEMIC & EXPERIENCE REQUIREMENTS
BS or MS or PhD in Electrical/Computer Engineering or related field.
Proven track record in delivering architecture for high-performance, low-power SoCs.
LOCATION: San Jose, California
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
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$126k-160k yearly est. 1d ago
Physical IC Design Engineer
Broadcom Inc. 4.8
San Jose, CA jobs
Physical IC Design Engineer page is loaded## Physical IC Design Engineerlocations: USA-California-San Jose-1320 Ridder Park Drivetime type: Full timeposted on: Posted Todayjob requisition id: R024621**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **:**Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves working with the latest technology to continue driving next generation AI/ML ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.**Responsibilities include, but are not limited to the following:*** Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure* Setup and Synthesizing RTL* Timing closure through various methods and strategies; preferable in-depth experience in top-level STA* EM/IR Analysis,* Place and Route* Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques* Floor-planning and Layout; preferable in-depth experience in top-level floorplanning* Flow and Methodology Development* Collaborating with IC Design RTL Engineers* Must work in person at our San Jose site: no remote work allowed.**Required attributes:*** TCL/PERL Scripting* Proficiency in related EDA Tools* Full physical design cycle experience: RTL to Tape-out* Excellent verbal and written communication skills**Education and Experience Requirements:*** Minimum: Bachelor's degree required in Electrical Engineering or Electronics Engineering* 12+ Years of relevant experience**Additional Job Description:****Compensation and Benefits**The annual base salary range for this position is $141,300 - $226,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.****If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**
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$141.3k-226k yearly 4d ago
Physical Design Engineer
Broadcom Inc. 4.8
San Jose, CA jobs
Physical Design Engineer page is loaded## Physical Design Engineerlocations: USA-CA San Jose Innovation Drivetime type: Full timeposted on: Posted Todayjob requisition id: R024355**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **:**The ASIC Products Division at Broadcom has developed some of the most complex IC solutions and technologies over the last two decades. Our products power the internet in areas such as machine learning, cloud computing, wireless infrastructure, and networking. We develop some of the most advanced technologies in the industry encompassing 3D and 2.5D interconnects.We are seeking a design engineer with physical layout skills to develop our next generation products with a focus on parallel interfaces. The job requires aspects of a successful layout engineer, an electrical background, a strong interest in 2.5D and 3D IC development, and new technology pathfinding. The candidate will work on a mix of customer products and development of new interconnect technologies and IP for MCM, 2.5D, and 3D ICs, working alongside R&D, IP development, customers, and manufacturing partners.This is an exciting opportunity to develop new ideas, design the next generation of leading edge ASIC products, and work on the most advanced technologies in the industry.**Responsibilities:*** Design implementation and physical layout implementation of power grids, 2.5D and 3D die-die interconnects.* DRC, LVS, and electrical checking.* Ability to automate common processes and design steps.* Development of high-speed signal interconnects working alongside SI and PI engineers.* Electrical analysis and optimization of ubump and RDL patterns.* Evaluation and development of new 2.5D and 3D interconnect technologies.* Technology and testchip roadmapping with a focus on advanced packaging.**Skills and Experience:*** Independent, self-starter who can work across a worldwide organization and customer base.* Ability to manage multiple concurrent customers under short timelines.* Comfort with providing guidance and direction with incomplete information.* Experience with various IC, Package and PCB layout databases and tools.* Strong TCL, Python scripting experience to automate routine tasks.* Bachelor's degree in Electrical Engineering or Computer Science and 8+ years related work experience or a Master's degree in Electrical Engineering or Computer Science and 6+ years related work experience.**Additional Job Description:****Compensation and Benefits** The annual base salary range for this position is $120,000 - $192,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.****If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**
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$120k-192k yearly 4d ago
Senior Field Service Engineer - Hardware & Linux Systems
Cadence Design Systems 4.7
San Jose, CA jobs
A leading electronic design automation company in San Jose seeks a Principal Field Service Engineer to install, troubleshoot, and maintain hardware emulation platforms. The role involves providing technical support at customer sites, primarily in the eastern US. Candidates should have a strong background in hardware troubleshooting, excellent communication skills, and a willingness to travel. Experience with Linux/Unix systems and various debugging tools is preferred. Join a company that values innovation and equal opportunity.
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$109k-144k yearly est. 2d ago
Senior Field Service Engineer - Hardware & Linux Systems
Cadence Design Systems 4.7
San Jose, CA jobs
A leading electronic design automation company is seeking a Principal Field Service Engineer to install, troubleshoot, and maintain hardware systems. This role is crucial for supporting the Atlanta data center and other locations, requiring excellent problem-solving and communication skills. Candidates should have at least 7 years of experience in a relevant field and be willing to travel. Full training provided, and experience in networking and scripting is advantageous.
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$109k-144k yearly est. 1d ago
High-Speed Mixed-Signal IC Design Engineer
Advanced Micro Devices 4.9
San Jose, CA jobs
A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship.
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$118k-155k yearly est. 17h ago
Physical Design Applications Engineer
Synopsys, Inc. 4.4
Senior applications engineer job at Synopsys
Category Engineering Hire Type Employee Job ID 13867 Base Salary Range $109000-$163000 Remote Eligible No Date Posted 20/12/2025 At Synopsys, we drive the innovations that shape the way the world connects and computes. Our technology powers cutting-edge silicon in applications from mobile and AI to autonomous systems and advanced computing. Join us to help customers achieve breakthrough performance using our leading EDA tool suite.
We are seeking a Physical Design Engineer with strong technical skills in digital implementation and optimization. In this role you will work with engineering teams and customers to deliver solutions that drive timing closure, power and area optimization, and robust RTL-to-GDS flows using Synopsys tools.
You Are
You are an ASIC/physical design engineer with 2-4 years of hands-on experience in digital implementation flows. You understand full RTL-to-GDS design flows and are comfortable applying state-of-the-art methodologies to achieve timing closure and quality signoff. You have solid scripting skills to automate flows and customize solutions, and you communicate clearly with internal teams and customers to solve complex design challenges.
What You'll Be Doing
* Execute RTL-to-GDSII digital implementation flows, including logic synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off quality closure.
* Work with customers and internal teams to troubleshoot and optimize implementation challenges, propose solutions, and deliver highly-tuned PPA results.
* Utilize Synopsys tools such as Fusion Compiler, PrimeTime, and DSO.ai/FusionAI in digital implementation and static timing analysis.
* Develop and enhance automation scripts and flows using TCL, Python, Perl, or other scripting languages.
* Perform static timing analysis (STA), debug timing violations, and implement ECOs to improve performance and timing closure.
* Drive DRC/LVS/Signoff quality closures at advanced technology nodes.
* Collaborate with customers, product teams, and research groups to share best practices and feedback to improve tool flows.
What You'll Need
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
* 2-4 years of hands-on experience in digital physical design or backend implementation.
* Experience with full RTL-to-GDS flows, including place & route methodologies, STA, timing closure, and signoff strategies.
* Proficiency with Synopsys tools such as Fusion Compiler, PrimeTime, and familiarity with AI-assisted optimization tools (e.g., DSO.ai/FusionAI) is highly desirable.
* Solid scripting skills in TCL, Python, Perl, or equivalent for flow automation.
* Strong analytical ability to dissect complex timing, PPA, and design challenges.
* Familiarity with unix/linux environments and engineering workflows.
* Excellent communication skills and ability to work in collaborative team and customer-facing environments.
Who You Are
* A proactive self-starter who takes ownership of technical solutions and delivery.
* Comfortable interfacing with customers and internal teams to understand requirements and deliver effective outcomes.
* Able to adapt to evolving methodologies and rapidly learn emerging tool capabilities in EDA.
* Detail-oriented and organized, capable of balancing multiple priorities in a fast-paced environment.
The Team You'll Be Part Of
Join a dynamic ApplicationsEngineering team dedicated to customer success and powerful EDA solutions. You'll work closely with fellow engineers, researchers, and tool developers to enable high-performance physical design solutions and push the boundaries of what's possible in semiconductor design.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.