Verification engineer job description

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Seeking Analog/Mixed-Signal Verification Engineer to define, verify and debug Analog and Mixed Signal Integrated circuits intended for Automotive and Industrial systems. In this role you will determine best modeling and simulation practices, including the use of behavioral models and object-oriented test benches used to develop advanced sensors. Candidate should have strong technical and communication skills.
You will:
Lead top level and block level verification of sensor IC'sResponsible for all aspects of design verification from initial plan to completed verification report.Assist Systems/Design Engineers in top-down chip architecture development and feasibility. Generate object-oriented System Verilog Testbenches for Analog IP verification Includes creation of Scoreboard, Sequencer, Driver, MonitorCreation class objects to allow for easier verification by other team members Translation of Jama based requirements to verification tests.Verification and documentation of ISO26262 Hardware Safety RequirementsAssertion development to enforce analog and digital requirements.Regression testing Train engineers to read analog schematics and extract functionality for generation of models.Verify integrated circuit blocks such as amplifiers, comparators, precision front ends, oscillators, regulators, A/D and D/A converter models with their corresponding analog netlists.Generation of top-level netlist for verification within the cadence mixed signal environment.Use various software environments for the behavioral modeling and verification of complex mixed-signal integrated circuit systems.

Qualifications:
BSEE, MSEE (preferred) with 5+ years of experience in analog/mixed signal IC design verification Ability to clearly communicate ideas and concepts.Proven track record of leading a verification with zero bugs.Proficient using Cadence design and Math works MBD tools.Use of scripting languages to facilitate the regression testing of designs.In depth understand of System Verilog including RNM coding, creation of objects, virtual interfaces Sufficient understanding of analog/mixed signal design practices to allow for creation of logic, dc and timing accurate models. Able to solve challenging problems during verification and debug Experience modeling mixed signal blocks including bias networks, regulators, oscillators, bandgaps, filters, OTA's, data converters.

#LI-MR1

At Allegro, we are committed to providing a harassment-free environment of mutual respect to fuel innovation through inclusive thought collaboration. Allegro is an Equal Opportunity Employer and does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, physical or mental disability, national origin, veteran status, parental status, or any other basis covered by appropriate law. Allegro makes hiring decisions based solely on qualifications, merit, and business needs at the time.

Infinera is the global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10 Tier 1 service providers and 6 of the top 7 ICPs. We design, develop and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine network. Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world's largest and most demanding networks that generate billions in service revenue for our customers.
Responsibilities:

* Contribute to verification infrastructure development for complex ASICs.
* Develop test plans based on functional requirements, as well as applicable standards requirements.
* Develop System Verilog/UVM based environment components, for use in the verification of DSP algorithms, ARM-based Control Planes, and/or Networking Protocols.
* Responsible for the definition, development, and execution of self-checking tests.
* Cross-functional support of emulation, firmware development, post-silicon validation, and system integration activities

Requirements:

* Masters degree desired, Bachelor's degree in CS/EE is required.
* 8+ years of relevant experience in ASIC verification field.
* Fluent in System Verilog/UVM and scripting languages such as Python.
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Solid communication skills and ability to interact with cross-functional teams
* Previous experience with ARM Processors, AMBA/AXI, DSP, or Networking a plus but not required

Please note that Infinera has adopted a mandatory COVID-19 vaccination policy to safeguard the health and well-being of our employees. As a condition of employment, our employees are required to be fully vaccinated for COVID-19, unless a reasonable accommodation for a medical/disability or religious basis is approved or as otherwise required by law. Candidates are not required to and must not furnish proof of vaccination or request an accommodation during the application process. Candidates will be required to do so only after a job offer has been extended and prior to their start date if they accept the job offer. A person is fully vaccinated against COVID-19 if the person has received one dose of the Johnson & Johnson COVID-19 vaccine or two doses of the Pfizer or Moderna vaccine and two weeks have passed since receiving the final dose of the vaccine.

#LI- SR2
Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, sex, color, religion, sexual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law. Infinera complies with all applicable state and local laws governing nondiscrimination in employment.

Our Team:

Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading-edge products.

The Wireless and Sensing Product Group located in our San Diego office has unique expertise in system level platform solutions for Touch & Proximity Sensing Products. These are the world's lowest power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance. These ultra-small, feature-rich touch controllers are optimized for a wide range of battery-powered, portable applications such as mobile phones, digital still cameras, media players, GPS, portable computers, handheld gaming devices and other consumer electronics.

Job Summary:

The Verification Engineer is responsible for developing tests and running verification regressions that will ensure the functionality and performance of Semtech's next generation touch and proximity sensing products. Within the verification team and working closely with the rest of the design team, he/she develops, runs, and debugs RTL, gate-level and analog mixed signal tests through the full design cycle.

Responsibilities:
Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS).Run digital/mixed-signal simulation as well as formal verification.Work closely with design team to create verification strategy and detailed verification plan.Develop tests, run regressions, and monitor coverage to ensure tape-out quality.Participate in design or project reviews and support these with verification perspective and schedule/priority assessment.Support post-silicon bring-up and debug, for bench validation as well as automated test equipment (ATE) testing.

Minimum Qualifications:
3+ years' experience in integrated circuit verificationB.S. in EE, M.S. in EE or higher Experience with High-Level Verification Language (HVL) such as System Verilog, PSL, OpenVera with familiarity of object-oriented programming Industrial experience with UVMHands-on experience with digital simulation in both RTL and gate-level flow Analog behavioral model development/verification experience Familiarity with VHDL or System Verilog RNM is preferred

Career Growth Philosophy

At Semtech, we seek innovation and leadership from each and every member of our team. Our goal is to ensure that our talented professionals are equipped with support, resources, and the opportunity to excel. Our pay-for-performance philosophy provides recognition and prestige coupled with a competitive compensation package.

The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description.

All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities.

We are proud to be an EEO employer M/F/D/V. We maintain a drug-free workplace.