Verilog jobs near me - 41 jobs

Santa Clara, CA; Austin, TX; Ottawa, CA; Toronto, CA; Boston, MA Full-time $200,000 - $250,000 base salary + bonus + equity An innovative AI technology company at the forefront of RISC-V CPU and AI platform development is looking for a SoC Chiplet Design Lead to drive the creation of advanced System-on-Chip (SoC) architectures. This pivotal role offers the chance to lead projects that shape next-generation computing solutions, working alongside multidisciplinary teams and cutting-edge technologies. This position is based out of Toronto, Ottawa, Boston, Austin, or Santa Clara, with the possibility of remote work within North America. Key Responsibilities: Oversee the complete lifecycle of SoC chiplet designs, from initial concept through to production. Partner with teams across architecture, systems, and packaging to balance trade-offs in performance, power, cost, and features. Lead efforts in RTL design, design-for-test (DFT) strategies, SoC verification, synthesis, and timing optimization. Collaborate closely with teams in software, hardware, and physical implementation to ensure seamless functionality and integration. Organize and lead technical reviews, offering direction and feedback to engineering teams. Work with project management to establish realistic timelines and deliverables. Manage third-party relationships, ensuring timely integration of vendor and IP components. Stay informed of emerging technologies and industry trends to maintain a competitive edge. Mentor and develop junior engineers, fostering a collaborative and growth-oriented team culture. Qualifications: A degree in Electrical Engineering, Computer Engineering, or a closely related field. 8+ years of hands-on experience in SoC design and development. Demonstrated success leading SoC projects from concept to high-volume production. Expertise in RTL design using Verilog or SystemVerilog. In-depth knowledge of SoC verification tools and methodologies such as UVM, SystemVerilog, or similar. Experience with synthesis, timing analysis, and place-and-route workflows. Familiarity with DFT and debugging strategies in large-scale designs. Strong understanding of embedded software and its interplay with hardware systems. Exceptional problem-solving, organizational, and communication skills. Preferred Skills and Experience: Familiarity with advanced process nodes (e.g., 7nm, 5nm). Knowledge of techniques for low-power design. Experience with high-speed interfaces like PCIe, UCIe, DDR, or Ethernet. Hands-on use of tools from major EDA vendors such as Synopsys, Cadence, or Mentor Graphics.

Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications-whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Location: Palo Alto, CA or Austin, TXHere's what you will do Participate in design and responsible for verifying complete IP macros specifically applicable for Mythic product architecture utilizing the available licensed NVM technologies from foundries Involve in NVM architecture for optimum performance and area of Analog Compute Engine Design and verify the new circuits to handshake with the analog computation and the digital controlling blocks Design, optimize and verify the NVM circuits and functional blocks (including and not limited to high voltage generator block, x-path, y-path, test and peripheral circuits) at the full chip level Responsible for NVM full chip circuit simulation setup, debugging, and verification Responsible for RNM and functional model of NVM circuits for verification Participate in RNM and functional model of NVM circuits for computational software Work closely with the validation engineers to expedite the silicon evaluation process and backend teams for the production qualification releases Here's the background we hope you will have Hands-on experience in NVM embedded or NVM product design, verification and production Hands-on experience in NVM full chip circuit simulation setup, debugging, and verification Hands-on experience modeling circuits using Python, Verilog-A, and System Verilog Real Number Modeling Familiar and hands-on experience some or all memory circuit block design: decoder, high voltage switches, charge pumps, HV and LV regulator, bandgap, high performance low power sense amp, monitoring, and BIST capability Good understanding & knowledge of semiconductor device physics, and advanced process technology Experienced in multiple generations NVM tapeout activities, layout supervision, chip planning, silicon debugging Excellent communication skills, ability to work well across multi-functional teams Fluent in all major CAD tools: SPICE, Cadence Virtuoso, Verilog simulation software Some knowledge of scripting such as Python Must be a self-starter, detail-oriented, and team player Ph.D. or MS degree in EE or related 5-10+ years of semiconductor memory industrial experience The following would be nice to have, but is not required Experience working at fluid fast-paced startups Experience in process integration, semiconductor reliability and product qualification of NVM technology Experience in Semiconductor Emerging Non-volatile Memory Technologies such as RRAM, MRAM and others Experience in cross-functional team development with a multi-technology foundry environment At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully. At Mythic, we pride ourselves in creating a culture where all employees feel valued and appreciated for the diverse perspectives and backgrounds they bring to the team. We aim to hire smart people, give them the resources they need to do their job well, and then leave the rest up to them. We celebrate individual differences and encourage people to be comfortable bringing their authentic selves to work. At the end of the day, we are committed to building a diverse workforce where everyone belongs. Mythic is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application!

Who We Are Applied Materials is a global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips - the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world - like AI and IoT. If you want to push the boundaries of materials science and engineering to create next generation technology, join us to deliver material innovation that changes the world. What We Offer Salary: $124,000.00 - $171,000.00 Location: Santa Clara,CA You'll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible-while learning every day in a supportive leading global company. Visit our Careers website to learn more. At Applied Materials, we care about the health and wellbeing of our employees. We're committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits. Position Overview We are seeking an experienced FPGA Design Engineer with strong expertise in Xilinx Zynq SoC/MPSoC platforms and practical experience in camera sensor interfaces and image processing pipelines. The ideal candidate will design, implement, and optimize FPGA-based solutions for real-time imaging applications. The candidate will play a key role in developing FPGA-based imaging systems and supporting hardware bring-up for new boards. Key Responsibilities FPGA & Zynq Development * Design and implement FPGA logic using Vivado, IP Integrator, and Vitis. * Develop RTL modules in VHDL/Verilog for Zynq PL or Xilinx FPGA. * Build and integrate custom IP cores and AXI interfaces. * Implement HW-SW co-design using ARM processors on Zynq SoCs. * Implement xDMA, memory IP to realize data transfer between PS and PL. * Implement high-speed IO to realize data transfer between different FPGAs. CMOS Sensor & Image Processing * Integrate and interface camera sensor in FPGA. * Develop and optimize real-time image processing pipelines for: Image filtering, conversion, scaling, Frame buffering and memory management. * Implement hardware accelerators to realize high frame rate application. PCB Bring-Up * Participate in FPGA-related PCB bring-up: power sequencing, voltage validation, clock bring-up. * Debug hardware issues using multimeters, oscilloscopes, chipscope. * Validate board-level interfaces such as DDR, high-speed IOs, I2C, UART, SPI. * Work closely with hardware engineers on schematics, layout reviews, and FPGA pin assignment planning. * Support signal integrity, timing, and high-speed routing considerations during board development. Verification, Testing & Debugging * Create simulation testbenches and verification plans. * Validate designs on Zynq evaluation boards (ZCU102, custom boards). * Perform hardware debugging using ILA, oscilloscopes, and logic analyzers. * Conduct performance tuning for timing closure, throughput, latency, and resource utilization. System Integration * Work with embedded developers to integrate FPGA logic with Linux or bare-metal applications. * Configure PS-PL interfaces, DMA and memory controllers. * Collaborate in developing end-to-end imaging systems (sensor, FPGA, ARM, image processing). Documentation & Collaboration * create & maintain documentation for design specifications and development workflows * work on test plan, test procedures, test fixture and test report. * Participate in design reviews and cross-functional team collaboration. Required Skills & Qualifications * Bachelor's/Master's degree * 5 - 8 years of experience in EE / Computer / Embedded HW or related field. * Strong experience with development of Xilinx Zynq UltraScale+ and FPGA. * Proficiency in FPGA design flows, and Embedded system integration. * Experience with CCD sensor interfaces and image processing. * Solid knowledge of AXI, xDMA, frame buffers, DDR and high-speed IO. * Good knowledge of digital electronics, schematics, and board-level design. * Strong debugging skills using ChipScope and lab equipment. * Understanding of timing analysis, CDC, and performance optimization. Soft Skills * Strong self-motivation and strong problem-solving and analytical mindset. * Ability to work cross-functionally with hardware and software teams. * Good communication and documentation skills. * Self-directed and able to handle multiple tasks or fast-paced development cycles. Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members. In addition to a comprehensive benefits package, candidates may be eligible for other forms of compensation such as participation in a bonus and a stock award program, as applicable. For all sales roles, the posted salary range is the Target Total Cash (TTC) range for the role, which is the sum of base salary and target bonus amount at 100% goal achievement. Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law. In addition, Applied endeavors to make our careers site accessible to all users. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_****************, or by calling our HR Direct Help Line at ************, option 1, and following the prompts to speak to an HR Advisor. This contact is for accommodation requests only and cannot be used to inquire about the status of applications.

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering We are seeking a highly skilled and versatile engineer who thrives at the intersection of RTL design and CAD automation. This role is ideal for someone who understands RTL workflows deeply and can build scalable automation solutions to streamline design and debug processes. You'll work closely with CPU design teams to support RTL development, triage issues, and enhance productivity through tooling and scripting. Key Responsibilities * Define and develop methodologies to build scalable, efficient CPU designs * Support RTL development and debug workflows across CPU design teams. * Maintain and enhance RTL databases and repositories using GIT and other version control systems. * Triage RTL issues and collaborate with design teams to resolve them efficiently. * Develop and maintain automation scripts and tools (primarily in Python) to improve RTL workflows, verification, and regression systems. * Interface with CAD teams to align RTL tooling with broader design infrastructure. * Contribute to continuous integration and build systems for RTL environments. * Document workflows, tools, and best practices for internal teams. Required Qualifications * Strong experience in RTL design (Verilog/SystemVerilog) and understanding of CPU microarchitecture. * Solid knowledge of RTL databases and version control systems (GIT). * Proven ability to triage RTL issues and support design/debug workflows. * Advanced scripting skills in Python; familiarity with other scripting languages (TCL, Perl, Bash) is a plus. * Experience with CAD tools and automation frameworks in a hardware design environment. * Familiarity with CI/CD pipelines and build systems for RTL. * Excellent problem-solving and communication skills. Minimum Qualifications: * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $198,700.00 - $298,100.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers.

Description Ventana is building the highest-performance RISC-V CPUs on the planet-designed for data center, AI, and edge workloads, with real silicon, not slideware.Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64-bit ARM server processor (X-Gene at AppliedMicro)-bringing decades of CPU innovation to a clean-slate, open-standards future. You can check us out here: Ventana Micro - YouTubeCPU/SOC Power Analysis & Optimization Engineer: For this role, the candidate must have strong analytical skills and background in power, micro-architecture and scripting to support the following activities on CPU, Compute Subsystem, and SOC designs: Characterization and development of dynamic power estimation and management features Develop energy models for early power estimation, what-if analysis and power targets Support RTL and gate-level power rollup and analysis Analyze various workloads to identify power reduction opportunities Evaluate, evangelize, and implement power optimizations in both RTL and gates Identify best power sign-off tests to improve power analysis coverage Develop flows & heuristics to accelerate power triage on large power data sets Present power results on a regular basis Qualifications Required: 8+ years industry experience with high performance CPU or GPU, memory subsystem, or related system-level designs Bachelors or Masters degree in related engineering field Strong domain knowledge of computer architecture Knowledge of low power ASIC design and implementation techniques Ability to work independently and across geographies Excellent communication skills, self-motivated and well organized Skills Desired: Verilog/SystemVerilog development experience Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems Experience with a broad range of high frequency design considerations (timing, multiple clock domains, clock distribution) including power. Experience with typical front-end tools including: Verilog simulators, waveform viewers, and linting tools, as well as logic synthesis and place and route Experience in compiled and/or interpreted (Python, perl) languages Experience in product level power budgeting and projection Experience in Joules, PowerArtist, PTPX or similar power analysis tools Experience in data mining applications to power modeling & triage Experience in power use-case definition and analysis Experience in post-silicon power correlation is a plus Experience in power management techniques is a plus BASE SALARY RANGE $105,000 TO $260,000 per year EEOE Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law.COVID-19 Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/ business partners. NOTICE: External Recruiters/ Staffing Agencies: Ventana Micro instructs agencies not to engage with its employees to present candidates. Employees are not authorized to enter into any agreement regarding the placement of candidates. All unsolicited resumes received as gratuitous submissions. We reserve the right to directly contact any candidate speculatively submitted by a third party. Such contact will not constitute acceptance of any contractual arrangement between Ventana and the agency, and Ventana will not be liable for any fees should it choose to engage the candidate's services. All external recruiters and staffing agencies are required to have a valid contract executed by Ventana's CFO.Please Note: Fraudulent job postings/job scams are increasingly common. Our open positions can be found through the careers page on our website.

DIGITAL DESIGN ENGINEER Matrix is always looking to hire outstanding team members that share our passion for providing exceptional technical solutions to our customers. CONTRIBUTE? Mission: By designing RF-front and back-end systems that can be integrated into various platforms, you will help us fulfill our mission of developing, integrating, and transitioning advanced multi-sensor military capabilities. How: By using industry best practices and being part of a team that: refines system requirements, creates a system-level design, and then creates, tests, and fields various military systems. WHAT SKILLS ARE NEEDED? Required: Ability to write VHDL (required) and Verilog (desirable) code in support of design and development of digital signal processing systems. Proficiency in all aspects of FPGA design and verification, familiarity with FPGA timing and resource optimization, familiarity with Vivado/ISE, Plan Ahead, Quartus, and Modelsim. Ability to develop architectures from high level requirements documents as well as the ability to document and present coded algorithms. Demonstrate good verbal and written communications skills and Microsoft Office proficiency. Successful applicants will possess a Bachelor's or Master's degree, with 5+ years experience with BSEE, or 2+ years with MSEE. Applicants must be US citizens capable of obtaining and maintaining a US DoD security clearance. Desired or Will Train: Preferred capabilities include digital and/or RF circuit design, embedded microcontroller and Linux driver experience. WHO IS MATRIX RESEARCH? Matrix Research is an employee-owned, small business advancing the State of the art in radar systems, radio frequency, and sensor exploitation technologies. Two thirds of our staff hold advanced degrees in Engineering, Mathematics, or the Physical Sciences. Our programs span basic research through the demonstration and low-rate production of advanced sensing systems, subsystems, and components. WHY WORK WITH US? We work with a purpose: Make the world safer through the development and delivery of advanced technologies. We work as a team: We are a collaborative company comprised of highly-educated industry leaders in radar systems, image and signal processing, machine learning, hardware development, and software engineering. We support our employees with industry-leading benefits: As an employee-owned company, we embrace quality benefits, including a 20% no-match-required retirement plan, accrued 4 weeks of vacation annually, substantially-subsidized health and dental insurance, discretionary annual bonuses, and many more. We support our employees with work/life flexibility: We offer a hybrid remote work environment for most positions and hourly pay for all positions - ensuring individuals are fairly compensated for hours worked while supporting a flexible work commitment. We transform ideas into reality: Our programs range from groundbreaking research to field deployment of advanced systems developed inhouse. DISCLAIMERS Matrix Research is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, marital status, veteran's status, disability, sexual orientation, gender identity, national origin or any other protected class set forth by federal or state law, or for inquiring about, discussing, or disclosing compensation. Matrix is a Drug-Free Workplace This job description is designed to provide general guidance in job tasks and is not meant to be all-inclusive of the responsibilities, duties, and skills required of this position. As business demands and needs change, the essential functions of this position may be updated to reflect the needs of Matrix Research, Inc. Job Posted by ApplicantPro

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. CPU Memory Systems RTL Lead will drive the development of Tenstorrent's next-generation CPU RTL. This position requires a deep understanding of CPU design including Architecture, RTL, Design Verification, Physical Design Flow. The ideal candidate will drive the team building, the microarchitecture specification, RTL design, and verification. This role is Remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Define and develop microarchitecture specifications for CPU (loadstore, data prefetch, cache coherency protocol, shared cache, etc…). The specification includes not only design, but also comprehensive analysis / strategy for verification and PPA (power, performance, area) closure. Define and develop interface between CPU core and external memory subsystem. This drives the definition of bus interface protocol including cache coherence protocol. The candidate will be responsible for the quality of RTL including design verification and PPA closure. This includes writing RTL, reviewing / refining unit verification environment, applying right RTL optimization to control PPA. To maximize the team's output, the candidate actively uses AI tools to accelerate the CPU design process. Experience & Qualifications: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Proven track record of memsys RTL design (e.g., loadstore) for high-performance CPU. Deep understanding of design verification strategy and trade-offs for verification methodology (simulation, formal, various checkers, etc…). The candidate should understand how to verify if your design complies with certain memory ordering rules. Deep understanding of CPU microarchitecture and PPA trade-off. Deep understanding of memory ordering model. Basic understanding of AMBA CHI protocol is preferred. Basic understanding of RISC-V Architecture is preferred. Proficiency in hardware description languages (HDLs) such as Verilog or VHDL. Excellent problem-solving abilities and analytical skills. Strong communication skills, with the ability to convey complex technical concepts to diverse audiences. Ability to work collaboratively in a team-oriented environment and across multiple disciplines. Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills As a Senior Manager in Silicon Design Validation, You lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products. Your role provides strategic oversight and technical direction across the full post-silicon lifecycle, from first silicon arrival to production release. Key Leadership Areas: Technology Enablement & Learning Culture Fostering a learning environment where engineers gain hands-on experience with FPGA architectures and foundational IP blocks such as SERDES (PMA/PCS), DDR memory (DDR4, LPDDR4, DDR5), DPHY, PLLs, DSPs, MIPI, Fabric, and I/O subsystems. Validation/Characterization Strategy & Execution Overseeing the validation and characterization of analog, digital, and mixed-signal IPs, ensuring robust coverage from initial silicon bring-up through production qualification. Planning & Infrastructure Development Guiding the development of validation plans, including bench hardware and software requirements, and ensure the team has the necessary tools and infrastructure to execute effectively. RTL Development for Test Enablement Supervising the creation of custom RTL test logic to support targeted validation and characterization efforts, enabling deeper insight into IP behavior. Silicon Bring-Up & Debug Leadership Driving the bring-up of new silicon products, driving validation and debug activities to assess IP functionality and performance. This includes characterizing datasheet parameters, performing statistical analysis of measured data, and overseeing datasheet preparation. Cross-Functional Collaboration Acting as the central liaison between design, verification, manufacturing, test, quality, and marketing/application teams, ensuring alignment and smooth transition from silicon arrival to product release. Customer Support & Issue Resolution Providing leadership in resolving post-release customer issues, coordinating with internal teams to ensure timely and effective solutions. You Have… 15+ years of experience in silicon validation, including 3-5 years in a leadership role. Master or Bachelor's degree in Electrical Engineering with a strong passion for engineering and management in silicon design validation. Proven track record in managing complex validation projects and leading cross-functional teams. Deep expertise in high-speed SerDes interface characterization and protocol compliance testing (e.g., PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, CSI/DSI-2, USB, DisplayPort, HDMI). Strong background in high-speed board design, signal integrity evaluation, and debug. Proficient in Verilog/VHDL and FPGA design implementation using industry-standard tools. Skilled in test automation development using Python and Perl. Solid understanding of statistical analysis and tools such as JMP and R. Hands-on experience with bench equipment including BERT, VNA, oscilloscopes, and protocol analyzers. Exposure to FPGA-based emulation and prototyping environments. Excellent written and verbal communication skills for effective collaboration across teams. Highly self-motivated, proactive, and strong in critical thinking and problem-solving. Who Are We? At Lattice, we're a collaborative and solutions-driven team that values innovation, problem-solving, and having fun along the way. We specialize in developing low-power, programmable logic technologies that power a wide range of applications-from the Edge to the Cloud. Our products and solutions span differentiated programmable logic devices, system-level solutions, design services, and IP licensing. As the leader in low-power programmable technology, we help solve complex customer challenges across communications, computing, industrial, automotive, and consumer markets. What sets us apart is our deep technical expertise, long-standing customer relationships, and commitment to world-class support. Together, we're enabling a smarter, more secure, and connected world. Join Team Lattice…and help us continue to drive innovation that creates a smarter, better-connected world. Together, we enable what's next. What are you waiting for? Apply today! At Lattice, we believe great engineers come from diverse backgrounds. Even if your experience doesn't check every box, we encourage you to apply. This role offers a unique opportunity to grow your skills in a supportive environment where learning is part of the journey. With the depth and breadth of knowledge on our team, Lattice is a great place to build your expertise and take your career to the next level

Job Description We're seeking an Embedded Systems Engineer with a passion for secure hardware design and cryptography. In this role, you'll work at the intersection of hardware and software, contributing to the architecture and implementation of hybrid cryptographic systems that protect data at the chip level. Responsibilities Design and implement hybrid cryptographic solutions within secure hardware architectures (e.g., hardware root of trust). Develop co-design modules for cryptographic algorithms, optimizing for performance and resource usage. Implement HDL modules (VHDL/Verilog) and associated embedded software in C and Python. Conduct integration and validation of cryptographic components in embedded environments. Participate in system-level testing, verification, and performance analysis. Support threat modeling and design reviews to enhance security robustness. Prepare design documentation, test reports, and implementation guides. Collaborate with multidisciplinary teams across hardware, software, and cybersecurity. Qualifications Master's degree in Electrical/Computer Engineering, Embedded Systems, or equivalent. Proficient in HDL (VHDL/Verilog), C, and Python. Strong understanding of cryptography and secure hardware principles. Experience with simulation, verification, and embedded software integration. Detail-oriented, self-motivated, and collaborative in cross-functional environments. Preferred / Plus Knowledge of post-quantum cryptography or hardware security primitives. Experience with hardware/software co-design tools and secure coding standards.

Senior RTL Design Engineer Remote / work from home US Citizen or US Permanent Resident Full-time/employee + Benefits + 401k + Stock Options Job Responsibilities: Participate in architectural feasibility studies Develop micro-architecture specifications based on the SoC requirements Design, implement and integrate complex SoC blocks Develop block-level test cases to deliver fully functional designs Develop synthesis constraints and resolve timing issues Resolve Lint, CDC, and DFT related issues Identify and resolve RTL and GLS failures at block and chip level Participate in ECO implementation Assist with silicon bring-up Skills & Experience: BSEE/MSEE with 10+ years of SoC design/architecture experience RTL Design including HVLs and HDLs (SystemVerilog, Verilog) Third Party IP Integration experience Logic synthesis and static timing analysis SoC design flow including chip-level design, block/IP design and behavioral modeling Modeling SoC architectures with FPGAs Working knowledge of standard bus protocols such as AXI/AMBA/TileLink Experience with RISC-V architecture Working knowledge of PCIe and DDR Clock domain crossing methodologies Scripting languages such as Python, Perl, Tcl, shell, etc. Strong familiarity with EDA tools Strong problem solving and debugging capabilities Working knowledge of SoC design with CHISEL is a plus Asynchronous logic design is a plus

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills Key Responsibilities Strategic Leadership: Define and execute the quality and validation vision for Radiant design tools. Build and mentor a high-performing team across QA, test automation, and validation. Develop KPIs and quality metrics aligned with business goals and product roadmaps. Software Quality Management: Own and drive software test strategies including functional, regression, performance, integration, and system-level testing. Develop and drive implementation of white-box (component-level) and black-box (flow-level) testing for Lattice's Radiant Software tool-chain Establish quality gates and CI/CD validation pipelines to accelerate delivery without compromising product integrity. Partner with DevOps to evolve test infrastructure, tools, and frameworks for scale and speed. Process and Compliance: Implement and enforce best practices for software quality across Agile and DevOps environments. Ensure compliance with industry standards and regulatory requirements (e.g., ISO, IEC, functional safety for automotive/industrial use cases). Cross-Functional Collaboration: Work closely with software engineering, architecture, and product teams to ensure testability, coverage, and defect prevention. Act as a key stakeholder in product release readiness reviews, quality assessments, and customer escalation triage. Qualifications Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related field. 12+ years of experience in software engineering, with at least 5 years in QA leadership roles. Deep expertise in software validation for complex EDA or embedded software tools (experience with FPGA or ASIC design tools is highly preferred). Proven success leading geographically distributed teams and managing large-scale test infrastructure. Hands-on experience with automated testing, CI/CD systems (e.g., Jenkins, GitLab CI), and scripting languages (Python, Shell, etc.). Strong knowledge of system-level validation, performance testing, and test planning in Agile environments. Familiarity with industry standards such as ISO 26262, DO-254, or IEC 61508 is a plus. Preferred Qualifications Experience with Lattice Radiant or similar FPGA development environments (e.g., Quartus, Vivado, Libero). Knowledge of Verilog, VHDL, simulation, synthesis and place and route toolchains. Prior experience integrating software quality practices in safety-critical or highly regulated domains. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit ******************** You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills Lattice Semiconductor is seeking a Principal RTL Engineer to join the EDA tools development team in Pune. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow. Accountabilities: Lead the design and development of FPGA debug engine in Lattice EDA suite. Architect and refactor the FPGA debug IP and guide the UI team to enhance existing functionality and new features. As a principal RTL Engineer, you will work closely with marketing requirements and generate functional architecture and specifications for new FPGA debug IP functionality and guide the QA teams and ensure that implementations match design intent. Mentor and guide junior RTL & UI engineers working on FPGA debug IP, fostering a culture of continuous improvement and innovation. Maintain high standards of architecture, implementation quality, performance, and reliability. Improve development methodologies and processes. Qualifications Master's in Electrical engineering/Computer engineering or related field with 12+ years of experience in RTL System Design and EDA experience. Strong communication skills. Expertise in HDL languages (Verilog/System-Verilog and VHDL). At least 15 years of Hardware design experience. At least 10 years of Hardware Design experience using FPGAs. At least 5 years on FPGA debugging methodologies. Proficiency in synthesis tools. Proficiency in simulation tools from leading EDA vendors. Proficiency in testbench/test-vector creation. Proficiency in C/C++ , TCL, Python languages. Proficiency in protocols such as Serdes interface, Ethernet, PCIe or Memory DDR is required. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit ******************** You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > Analog Mixed Signal Design Qualcomm's Mixed-Signal PHY design team is actively looking for analog and mixed-signal circuit designer to work on SerDes PHY designs. This designer will be involved in delivering next-generation PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-edge CMOS process technology nodes at 7nm and beyond. Design goals also include low-power analog designs to address Qualcomm's wireline interface need. Job Description The primary responsibility of this position entails working within a team to deliver analog and mixed-signal transistor level circuit designs along with supervising physical layouts of the high speed, low-power PHY SerDes blocks. Experience with >32Gbps transceiver or clocking design is highly desired Minimum Qualifications: * Bachelor's Degree in Electrical Engineering with 2+ years of experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET and 2+ years of ASIC design, verification, or related work experience. OR Master's degree in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience. OR PhD in Electrical Engineering or related field. * 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL). Preferred Qualifications: * PhD in Electrical Engineering or related field. * 2+ years of experience in analog/mixed-signal integrated CMOS circuit design for a specific area (e.g., VCO, PLL, and DLL design, Audio CODEC and Class D Audio amplifier design, Delta-Sigma, SAR ADCs, Current-Steering DACs, high speed DDR PHYs, high-speed SERDES). Principal Duties and Responsibilities: * Uses appropriate tools or databases to contribute to architecture and circuit designs for one or more blocks; participates in design reviews. * Works with layout teams to oversee block-level layout of one or more blocks. * Defines and runs own simulations and analyses (e.g., power, performance) on designs; documents and utilizes results to improve and verify designs. * Programs and runs tests to identify bugs in own work and helps more junior team members with the same; debugs most issues and escalates highly complex issues. * Consults with internal or external users as directed to assist with implementation and achieve goal alignment. * Maintains understanding of one's technical domain and builds understanding of other domains to ensure integration with different components. * Writes detailed technical documentation and design descriptions to guide users and/or customers. * Collaborates with team members to generate ideas. Level of Responsibility: * Working under some supervision. * Taking responsibility for own work and making decisions with limited impact; impact of decisions is readily apparent; errors made typically only impact timeline (i.e., require additional time to correct). * Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area. * Working within prescribed budget and resources. * Completing most tasks with multiple steps which can be performed in various orders; some planning and prioritization must occur to complete the tasks effectively; mistakes may result in some rework. * Exercising creativity to draft original documents, imagery, or work products within established guidelines. * Using deductive problem solving to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be required. * May be solicited during strategic planning period. The responsibilities of this role do not include: * Providing supervision/guidance to others. * Influence over key organizational decisions. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $115,600.00 - $173,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers.

Shift5 is redefining the future of onboard operational technology (OT). As a fast-growing scale-up, we specialize in cutting-edge cybersecurity, predictive maintenance, and compliance for OT systems across defense, aerospace, and rail. We are a team of passionate, innovative professionals who thrive in a collaborative environment, driven by a shared mission to revolutionize how fleets operate. By unlocking and democratizing the vast potential of onboard OT data, we help our customers' fleets run smarter, safer, and more efficiently. Ready to be part of the next frontier in transportation and critical infrastructure? Come join us. Our Values: Mission First Mindset: We exist to protect the service members who defend our nation and secure the critical systems that keep our economy moving. Relentless Innovation: We are motivated by the challenge of solving the toughest problems facing transportation and defense industries. Data Driven Decisions: We make decisions rooted in data. Giving our team and stakeholders a more informed perspective possible when lives and missions are on the line. Shift5 is looking for a Firmware (FPGA) Detection Engineer to join our growing Detection Engineering team. You'll be crucial in designing and developing firmware that unlocks critical data streams for our DoD and commercial customers. If you're low ego, thrive on new challenges, and enjoy collaborating with a driven team, Shift5 could be a great fit. In this role you will be expected to: Architect and define FPGA-based detection capabilities which identify anomalies, unexpected protocol behavior, and threatening behavior in serial buses communications. Integrate detection capabilities with data acquisition and transmissions capabilities. Design and model detection logic for avionic serial busses (e.g., MIL-STD-1553, ARINC 429) in Simulink, and use HDL Coder to automatically generate, verify, and implement this logic on FPGAs. Manage the full model-based design lifecycle for serial bus detections: from algorithm conception and simulation to hardware implementation and in-system validation. Perform investigations of real-world anomalies across OT communication buses, using your protocol expertise to enhance detection algorithms. Work with hardware validation and software QA engineers to conduct rigorous testing, including hardware-in-the-loop (HIL) validation for FPGA designs. Collaborate with vulnerability researchers to translate novel exploit techniques into detectable signatures suitable for FPGA-based serial bus monitoring. Read technical documentation such as avionic standards, and device datasheets to inform your algorithm and model design. Troubleshoot and resolve issues across hardware, firmware, and software. Document your algorithms, models, and verification results for both technical and non-technical audiences. Be ready to learn and be flexible, contributing to a wide variety of work in support of Shift5 priorities. Work from Shift5 HQ in Rosslyn VA, 2-3 days a week, and occasionally travel ( We're looking for someone who is/has: BS or MS in Electrical Engineering, Computer Engineering, or a related field. 3+ years of experience in FPGA design and testing, preferably with VHDL. Proficiency with model-based design using MATLAB, Simulink, and HDL Coder for targeting FPGAs. Experience with serial bus protocols (MIL-STD-1553, ARINC 429, Ethernet, CANBUS/J1939, ASCB) Experience integrating HDL Coder outputs with FPGA development toolchains for synthesis, place-and-route, and timing closure. Strong understanding of VHDL/Verilog for integration and debugging purposes. Knowledge of AXI4 and AXI4-Stream protocols. Experience with scripting languages (TCL, Bash, Python, etc.). Experience designing HDL simulations (ModelSim, GHDL, or similar). Experience with embedded software development (C, C++, Rust, or similar). Comfortable debugging firmware, software, and hardware issues. Proficient with the Linux command line environment. Experience with Git or similar version control, and CI/CD automations. Experience with protocol analysis tools and oscilloscopes for validating serial bus communications (e.g., protocol analyzers, digital storage oscilloscopes with serial decode capabilities) A solid grasp of cybersecurity concepts as they apply to embedded and RF systems. A US Government Security Clearance or the ability to obtain one. Preferred Qualifications: Experience with formal FPGA design verification is a plus. Experience with Linux kernel driver development is a plus. Experience with inline IPS firmware development experience. Familiarity with System-on-Chip (SoC) architectures and interfacing FPGA logic with embedded processors. Protocol or firmware reverse engineering experience. Compensation & Benefits: Base Salary: $100,000-$175,000 Bonus program and equity in a fast-growing startup Competitive medical, dental, and vision coverage for employees and their families Health Savings Account with annual employer contributions Employer-paid Life and Disability Insurance Uncapped paid time off policy Flexible work & remote work policy Tax-deferred public transit benefits with Metro SmartBenefits (DC/MD/VA) We are committed to building an inclusive culture of belonging that embraces the diversity of our people and represents the communities in which we work and the customers we serve. We know the happiest and highest performing teams include people with diverse perspectives and ways of solving problems. We strive to attract and retain talent from all backgrounds and create workplaces where everyone feels empowered to bring their full, authentic selves to work. Shift5 is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sexual orientation, gender identify, national origin, disability, age, marital status, ancestry, projected veteran status, or any other protected group or class. Privacy Policy and Notice for Shift5, Inc. Job Applicants, Employees & Contractors

Description Ventana is building the highest-performance RISC-V CPUs on the planet-designed for data center, AI, and edge workloads, with real silicon, not slideware.Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64-bit ARM server processor (X-Gene at AppliedMicro)-bringing decades of CPU innovation to a clean-slate, open-standards future. You can check us out here: Ventana Micro - YouTube Processor Performance Engineer will be tasked to: Critically review Design Specifications Refine Performance Modeling infrastructure and near cycle accurate models Define (and develop as necessary) applications, benchmarks, and micro-benchmarks on which to measure performance Analyze and verify important performance characteristics at multiple levels of simulation, as well as with prototyping platforms and silicon. Track results over time and quickly identify unexpected regressions. Work with Core and Noncore Architects and the RTL Design team to pinpoint performance opportunities and develop approaches to address them Help specify performance monitoring hardware support Collaborate with our Software team on: Characterization and optimization of key software libraries and middle-ware (e.g. JVM) Compiler/toolchain optimization/tuning guidelines for our microarchitecture Application-level workload characterization/optimization Qualifications Required: In Depth understanding of both the RISC-V ISA and our Core and Subsystem microarchitecture Recently responsibility for microarchitecture/design or a combination of performance modeling, analysis, validation, and correlation for high performance CPU or GPU, memory subsystem, or related system-level designs Domain expertise in computer architecture concepts Ability to work independently and across geographies, with a strong passion for developing excellent products Bachelors or Masters degree in a related engineering field Skills Desired: C/C++/System-C modeling of near cycle accurate simulators Industry experience with CPU microarchitecture (e.g. ISAs including: x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems. Working knowledge of compiler technology and optimization techniques Verilog/ SystemVerilog development experience Experience in compiled and/or interpreted (Python, perl) languages, especially with respect to processing large, complex data sets and extracting meaningful information EEOE Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law. COVID-19 Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/ business partners. NOTICE: External Recruiters/ Staffing Agencies: Ventana Micro instructs agencies not to engage with its employees to present candidates. Employees are not authorized to enter into any agreement regarding the placement of candidates. All unsolicited resumes received as gratuitous submissions. We reserve the right to directly contact any candidate speculatively submitted by a third party. Such contact will not constitute acceptance of any contractual arrangement between Ventana and the agency, and Ventana will not be liable for any fees should it choose to engage the candidate's services. All external recruiters and staffing agencies are required to have a valid contract executed by Ventana's CFO. Please Note: Fraudulent job postings/job scams are increasingly common. Our open positions can be found through the careers page on our website.

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills Responsibilities Develop characterization test plans using established methodologies targeted on chip IP functions and features. Execute characterization of target chip IP features using wafer-level ATE, package-level ATE, and package-level bench platforms across process, temperature, and voltage conditions. Apply statistical analysis on collected characterization data to define key product datasheet parameters and report out results. Identify and analyze to root cause product marginalities, communicating and coordinating root cause closure to appropriate cross-functional team (eg. Applications Engineering, Design Engineering, etc.) Design and implement test circuits using FPGA fabric and embedded IP. Develop bench automation and data collection scripts and programs. Design and develop ATE and bench HW. Drive all product issues to resolution. Plan and execute testing of samples (ie. AS, ES), ensuring timely delivery of tested samples to internal and external customers. Analyze and report out on test yield and test time. Required Skills 3+ years individual contributor in Product Engineering, Si Validation / Characterization, RTL Design, or Design Verification BS degree (ECE, CoE, EE, Physics) Good working knowledge of semiconductor devices and test methodologies Experience in ATE test program development and integration, experience on Nextest Magnum and Advantest T2K preferred Experience in hardware development (bench board) Experience in IC validation and characterization using various bench tools (i.e. Oscilloscope, Pattern Generators, Data Timing Generator, Multimeters, etc) Experience with WAT/etest, wafer sort, package assembly, final test (i.e. full backend IC process) Experience in Programmable Logic is desired Experience in RTL Design, Design Verification an advantage Knowledge in test, DFT methodologies (ie. scan, BIST), and fault grade methodologies an advantage Knowledge in Hardware Description Language such as Verilog or VHDL an advantage Knowledge in programming languages (ie. Python, C++) Knowledge of Statistical Process Control Proficient in the use of statistical analysis SW (ie. SAS JMP, R) Knowledge in Yield Analysis Excellent verbal and written English skills. Demonstrated ability to work with multiple groups and across cultures Good analytical and problem solving abilities Strong Windows, Unix, and MS Office skills Curious with strong self-motivation to learn and explore

ELIGIBILITY: US Citizen CLEARANCE: Secret Clearance required. Ability to obtain Top Secret Clearance. VERIFICATION: Successful Full Scope Background Check Required. Engineer / Senior Engineer / SME I / SME II DESCRIPTION: TECHFORGE Solutions, a TECHFORGE company, is looking for an experienced Secure Systems Design & Test Engineer to join our team in the Dayton, OH office. You will take complete, end-to-end ownership of interactions with USG program offices as well as component, weapon, and sensor system manufacturers in technical interchange meetings and Program reviews to achieve a technically acceptable secure system design for Anti-Tamper implementation. You will lead the analysis of systems for potential export programs, conduct vulnerability analyses of system level implementations and architectures; as well as develop and review Program Protection Plans, Science & Technology Protection Plans, and Anti-Tamper plans and annexes to provide technical written feedback, evaluations, and guidance to USG programs and commercial clients. You will evaluate protection methodologies and devices used to prevent exploitation of US system technology alone or with a team of engineers. You will participate in the verification testing of secure system design and testing, to include anti-tamper protection treatments and implementations. You will produce test reports on protected systems of interest and develop/apply your skills in circumventing AT protection techniques to better harden customer systems. The ideal candidate must be self-motivated and explore alternatives for quickly prototyping to validate hypothetical architectures or solutions. They must be passionate about protecting customer systems from exploitation. RESPONSIBILITIES: The SME will serve as an advising consultant working directly with the client's team of hardware and software subject matter experts (SME), the program Technical Lead, and the client Program Manager to support various project-specific research scope and deliverables providing value to our customers. You will also contribute to the growth of both our government customer and internal R&D capability to help advance Anti-Tamper and Trusted / Secure Export technologies. As a TECHFORGE team member, the SME will work alone or on a team within an AGILE system / product development life cycle, supporting activities which include requirements creation, sprint planning, and grooming, etc. to collaborate across time zones via MS Teams collaboration tools, and frequent video conferences. Some travel will be required to meet with the remote engineering and software development teams. TRAVEL: The role will be hybrid with some remote work options available; but, will require frequent time in the office with clients and team members in Dayton, OH, as well as some travel out of state as necessary for team & client meetings, and/or presentations. REQUIREMENTS: All candidates must be U.S. Citizens. All candidates must pass a background check. Must have active (or recently inactive) Secret clearance to start. The ability to obtain a Top Secret security clearance is also required, but may not be necessary for every project. Must be able to travel up to 10% (CONUS) as needed. Excellent oral and written communication skills. Ability to work in a remote, collaborative, team environment. Experience with remote collaboration tools (e.g., Teams, WebEx, Meet, Zoom, etc.). Perform other related duties as assigned. REQUIRED SKILLS: Must possesses the capability to organize plans and programs specifying the nature and sequence of actions to be accomplished in a specific project. Must possesses 5+ years of professional experience in Systems integration/systems level engineering experience with complex computer systems, weapons or sensor systems, including electronic design, analysis or system test or system integration. Familiar with electronic components found in modern systems, including Integrated Circuit, FPGAs and ASIC technologies. Knowledgeable of protection features and devices. Familiarity with DOD 5000 series, DOD 5200 series, Defense Acquisition policy, and Horizontal Protection of DoD Critical Program Information. Knowledgeable of system development processes and system level testing. Willing to engage groups across the government microelectronics space, anti-tamper organizations, and commercial AT suppliers to support technical roadmaps for technology trade space and selection. Willing to learn the associated tools for tasking, planning, researching and data routing as applied within the scope of the program. Support development of Program Protection Plans, Science and Technology Protection Plans, and Anti-Tamper plans and annexes, and other project documentation. Excellent analytical, critical thinking and problem-solving skills. Excellent verbal communication skills, comfortable interacting with technical peers and the ability to work as part of a team is required. Ability to communicate technical issues clearly and effectively and execute assignments with little supervision and actively participate in a collaborative team environment. Proficient technical writing skills and the ability to produce reports and presentations. Ability to generate and evaluate technical documents and reports. Ability to create technical briefings and materials and effectively present technical material to both technical and non-technical stakeholders. Willing to travel to CONUS and/or OCONUS work locations 2-4 times per year. MINIMUM EDUCATION: Bachelor's degree in Physics, Engineering Physics, Computer Science, Computer Engineering, Electronics or Electrical Engineering, Mechanical Engineering or similar field and at least 8 years of related professional experience; or 4 years of professional experience with a Masters, or 2 or more years professional experience with a PhD. DESIRED SKILLS: Advanced hands-on experience with system development processes and system level testing a plus. Microelectronics/Embedded Systems security experience such as Defensive Cyber or Anti-Tamper. Experience in FPGA or ASIC development including requirements definition, design, simulation, implementation, tape out, and testing. Proficient in Hardware Description Languages (HDL) such as VHDL or Verilog and associated software tools. Proficient in embedded software development, debug, and testing. Experience with Model-Based Systems Engineering (MBSE) tools and techniques. Experience working in a classified research environment. Prior experience implementing systems engineering tools and techniques. Strong interest in in learning new tools, languages, workflows, and philosophies SALARY: 145,000 - 195,000. The listed salary range for this role is intended as an estimate based on the role's location, expectations, and responsibilities. When extending an offer, TECHFORGE takes many factors into consideration which include, but are not limited to, the candidate's education, training, work experience, and key skills related to the role. ======================================= OUR COMPANY TECHFORGE Solutions (TFS) is an Aerospace and Defense company located in Dayton, Ohio. Our amazing team is consistently delivering solutions to our customers' most challenging problems in core business areas including aerospace systems, autonomy, business intelligence, cloud technologies, cybersecurity, data science, and enterprise risk governance. TECHFORGE is a leader in innovation and technology commercialization. At TECHFORGE Solutions we are committed to providing a work environment that is exciting, challenging, and deeply rewarding. We value our employees and provide industry leading benefits, rewards, and a healthy workplace to support them. Due to the nature of our work, U.S. citizenship is required for employment, and employees may be required to obtain and maintain a security clearance. To learn more about us, please visit: ****************************** Equal Opportunity Employer: TECHFORGE is committed to providing equal opportunity to applicants and employees without regard to race, religion, color, national origin, sex, age, disability, pregnancy, genetic information, marital status, veteran status, sexual orientation, or any other characteristic protected by law. This policy applies to all areas of employment including recruitment, placement, training, transfer, promotion, lay off, termination, pay, and other forms of compensation and benefits. The Company will comply with its legal obligation to provide reasonable accommodation to qualified individuals with disabilities. We are committed to providing accessibility to employment opportunities for person with disabilities. If you require assistance to navigate or apply to our careers site, please send your request to: HR@techforge.solutions. Work Environment and Responsibilities Every candidate is expected to be able to handle multiple priorities and the demands of a fast-paced environment. This role will operate in a professional office environment; whether on-site, remote, hybrid, or client-site. Physical Environment and Responsibilities The physical demands described here are representative of those that must be met by a team member to successfully perform the essential functions required of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions of this job. Other Duties/Changes This role description is not intended to cover or contain a comprehensive listing of all duties, responsibilities or activities that are required of a team member for this job. Duties, responsibilities, and job-related activities may change at any time. At any point in time, the essential functions and primary duties associated with this position will be the principal, major or most important duties, responsibilities and activities that the employee is expected to perform as determined and directed by management. TECHFORGE SOLUTIONS is an EEO Employer - M/F/Disability/Protected Veteran Status View all jobs at this company

We are seeking a highly skilled FPGA Engineer to join our expanding High-Frequency Trading team. In this role, you will be at the forefront of financial technology, working on cutting-edge hardware solutions that power our ultra-low-latency trading systems. As a member of our expert team, you will be responsible for designing, implementing, and optimizing FPGA-based systems to improve trading performance, reduce latency, and increase throughput. This is a unique opportunity to combine your expertise in hardware engineering with the fast-paced world of financial markets. You will play a critical role in developing the infrastructure that underpins our competitive advantage, working collaboratively with software engineers, quantitative researchers, and traders to deliver high-performance, reliable solutions. What You'll Be Doing: Design, develop, and optimize FPGA-based solutions for ultra-low-latency trading systems. Work closely with software developers to integrate FPGA solutions into broader system architectures. Implement hardware-accelerated solutions for protocol parsing, order entry, and market data processing. Perform timing analysis, timing closures, resource optimization, and latency measurements to ensure peak performance. Collaborate with traders and researchers to identify opportunities. Monitor and troubleshoot system performance in a live trading environment. What We Look For In You: Bachelor's or Master's degree in Electrical Engineering or related field. Proficiency in Verilog/SystemVerilog. Experience with FPGA design tools (Xilinx Vivado or Altera Quartus). Experience with FPGA debugging tools (ILA, SignalTap,Chipscope). Experience with Simulation tools (e.g Questa/ModelSim). Nice-to-have: Programming and Scripting skills in tcl/C++/Python is a bonus. Experience with peripheral integration (10G PHY/MAC, PCIe). Experience with custom network stack implementations (TCP/UDP). Why Should You Join Our Team? Great challenges with fast feedback loops and top-notch analytics A welcoming group of highly qualified international professionals Cutting-edge hardware and technology Work remotely from anywhere in the world Access any of our global offices anytime Flexible schedule 40 paid days off Competitive salary

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills Lattice is seeking candidates for the position of Sr EDA SW Dev Engineer. This is a full-time position located in Pune, India. Accountabilities: Develop and deliver state-of-art Lattice FPGA software tool for small, mid-range and large FPGA products. Develop software capabilities for next generation of Lattice FPGA products. Support and maintain existing Lattice FPGA design and debug tools. Learn and contribute to Spec and Plan process - review marketing requirement documents, generate functional specifications and developer unit test plans to ensure quality software. Improve development methodologies and processes. Qualifications: BS/MS/PhD Electrical Engineering or Computer Science 5+ years of experience in large-scale software development for engineering application domains, preferably in FPGA/ASIC Design Automation Must be proficient with C++. Modern C++ proficiency is a plus Familiarity with Verilog/VHDL Strong background in Software Architecture, object-oriented programming, data structures and algorithms, Design Patterns Experience of working on multiple platforms - at least Linux and Windows - is required. Knowledge of shell, Tcl or Python scripting is a plus. Familiarity with commercial FPGA software tools and design flow is a plus. Knowledge in FPGA logic design is a plus. Must be detail oriented and possess independent problem-solving skills. Must be able to drive projects and lead a discussion. Strong written and verbal communication skills, and collaboration skill with the ability to work with multiple groups.