Senior verification engineer jobs in Groton, MA

Senior Systems Engineer | Remote | $110k-$130k About the Role Our client is seeking a senior systems engineer to be their go-to person. Looking for someone ready to design cloud-first environments. The role combines high-level systems engineering and solution architecture. You will be handling critical escalations, run client assessments, and architect end-to-end solutions- particularly around azure. What You'll Do: Lead technical assessments and turn business needs into secure, scalable infrastructure designs. Design and deploy solutions in Azure, M365, and Intune/Endpoint Manager (Autopilot, compliance/CA policies, app packaging). Redesign and optimize networks - firewalls, switching, routing, VLANs - for performance and security. Use CLI confidently for common network tasks. Troubleshoot loops, configure switches, and support HP/Dell switching and SonicWall/Fortinet firewalls. Administer Windows Server roles, Office 365, and core Azure services. Build and harden servers/workstations for reliability and security. Create accurate SOWs outlining deliverables, timelines, and technical requirements. Own complex L3+ escalations with deep-dive troubleshooting and root-cause analysis. Produce clear, repeatable documentation for architectures and deployments. Mentor junior/mid-level engineers to elevate team skill. What you Bring: 5+ years in a Managed Service Provider (MSP) or high-volume IT support environment Strong experience with Windows Server (2016/2019/2022), Active Directory, Group Policy, DNS Microsoft 365 administration and security Azure infrastructure and virtual networks (AZ-104 or higher preferred) Virtualization tools: VMware, Hyper-V, AVD Networking: Layer 2/3, VPNs, firewalls (SonicWall, Meraki, etc.) Scripting & automation Strong documentation habits and familiarity with ConnectWise Confident communication with the ability to explain solutions to non-technical users Bonus if you have: AZ-305, CCNA/CCNP, or any cybersecurity-related certs Perks & Benefits: Full Benefits Package Mental Health Days PTO Equal Opportunity Employer

Veteran-Owned Firm Seeking a System Cybersecurity Engineer II for an Onsite Assignment at Hanscom Air Force Base (AFB) My name is Stephen Hrutka. I lead a Veteran-Owned management consulting firm in Washington, DC. We specialize in Technical and Cleared Recruiting for the Department of Defense (DoD), the Intelligence Community (IC), and other advanced defense agencies. At HRUCKUS, we support fellow Veteran-Owned businesses by helping them recruit for positions across organizations such as the VA, SBA, HHS, DARPA, and other leading-edge R&D-focused defense agencies. We seek to fill a System Cybersecurity Engineer II role at Hanscom Air Force Base (AFB) in Bedford, MA. The ideal candidate must have an active Secret Security Clearance, a DoD 8570.01-M MGT512-compliant certification, and experience with LogRhythm. Required qualifications include either a BA/BS with 10 years of cybersecurity experience (5 in DoD), an MA/MS with 5 years (3 in DoD), or 15 years of related experience with proper certifications, including 5 years in DoD. If you're interested, I'll gladly provide more details about the role and discuss your qualifications further. Thanks, Stephen M Hrutka Principal Consultant HRUCKUS LLC Executive Summary: HRUCKUS is seeking a System Cybersecurity Engineer II with Secret Clearance for a role at Hanscom Air Force Base (AFB) in Bedford, MA. Position Overview: The System Cybersecurity Engineer II will be able to perform work that involves ensuring the confidentiality, integrity, and availability of systems, networks, and data through the planning, analysis, development, implementation, maintenance, and enhancement of information systems security programs, policies, procedures, and tools. Position Responsibilities: Supporting the system/application authorization and accreditation (A&A) effort, to include assessing and guiding the quality and completeness of A&A activities, tasks, and resulting artifacts mandated by governing DoD and Air Force policies (i.e., Risk Management Framework (RMF). Recommending policies and procedures to ensure the reliability of and accessibility to information systems and to prevent and defend against unauthorized access to systems, networks, and data. Conducting risk and vulnerability assessments of planned and installed information systems to identify vulnerabilities, risks, and protection needs. Promoting awareness of security issues among management and ensuring sound security principles are reflected in organizations' visions and goals. Conducting systems security evaluations, audits, and reviews. Recommending systems security contingency plans and disaster recovery procedures. Recommending and implementing programs to ensure that systems, networks, and data users are aware of, understand, and adhere to systems security policies and procedures. Participating in network and systems design to ensure implementation of appropriate systems security policies. Facilitating the gathering, analysis, and preservation of evidence used in the prosecution of computer crimes. Assessing security events to determine impact and implementing corrective actions. Ensuring the rigorous application of information security/cybersecurity policies, principles, and practices in the delivery of all IT services. Perform the Information System Security Engineer (ISSE) duties in an Information Assurance Workforce System Architecture and Engineering (IASAE) position as outlined in AFI 33-200, AFI 33-210 and AFMAN 33-285 for assigned systems. Perform the Information System Security Manager (ISSM) duties as outlined in DoDI 8510.01 for assigned systems/applications. Perform the Information System Security Officer (ISSO) duties as outlined in DoDI 8510.01 for assigned systems/applications. Other duties as assigned. Required Qualifications: Clearance: Active Secret Security Clearance BA/BS degree with a minimum of 10 years of cybersecurity experience, including 5 years supporting the Department of Defense (DoD); or an MA/MS degree with at least 5 years of experience, including 3 years in a DoD environment; or 15 years of directly related experience with the appropriate certifications, of which a minimum of 5 years must be within the DoD. DoD 8570.01 MMGT512 compliant certification. Experience with LogRhythm. Lab/SCIT management experience preferred. Experience with the Risk Management Framework (RMF). Details: Job Title: System Cybersecurity Engineer II Location: Hanscom Air Force Base, MA Clearance Requirement: Active Secret Clearance Assignment Type: Full-time, Onsite Salary Range: $130,000 - $140,000 per year

Our client is seeking a highly skilled Systems Engineer to provide advanced technical and systems engineering expertise across complex defense programs. This role involves applying engineering principles and innovative problem-solving to develop, evaluate, and enhance systems and technologies that support mission objectives. The ideal candidate will have a strong foundation in systems engineering, digital engineering, and Model-Based Systems Engineering (MBSE), with the ability to influence strategy and guide program decisions through analytical insight and technical leadership. Essential Duties and Responsibilities (but not limited to): Apply and adapt engineering principles, standards, and methods to address unique and complex technical challenges. Research, design, and develop solutions that extend existing engineering concepts and technologies. Provide expert technical consultation and guidance to senior management and program stakeholders. Integrate digital engineering and MBSE practices throughout all phases of the system lifecycle. Evaluate new technologies, engineering methodologies, and emerging industry trends for potential application. Conduct systems-level analysis, trade studies, and performance evaluations to support mission and design objectives. Lead or contribute to the development of new engineering standards, methods, or models. Assess risks, recommend mitigations, and support system and program risk management activities. Analyze system performance and ensure alignment with cost, schedule, and security requirements. Incorporate resiliency and system security principles into engineering designs and architectures. Conduct feasibility assessments, concept development, and decision analyses for proposed solutions. Perform validation and verification of system designs, develop testing criteria, and evaluate results. Provide systems integration oversight to ensure interoperability among subsystems and external interfaces. Prepare technical documentation, reports, and presentations summarizing findings, recommendations, and performance metrics. Support communication system integration and open architecture frameworks (e.g., Open Mission Systems) for NC3 modernization efforts. Qualifications: Bachelor's degree in Engineering or a related technical discipline (advanced degree preferred). Minimum of 10 years of experience in systems engineering or a related engineering field. Proven expertise applying engineering theories and principles to solve complex technical and operational problems. Experience supporting system design, development, testing, and sustainment activities. Strong understanding of digital engineering and MBSE concepts and tools. Ability to assess and evaluate the impact of emerging technologies, methodologies, and strategies. Skilled in developing technical recommendations, performing trade analyses, and influencing engineering decisions. Excellent communication, analytical, and technical writing skills. Adaptable and proactive, with the ability to learn and lead in a dynamic environment. Must be a United States Citizen with an active Top Secret clearance and SCI eligibility. POST-OFFER BACKGROUND CHECK IS REQUIRED. Digital Prospectors is an Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other characteristic protected by law. Digital Prospectors affirms the right of all individuals to equal opportunity and prohibits any form of discrimination or harassment. Come see why DPC has achieved: 4.9/5 Star Glassdoor rating and the only staffing company (< 1000 employees) to be voted in the national Top 10 ‘Employee's Choice - Best Places to Work' by Glassdoor. Voted ‘Best Staffing Firm to Temp/Contract For' seven times by Staffing Industry Analysts as well as a ‘Best Company to Work For' by Forbes, Fortune and Inc. magazine. As you are applying, please join us in fostering diversity, equity, and inclusion by completing the Invitation to Self-Identify form today! ******************* Job #18001

Job Title: Artificial Intelligence Engineer Location: Boston/Hybrid Type: Full-time The Role We're looking for a hands-on AI Systems Engineer to own the deployment, integration, and support of AI-powered tools (LLMs, Copilot, Claude, etc.) while keeping enterprise infrastructure running smoothly in a professional services environment. What You'll Do Build, deploy, and maintain AI applications that supercharge legal and knowledge workflows Manage and optimize cloud (Azure/M365) and on-prem environments (Windows/Linux, VMware/Nutanix, AD, SQL) Write production-grade Python/PowerShell, automate everything, consume REST APIs and SDKs Craft high-impact prompts and fine-tune LLM usage Partner with architecture and ops leadership on strategy, resilience, and continual improvement Research emerging tech and drive efficiency gains Rotate in 24×7 on-call (escalation/triage) You Bring 7+ years supporting mission-critical IT in professional services or similar Real experience with modern LLMs and AI tools Strong Python or PowerShell + familiarity with ML libraries Deep experience with Azure, M365, Active Directory, virtualization, networking, backups Proven ability to solve complex problems independently and communicate clearly Bachelor's in CS or related field

Our client is building a cutting-edge AI platform for autonomous system design and operations. The platform understands workload characteristics, adapts to dynamic environments, and continuously optimizes multiple layers of the AI stack to meet performance and cost objectives. It can design and deliver system optimizations 10-100x faster than human experts, compressing weeks of effort into just hours. The technology is grounded in over a decade of award-winning research originating from the Networks and Mobile Systems group at MIT CSAIL. The company has been founded to commercialize this technology, with an initial focus on AI inference optimization - spanning the inference engine as well as higher-level orchestration layers such as scheduling, routing, autoscaling, and GPU selection. As one example, the platform recently discovered a completely novel request routing algorithm for distributed LLM serving, achieving more than a 10x reduction in latency slowdown while reducing GPU costs by over 20%. This solution was discovered and validated in simulation in just two hours - a task that would typically take an experienced systems researcher weeks. About the Role Our client is hiring an AI Systems Engineer who combines strong systems engineering instincts with a genuine enthusiasm for AI. This is not a role for someone who is skeptical of AI's role in systems development; the ideal candidate actively embraces AI as a collaborator and a tool for discovering new ideas in computer and networked systems. In this role, you will help design, build, and ship the first versions of the company's product. You'll work closely with the core engineering team to translate deep research into robust, production-ready systems, with the broader goal of transforming how computer systems are designed and optimized using AI. What You'll Do Design, build, and deploy core components of the AI-driven optimization stack. Collaborate with the founders to translate research insights into real, usable systems. Own critical pieces of the platform: routing, scheduling, autoscaling, hardware selection, inference engine integrations, and more. Build prototypes quickly, validate them, and iterate based on user and customer feedback. Help establish technical architecture, coding standards, and best practices for a high-velocity engineering culture. Set up development workflows, infrastructure, tooling, and deployment pipelines. Evaluate third-party tools/services and make key build vs. buy decisions. Document design and development work and help establish the foundation for future engineering hires. What We're Looking For Because this field is new, we don't expect years of experience. We're looking for engineers with great systems intuition, intellectual curiosity, and a strong desire to embrace AI-driven engineering. Strong signals include: Experience with AI inference, distributed serving, model optimization, and related topics. Hands-on with vLLM, PyTorch, Triton inference server, Ray Serve, or other inference frameworks Experience with GPU optimization, kernel design, CUDA programming, and low-level systems performance engineering Strong Python and PyTorch fundamentals Comfort in building large-scale, high-performance distributed systems PhD or equivalent experience (PhD or equivalent + ~5 years is a good sweet spot) Dislike for rigid bureaucratic engineering processes, but appreciation for disciplined engineering rigor.

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at ************** and on LinkedIn and Twitter (X). Analog Devices, Inc is looking for a Senior Analog Design Verification Engineer with deep technical expertise and strategic vision to lead verification efforts for complex analog and mixed-signal ICs to join our Automotive Connectivity Design Verification team. Our team is responsible for complete design verification for our automotive connectivity silicon products including block-level, chip-level, and system-level verification. The team works closely with our design and product test engineering teams to maximize the quality of our silicon products. Key Responsibilities * Own and drive the end-to-end verification strategy for high-performance analog and mixed-signal IPs and subsystems. * Architect and implement advanced verification methodologies, including assertion-based verification, coverage-driven verification, and mixed-signal co-simulation. * Lead the development of behavioral models, testbenches, and automated regression environments using Verilog, SystemVerilog, and scripting languages. * Perform deep analysis of simulation results, including statistical and corner case evaluations (Monte Carlo, mismatch, PVT). * Collaborate with design leads to influence architecture decisions and ensure verification coverage of critical design features. * Interface with design teams, digital verification teams, and post-silicon validation to ensure seamless integration and testability. * Mentor junior engineers and contribute to the development of internal best practices, tools, and reusable verification IP. Job Requirements * Master's or Ph.D. in Electrical Engineering * 7+ years of relevant experience in mixed signal design verification. * Advanced knowledge of design verification flows including UVM methodology and mixed signal co-simulation. * Expert-level proficiency in simulation tools including Spectre (or similar) and SystemVerilog. * Strong understanding of analog design fundamentals * Demonstrated leadership in verification planning, execution, and cross-functional collaboration. * Candidates should have strong analytical and problem-solving skills and the ability to work on multiple projects as required * Strong interpersonal, teamwork and communication skills are required #LI-PG1 For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days The expected wage range for a new hire into this position is $125,250 to $187,875. * Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. * This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. * This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a SOC Core Data Path Design Verification Engineer on AMD's Strategic Silicon Solutions (S3) team, you will plan, create, and execute tests, testbenches, and verification environments to integrate IP blocks into complex SOC projects. You will help create custom advanced SOCs for external customers such as Sony (PlayStation 5), Microsoft (Xbox Series X), and Valve (Steam Deck) along with customers outside the game console space. You will collaborate closely with architects, design engineers, and software teams to ensure design functionality, performance, and quality for cutting-edge SOC products. THE PERSON: You are passionate about modern processor architecture, digital design, and SOC-level verification. You thrive in complex technical environments, are eager to understand legacy processes to improve them, and excel at problem-solving. You communicate effectively across global teams and are motivated to learn and innovate continuously. KEY RESPONSIBILITIES: * Collaborate with architects, hardware engineers, and others to understand the new features to be verified * Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases * Estimate the time required to write the new feature tests and any required changes to the test environment * Build the directed and random verification tests * Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues * Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: * Strong background in SOC and IP-level ASIC verification. * Proficient in debugging RTL using industry-standard simulation tools. * Hands-on experience with UVM-based testbenches in both Linux and Windows environments. * Skilled in Verilog, SystemVerilog. * Experience developing and maintaining UVM verification frameworks, test environments, and automation flows. * Knowledge of distributed compute environments, workflow automation, and regression management. * Familiarity with simulation profiling, acceleration, or HLS tools/processes. * Strong C++ programming skills, especially on Linux; Windows exposure is a plus. * Working knowledge of SystemC and TLM methodologies. * Scripting experience in Perl, Ruby, Makefile, or shell. * Leadership or mentorship experience is considered an asset. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, or a related discipline. LOCATION: * Boxborough, MA This role is not eligible for Visa Sponsorship. #LI-IA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

HPR is a leading provider of high-performance and ultra-low latency electronic trading and capital markets infrastructure solutions offered as a managed service. Our cutting-edge technology is used by tier-1 financial institutions to monitor and execute trades rapidly and efficiently. As we continue to innovate and grow, we're searching for a forward-thinking Senior Design Verification Engineer to help us build the future of capital markets infrastructure. As a Senior Design Verification Engineer at HPR, you will: Verify and maintain high-performance FPGA compute and networking systems used in electronic trading Own the verification process from specification, test planning, and testbench development through execution and coverage closure Partner with design engineers to review and execute comprehensive test plans Create and maintain reusable verification components and testbenches written in SystemVerilog Lead and mentor junior engineers, promoting our culture of continuous learning and collaboration Contribute to improving our verification processes, tools, and methodologies Required Qualifications BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related 5+ years of experience in design verification for FPGAs or ASICs Proficiency in SystemVerilog for verification Familiarity with advanced verification methods, including constrained randomization, functional coverage, and assertion-based checking Experience with industry-standard simulation and debugging tools (e.g., VCS, Verdi) Comfortable working in a Linux environment Strong problem solving, debugging, and communication skills Desired Qualifications Deep understanding of computer architecture and digital design concepts In-depth knowledge of networking protocols (IP, TCP, UDP) Experience verifying designs with high-speed interfaces (PCIe, Ethernet, and/or DDR) Familiarity with C programming and scripting in Python and/or Perl Compensation: In compliance with Massachusetts law, the anticipated annual base salary range for this position is $ $159,300 to $215,000. Please note that this range represents the expected base salary for this role at the time of posting. The final offer may vary based on factors such as the candidate's experience, skills, and qualifications. This range does not include other forms of compensation such as potential bonuses, equity, or benefits. This position requires being on-site at our office in Needham, MA full-time (5 days per week) HPR does not currently provide employment sponsorship

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Meet the Team Acacia, now part of Cisco, provides innovative silicon-based high speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world's best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your Impact The ASIC Design Verification Co-Op Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products. This role is focused on verifying highly-complex ASICs that are used in these next-generation telecom systems. The engineer in this role uses sophisticated verification techniques to complete advanced individual contributions to the projects. There are opportunities to develop process improvements for the team and to coordinate with other engineers within the engineering community to add value to the ASIC projects. This engineer must be a fast-learning, self-motivated effective person who is able to operate in a fast-paced, dynamic and highly technical environment. A successful candidate will be energetic, collaborative and passionate about learning how to deliver the most advanced high speed optical products in the world. Knowledge of object-oriented verification methodologies is required. * Develop detailed and comprehensive test plans * Develop verification test benches * Timely execution of test plans * Assist with chip level design tradeoffs by working with design engineers * Participate in review of design verification coding and coverage metrics * Participate and assist in FPGA emulation efforts * Work collaboratively with team to develop & incorporate latest technologies & processes Minimum Qualifications * Currently enrolled in a full-time graduate program * Knowledge of the latest ASIC verification methodologies, tools and scripting/programming languages * Knowledge of SystemVerilog/UVM, SystemC * Knowledge of C and/or C++ Preferred Qualifications * Knowledge of DSP algorithms and modulation techniques such as QAM * Lab silicon validation experience * Knowledge of Formal Verification methodologies and tools such as Jasper * Ability to work collaboratively across business groups * Excellent communication skills (verbal and written) Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: * 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees * 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco * Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees * Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) * 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next * Additional paid time away may be requested to deal with critical or emergency issues for family members * Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: * .75% of incentive target for each 1% of revenue attainment up to 50% of quota; * 1.5% of incentive target for each 1% of attainment between 50% and 75%; * 1% of incentive target for each 1% of attainment between 75% and 100%; and * Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $44,000.00 - $185,000.00 Non-Metro New York state & Washington state: $44,000.00 - $185,000.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Infrastructure Processor Business Unit, a part of Networking and Processor Business Group, encompasses OCTEON and the award-winning OCTEON Fusion-M product families. The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. As part of the Infrastructure Processor unit at Marvell, you will verify all of the circuitry that goes inside our chips for the general market and for specific customers. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major telecom organization or automotive company, etc. What You Can Expect In this role, the successful candidate will: · Develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers. · Write a verification test plan using random techniques and coverage analysis, and work with designers to ensure it is complete. · Develop tests and tune the environment to achieve coverage goals. · Debug failures and work with designers to resolve issues. Other Skills: · Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision. · Requires the ability to accept and work with differing opinions · Must be able to learn on the fly and work in a fast-paced environment. What We're Looking For Candidate should possess: · Proficiency using C/C++ · Experience with Verilog and SystemVerilog, preferably with UVM. · Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment. · Experience with scripting language such as Python or Perl and EDA Verification tools. · A good understanding of Linux OS. Education: BS or MS is Computer Engineering, Electrical Engineering, or Computer Science with 3+ years of verification and firmware and software development experience. Expected Base Pay Range (USD) 118,500 - 175,380, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at *****************. Interview Integrity As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews. Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SA1

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Custom Compute & Storage (CCS) Business Unit, is one of Marvell's fastest growing business units. In CCS, we focus on helping our customers with their custom designs for cloud-based AI applications as well as customers in the enterprise and carrier markets.Custom Compute & Storage (CCS) Business Unit, is one of Marvell's fastest growing business units. In CCS, we focus on helping our customers with their custom designs for cloud-based AI applications as well as customers in the enterprise and carrier markets. What You Can Expect . * Develop and execute verification plans for ethernet or memory subsystems/ * Create and maintain testbenches and test cases. * Perform functional and performance verification. * Debug and resolve design and verification issues. * Collaborate with design and architecture teams to ensure verification coverage. Other Skills: * Excellent problem-solving and analytical skills. * Strong communication and teamwork abilities. * Develop and execute verification test plans. * Create and maintain testbenches and test cases. * Perform functional and performance verification. * Debug and resolve design and verification issues. * Collaborate with design and architecture teams to ensure verification coverage. Other Skills: * Excellent problem-solving and analytical skills. * Strong communication and teamwork abilities. What We're Looking For . * Bachelor's degree in Computer Science, Electrical Engineering, or related fields and 3+ years of related professional experience. * Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2+years of experience. * Proficiency in SystemVerilog and UVM (Universal Verification Methodology). * Experience with simulation tools (e.g., VCS). * Knowledge of scripting languages (Python, Perl, TCL). * Knowledge in one of the following areas preferred PCIe, Ethernet. UEC, or DDR. Expected Base Pay Range (USD) 118,500 - 175,380, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at *****************. Interview Integrity As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews. Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SA1

Job Description Career Renew is recruiting for one of its clients a Senior FPGA Design Verification Engineer in Dedham, MA. Our engineers redefine what's possible and our manufacturing team brings it to life, building the brains behind the brawn on submarines, ships, combat vehicles, aircraft, satellites, and other advanced systems. We pride ourselves in being a great place to work with this shared sense of purpose, committed to a diverse and exciting employee experience that drives innovation and creates a community where all feel welcome and a part of something amazing. As a Senior Cyber FPGA Design Verification engineer, you'll be a member of a cross functional team responsible for product design from system architecture & requirements allocation through product release and production of cost-sensitive secure products. Requirements Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience. Experience with OVM / UVM design verification methodology: bash/csh, Perl, TCL, Python or similar scripting languages; VHDL or similar hardware description languages. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required. What sets you apart: Experience defining verification methodology for complex FPGAs. Ability to analyze requirements, create test plan, build and set up scalable simulation environments from the ground up using SystemVerilog/UVM Familiarity with testing complex designs, code coverage, functional coverage, assertions. Ability to work in a dynamic environment that includes working with changing needs and requirements. FPGA/ASIC design experience is a plus. Familiarity with Xilinx FPGA & Questa Advanced Functional Verification tools is a plus. Team player who thrives in collaborative environments and revels in team success Benefits An exciting career path with opportunities for continuous learning and development. Research oriented work, alongside award winning teams developing practical solutions for our nation's security Flexible schedules with every other Friday off work, if desired (9/80 schedule) Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more

Job DescriptionzeroRISC zero RISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Led by the founders of the OpenTitan secure silicon project, zero RISC is driving commercial adoption of high assurance software and services rooted in open silicon. Our products forge an immutable connection between hardware and software, enabling users to trust their devices no matter where they're built or where they're deployed. Role Overview As a zero RISC SoC/ASIC Design Verification Engineer, you will develop, verify, and maintain silicon in security-sensitive settings, including root-of-trust technology. You will elevate and solidify zero RISC's status as the leading provider of secure silicon IP by developing essential verification collateral. You will interact directly with zero RISC customers to understand their requirements and deliver solutions benefitting both customer and zero RISC alike. You will participate in the whole chip design process from architecture to tapeout and silicon validation. By engaging with the world's premier open-source silicon community, you will support our mission of open secure silicon everywhere. We're looking for engineers with strong design verification skills (and a long view of secure system architecture) who are also fast, flexible learners and enthusiastic about open source.Key Responsibilities: Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off Build high quality verification environments at the chip/top and block levels following engineering best practices Write thorough verification documentation including test plans Diagnose, debug, and resolve regression failures and other errors Achieve coverage closure Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers What We're Looking For: Bachelor's degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience 4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments Preferred Qualifications (not required): Master's or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experience Knowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs) Knowledge of computer architecture and memory subsystem architectures Experience verifying low power designs Experience with scripting languages such as Python Why Join Us? Your work will directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environments As a seed-stage startup, this role offers significant opportunities for learning and career growth Join a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.

At WHOOP, we're on a mission to unlock human performance. WHOOP empowers members to perform at a higher level through a deeper understanding of their bodies and daily lives. WHOOP is seeking a Senior Embedded Engineer to drive the development and optimization of the hardware systems behind our cutting-edge wearable technology. As a critical member of this team, you will drive the design, development, and optimization of embedded systems that power WHOOP's devices, ensuring they meet the high standards of reliability and performance our members expect. Your expertise will directly impact WHOOP's ability to innovate and deliver transformative experiences. RESPONSIBILITIES: * Drive the development and optimization of the hardware systems behind our cutting-edge wearable technology. * Develop and optimize hardware systems for low-power, resource-constrained embedded environments, ensuring efficient and reliable device performance. * Collaborate with cross-functional teams to define hardware requirements and support the integration of sensors, communication modules, and power management systems. * Design, prototype, and test hardware components to ensure quality, scalability, and functionality align with product goals. * Debug and resolve complex issues across the hardware stack, leveraging advanced diagnostic tools and methodologies. * Support the selection and validation of electronic components, ensuring reliability and performance in real-world conditions. * Contribute to the development and optimization of communication interfaces such as I2C, SPI, UART, and BLE for seamless connectivity. * Conduct hardware performance analysis and testing to meet stringent power and reliability requirements for wearable devices. * Collaborate with manufacturing teams to ensure robust design-for-manufacturing (DFM) and design-for-test (DFT) processes. QUALIFICATIONS: * Master's degree in Computer Engineering, Electrical Engineering, or related technical field or foreign degree equivalent and 6 months experience with developing and debugging embedded hardware and software systems. * 6 months of experience with programming languages (Python or similar); 6 months of experience with C, C++ or other scripting language. * 6 months of experience working with microcontrollers, RTOS, and peripheral interfaces including I2C, SPI, UART, and BLE. * 6 months of experience with low-power design and optimization techniques for battery-powered devices. * 6 months of experience with debugging using tools including oscilloscopes, logic analyzers, and similar equipment. * 6 months of experience solving problems and developing innovative solutions in the wearable or IoT space. * 6 months of experience effectively communicating across technical and non-technical teams. Partial telecommuting permissible from home office within normal commuting distance. Interested in the role, but don't meet every qualification? We encourage you to still apply! At WHOOP, we believe there is much more to a candidate than what is written on paper, and we value character as much as experience. As we continue to build a diverse and inclusive environment, we encourage anyone who is interested in this role to apply. WHOOP is an Equal Opportunity Employer and participates in E-verify to determine employment eligibility. It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability. The WHOOP compensation philosophy is designed to attract, motivate, and retain exceptional talent by offering competitive base salaries, meaningful equity, and consistent pay practices that reflect our mission and core values. At WHOOP, we view total compensation as the combination of base salary, equity, and benefits, with equity serving as a key differentiator that aligns our employees with the long-term success of the company and allows every member of our corporate team to own part of WHOOP and share in the company's long-term growth and success. The U.S. base salary range for this full-time position is $155,000 - $245,000. Salary ranges are determined by role, level, and location. Within each range, individual pay is based on factors such as job-related skills, experience, performance, and relevant education or training. In addition to the base salary, the successful candidate will also receive benefits and a generous equity package. These ranges may be modified in the future to reflect evolving market conditions and organizational needs. While most offers will typically fall toward the starting point of the range, total compensation will depend on the candidate's specific qualifications, expertise, and alignment with the role's requirements.

Systems Engineer Contract-to-Hire Boston-based 1x per week onsite We're looking for a hands-on Systems Engineer with broad experience across Windows Server, Active Directory, virtualization, and endpoint management. You will be responsible for maintaining, supporting, and improving a large and active IT environment. Role Administer and maintain Windows servers, Active Directory, and group policies Support virtualization platforms such as VMware or Hyper-V Manage endpoint systems including SCCM, Intune, and patching cycles Handle backup, monitoring, and basic networking tasks Build and maintain automation scripts for routine tasks and deployments Troubleshoot system issues and implement long-term solutions Participate in projects to modernize and optimize the IT estate Responsibilities Strong hands-on experience with Windows Server and Active Directory Solid knowledge of endpoint management (SCCM, Intune, or similar) Experience with virtualization platforms (VMware or Hyper-V) Familiarity with patch management, backup, and monitoring tools Comfortable with scripting (PowerShell, Python, or similar) Able to work independently and take ownership of issues Exposure to cloud environments (Azure, AWS) is a plus If you're a proactive engineer who enjoys a varied role across servers, endpoints, and virtualization, this is a great opportunity to make an impact. Apply today.

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X). Analog Devices, Inc is looking for a Senior Analog Design Verification Engineer with deep technical expertise and strategic vision to lead verification efforts for complex analog and mixed-signal ICs to join our Automotive Connectivity Design Verification team. Our team is responsible for complete design verification for our automotive connectivity silicon products including block-level, chip-level, and system-level verification. The team works closely with our design and product test engineering teams to maximize the quality of our silicon products. Key Responsibilities Own and drive the end-to-end verification strategy for high-performance analog and mixed-signal IPs and subsystems. Architect and implement advanced verification methodologies, including assertion-based verification, coverage-driven verification, and mixed-signal co-simulation. Lead the development of behavioral models, testbenches, and automated regression environments using Verilog, SystemVerilog, and scripting languages. Perform deep analysis of simulation results, including statistical and corner case evaluations (Monte Carlo, mismatch, PVT). Collaborate with design leads to influence architecture decisions and ensure verification coverage of critical design features. Interface with design teams, digital verification teams, and post-silicon validation to ensure seamless integration and testability. Mentor junior engineers and contribute to the development of internal best practices, tools, and reusable verification IP. Job Requirements Master's or Ph.D. in Electrical Engineering 7+ years of relevant experience in mixed signal design verification. Advanced knowledge of design verification flows including UVM methodology and mixed signal co-simulation. Expert-level proficiency in simulation tools including Spectre (or similar) and SystemVerilog. Strong understanding of analog design fundamentals Demonstrated leadership in verification planning, execution, and cross-functional collaboration. Candidates should have strong analytical and problem-solving skills and the ability to work on multiple projects as required Strong interpersonal, teamwork and communication skills are required #LI-PG1 For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process. Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group. EEO is the Law: Notice of Applicant Rights Under the Law. Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $125,250 to $187,875. Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. This position qualifies for a discretionary performance-based bonus which is based on personal and company factors. This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivated Design Verification Engineer to join our growing team. As a key contributor, you will help develop and execute verification strategies that ensure AMD delivers high-quality, industry-leading technologies to market. The Verification Engineering team fosters continuous technical innovation and supports career development through collaboration and learning. THE PERSON: You are passionate about modern processor architectures, digital design, and verification methodologies. You thrive in a collaborative environment, communicate effectively across teams and time zones, and bring strong analytical and problem-solving skills. You are eager to learn and ready to tackle complex challenges. KEY RESPONSIBILITIES: * Develop and maintain functional and performance verification tests at the core level. * Build testbench components to support next-generation IP. * Maintain and enhance test libraries for IP-level testing. * Create and optimize hardware emulation builds to verify IP functionality and * performance. * Improve emulation environments to accelerate runtime and enhance debug capabilities. * Provide technical support and collaborate with cross-functional teams. PREFERRED EXPERIENCE: * Strong object-oriented programming skills. * Proficiency in UVM, SystemVerilog, and C++. * Background in computing or graphics architectures. * Familiarity with OpenGL, OpenCL, or Direct3D programming. * Experience with ARM protocols is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering This role is not eligible for visa sponsorship. #LI-BS1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. _Applications are accepted until further notice._ _Please_ _note_ _this posting is to advertise potential job opportunities._ _This exact role may not be open today but could open_ _in the near future_ _._ _When you apply, a Cisco representative may contact you directly if a relevant position opens._ **Meet the Team** Acacia, now part of Cisco, provides innovative silicon-based high speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world's best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. **Your Impact** The ASIC Design Verification Co-Op Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products. This role is focused on verifying highly-complex ASICs that are used in these next-generation telecom systems. The engineer in this role uses sophisticated verification techniques to complete advanced individual contributions to the projects. There are opportunities to develop process improvements for the team and to coordinate with other engineers within the engineering community to add value to the ASIC projects. This engineer must be a fast-learning, self-motivated effective person who is able to operate in a fast-paced, dynamic and highly technical environment. A successful candidate will be energetic, collaborative and passionate about learning how to deliver the most advanced high speed optical products in the world. Knowledge of object-oriented verification methodologies is required. + Develop detailed and comprehensive test plans + Develop verification test benches + Timely execution of test plans + Assist with chip level design tradeoffs by working with design engineers + Participate in review of design verification coding and coverage metrics + Participate and assist in FPGA emulation efforts + Work collaboratively with team to develop & incorporate latest technologies & processes **Minimum Qualifications** + Currently enrolled in a full-time graduate program + Knowledge of the latest ASIC verification methodologies, tools and scripting/programming languages + Knowledge of SystemVerilog/UVM, SystemC + Knowledge of C and/or C++ **Preferred Qualifications** + Knowledge of DSP algorithms and modulation techniques such as QAM + Lab silicon validation experience + Knowledge of Formal Verification methodologies and tools such as Jasper + Ability to work collaboratively across business groups + Excellent communication skills (verbal and written) **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to work in the U.S. and/or Canada:** Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: + 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees + 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco + Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees + Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) + 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next + Additional paid time away may be requested to deal with critical or emergency issues for family members + Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: + .75% of incentive target for each 1% of revenue attainment up to 50% of quota; + 1.5% of incentive target for each 1% of attainment between 50% and 75%; + 1% of incentive target for each 1% of attainment between 75% and 100%; and + Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $44,000.00 - $185,000.00 Non-Metro New York state & Washington state: $44,000.00 - $185,000.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.

Job DescriptionAt WHOOP, we're on a mission to unlock human performance. WHOOP empowers users to perform at a higher level through a deeper understanding of their bodies and daily lives. WHOOP is looking for an enthusiastic Senior Embedded Engineer to join our Software Organization as part of the Embedded Engineering team. You will work with Hardware, Signal Processing, Manufacturing and Product teams to develop and deliver against Hardware and Software roadmaps. The Embedded team's mission is to build and deploy stable, accurate, and power efficient firmware platforms for all our in house developed devices via a seamless 24/7 connection and interaction between our mobile apps. At Whoop, the Embedded team is at the intersection of the Hardware and Software domains, bridging the gap between the physical and the digital world. As a Senior Embedded Engineer you will collaborate with a diverse group of the industry's best and brightest engineers in supporting current products, as well as developing new cutting edge products that help our members achieve their health and fitness goals with industry leading monitoring and data analysis.RESPONSIBILITIES: Develop and test firmware in C for WHOOP's product line, including features optimized for low-power performance. Take ownership of complex firmware features and ensure they meet performance, power, and reliability goals. Debug and resolve challenging issues across software, hardware, manufacturing, and system integration. Define, write, and maintain clear technical requirements and documentation. Participate in code reviews to ensure clarity, correctness, and adherence to coding standards. Design and improve firmware self-tests, validation tools, CI workflows, and internal development tools. Support electrical development by evaluating components, bringing up drivers, and contributing to hardware design discussions. Leverage AI as a development tool and share learnings with the team. Collaborate with Electrical, Signal Processing, Mobile, and Manufacturing teams to validate designs and refine interfaces. Mentor teammates by providing guidance on design, implementation, and debugging. Identify opportunities to improve performance, power efficiency, stability, and reliability across the firmware platform. QUALIFICATIONS: Bachelor's or Master's in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 5+ years of embedded firmware development experience. Excellent problem-solving and analytical skills, with the ability to resolve ambiguous issues independently. Excellent interpersonal, written, and verbal communication skills, with experience mentoring and collaborating across teams. Strong experience with electronics debugging tools such as oscilloscopes, multimeters, power supplies, and logic analyzers. Proficient with device driver development and 32-bit RISC architectures such as ARM Cortex. Proficient in C/C++ programming. Strong understanding of electrical engineering fundamentals, with proficiency in reading schematics and hardware specifications. Experience working with operating systems (OS) and real-time operating systems (RTOS). Strong understanding of system communication protocols such as I2C, SPI, USART/UART, and BLE. Experience with version control using git and modern CI/CD workflows. Experience with unit, integration, and functional testing for embedded systems. Experience with Agile software development practices. Experience working on high-volume consumer electronics products preferred. Willingness to act as both a team player and a technical leader. Learn more about our Software Org and how to be successful in your engineering career at WHOOP via our Career Framework. Also check out our AI studio blog here. This role is based in the WHOOP office located in Boston, MA. The successful candidate must be prepared to relocate if necessary to work out of the Boston, MA office. Interested in the role, but don't meet every qualification? We encourage you to still apply! At WHOOP, we believe there is much more to a candidate than what is written on paper, and we value character as much as experience. As we continue to build a diverse and inclusive environment, we encourage anyone who is interested in this role to apply. WHOOP is an Equal Opportunity Employer and participates in E-verify to determine employment eligibility. It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability. The WHOOP compensation philosophy is designed to attract, motivate, and retain exceptional talent by offering competitive base salaries, meaningful equity, and consistent pay practices that reflect our mission and core values. At WHOOP, we view total compensation as the combination of base salary, equity, and benefits, with equity serving as a key differentiator that aligns our employees with the long-term success of the company and allows every member of our corporate team to own part of WHOOP and share in the company's long-term growth and success. The U.S. base salary range for this full-time position is $150,000-$210,000. Salary ranges are determined by role, level, and location. Within each range, individual pay is based on factors such as job-related skills, experience, performance, and relevant education or training. In addition to the base salary, the successful candidate will also receive benefits and a generous equity package. These ranges may be modified in the future to reflect evolving market conditions and organizational needs. While most offers will typically fall toward the starting point of the range, total compensation will depend on the candidate's specific qualifications, expertise, and alignment with the role's requirements. Learn more about WHOOP .