Time study engineer job description
Example time study engineer requirements on a job description
- Bachelor's degree in Industrial Engineering or related field.
- Knowledge of time studies and data analysis.
- Previous experience in a manufacturing environment.
- Proficiency in statistical analysis software.
- Strong numerical and analytical skills.
- Excellent verbal and written communication skills.
- Attention to detail and accuracy.
- Ability to work independently and make sound decisions.
- Strong problem-solving and troubleshooting skills.
- Ability to multitask, prioritize, and manage time effectively.
Time study engineer job description example 1
Peraton time study engineer job description
- Provides ongoing network timing system support, addresses availability issues, overcomes performance problems and provides overall level 3 support to meet SLA requirements
- Support maintenance and upgrades to the for timing network architecture (includes evaluating timing related equipment)
- Troubleshoots and resolves problems to ensure quality transmission service on the timing network
- Reports on overall timing network performance including problem resolution tasks
- Advises customer of network hardware requirements, configurations, and limitations
- Plans implementation of enhancements and upgrades to the timing network
Candidate must be able to:
- When applicable, report to work during non-business hours for emergency situations, working independently for extended durations
- Perform product evaluations and recommendation of products/services to improve timing network performance, redundancy, and resiliency
- Provide technical guidance for directing and monitoring timing/network system operations
- Monitor and respond to complex technical control facility hardware and software problems
- Interface with timing vendor support service groups
- Devise and direct routine testing and perform analysis of all elements of the timing network facilities (including power, software, communications machinery, lines, modems, and terminals)
- Demonstrate proficiency in utilizing software and hardware tools to identify and diagnose problems and factors affecting timing network performance
- Devise work instructions or standard operating procedures for newly installed or changed network systems
- Complete electronic documentation of all work completed
- Must hold at minimum, active/current DoD Secret clearance. With the ability to obtain Top Secret security clearance
- Relevant knowledge and/or experience with Atomic Clock technology (i.e., Cesium, Rubidium or similar), is a plus
- Familiar with any of the following technologies (i.e., SSU-2000, Symetricom 9611B, FiberPlex Frequency Distribution, CommSync II, Cesium Oscillator Microsemi 4500, etc.)
- Experience with wire wrapping and wiring blocks
- Understanding of network timing protocols and timing distribution systems
Education:
BS 2-4 Years, MS 0-2 or HS 8-10
Required Certifications:
DoD 8570 IAT Level II (CCNA Security, CySA+, GICSP, GSEC, Security+, CND, SSCP)
Peraton drives missions of consequence spanning the globe and extending to the farthest reaches of the galaxy. As the world’s leading mission capability integrator and transformative enterprise IT provider, we deliver trusted and highly differentiated national security solutions and technologies that keep people safe and secure. Peraton serves as a valued partner to essential government agencies across the intelligence, space, cyber, defense, civilian, health, and state and local markets. Every day, our employees do the can’t be done, solving the most daunting challenges facing our customers.
An Equal Opportunity Employer including Disability/Veteran.
Colorado Salary Minimum: $50,000Colorado Salary Maximum: $121,400
The estimate displayed represents the typical salary range for this position, and is just one component of Peraton's total compensation package for employees. Other rewards may include annual bonuses, short- and long-term incentives, and program-specific awards. In addition, Peraton provides a variety of benefits to employees.
Time study engineer job description example 2
Vencore time study engineer job description
- Provides ongoing network timing system support, addresses availability issues, overcomes performance problems and provides overall level 3 support to meet SLA requirements
- Support maintenance and upgrades to the for timing network architecture (includes evaluating timing related equipment)
- Troubleshoots and resolves problems to ensure quality transmission service on the timing network
- Reports on overall timing network performance including problem resolution tasks
- Advises customer of network hardware requirements, configurations, and limitations
- Plans implementation of enhancements and upgrades to the timing network
Candidate must be able to:
- When applicable, report to work during non-business hours for emergency situations, working independently for extended durations
- Perform product evaluations and recommendation of products/services to improve timing network performance, redundancy, and resiliency
- Provide technical guidance for directing and monitoring timing/network system operations
- Monitor and respond to complex technical control facility hardware and software problems
- Interface with timing vendor support service groups
- Devise and direct routine testing and perform analysis of all elements of the timing network facilities (including power, software, communications machinery, lines, modems, and terminals)
- Demonstrate proficiency in utilizing software and hardware tools to identify and diagnose problems and factors affecting timing network performance
- Devise work instructions or standard operating procedures for newly installed or changed network systems
- Complete electronic documentation of all work completed
- Must hold at minimum, active/current DoD Secret clearance. With the ability to obtain Top Secret security clearance
- Relevant knowledge and/or experience with Atomic Clock technology (i.e., Cesium, Rubidium or similar), is a plus
- Familiar with any of the following technologies (i.e., SSU-2000, Symetricom 9611B, FiberPlex Frequency Distribution, CommSync II, Cesium Oscillator Microsemi 4500, etc.)
- Experience with wire wrapping and wiring blocks
- Understanding of network timing protocols and timing distribution systems
Education:
BS 2-4 Years, MS 0-2 or HS 8-10
Required Certifications:
DoD 8570 IAT Level II (CCNA Security, CySA+, GICSP, GSEC, Security+, CND, SSCP)
Peraton OverviewPeraton drives missions of consequence spanning the globe and extending to the farthest reaches of the galaxy. As the world's leading mission capability integrator and transformative enterprise IT provider, we deliver trusted and highly differentiated national security solutions and technologies that keep people safe and secure. Peraton serves as a valued partner to essential government agencies across the intelligence, space, cyber, defense, civilian, health, and state and local markets. Every day, our employees do the can't be done, solving the most daunting challenges facing our customers.
An Equal Opportunity Employer including Disability/Veteran.
For Colorado Residents Colorado Salary Minimum: $50,000Colorado Salary Maximum: $121,400
The estimate displayed represents the typical salary range for this position, and is just one component of Peraton's total compensation package for employees. Other rewards may include annual bonuses, short- and long-term incentives, and program-specific awards. In addition, Peraton provides a variety of benefits to employees.
Time study engineer job description example 3
Intel time study engineer job description
The Programmable Solutions Group (PSG) will continue to drive the future for FPGAs and Structured ASICs to build a better tomorrow. By pushing forward in cutting edge technology our work is at the heart of innovation. With a career at Intel you have the opportunity to shape the future for everyone.
As a Full Chip Timing Engineer, you will be developing and executing full-chip timing analysis and timing modeling methodologies for Intel's Programmable Solutions Group's next generation product lines in the world's most advanced process technologies. This will be a fast-paced dynamic environment where you will be part of a high-performance design team working toward next generation FPGA products.
You will work in a hands-on capacity performing full chip timing analysis. You will utilize your extensive design experience and interpersonal skills to efficiently solve technical issues, drive continuous improvement, negotiate and clearly communicate technical tradeoffs with a diverse cross-functional and multi-site team. You will need to work with aggressive schedules as both part of a team and independently.
Your role will include, but not limited to:
Design and Architecture understanding.Interaction with Front End and Back End teams. Knowledge of Clocking and Constraints Development.Understanding extraction issues, design margins, timing signoff and quality checks.Be part of debug and troubleshooting for a wide variety of tasks up to and including difficult, critical design issues and proactive intervention.
Qualifications:
Relevant experience can be obtained through work, classes, projects, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Education Requirement
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
What You'll Bring (Minimum Qualifications)
8+ years of relevant experience, experience should include:
Experience in SoC development.Experience with advanced process nodes (e.g. 32nm and below).Industry standard timing formats such as Liberty, SPEF, Verilog, and SDC.STA / Correlating STA results with Spice.Timing modeling and library QA.Script writing for design automation in one or more of the following languages (Python, Perl, or TCL).Silicon modeling concepts (e.g. AOCV, POCV).
Ways to Stand Out From the Crowd (Experience in one, or more, of the following preferred qualifications is considered a plus factor):
10+ years of SoC Development / Timing Lead Experience.Experience in the completion of several complex multi voltage domain.Common modes of operation, including functional and DFT, for use in constraint review and management.
Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, California, San Jose
Additional Locations:
US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
Business group:
The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.