Principal Hardware Engineer

Principal Design Engineer

Principal Design Engineers

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California

Arteris IP

SALARIES

Arteris IP is helping power the next wave of autonomous driving, 5G and Artificial Intelligence (AI) systems fueling the growth the of the semiconductor industry. Our Network-on-Chip (NoC) interconnect semiconductor intellectual property (IP) is the on-chip communications backbone of most of the world's most important and sophisticated systems-on-chip (SoC). Optimizing on-chip dataflow and connectivity is the cornerstone of our vision for system-on-chip development and assembly. Since our inception in 2003, we have pioneered the development and commercialization of NoC interconnect technology, cementing our position as the world's first and largest commercial NoC interconnect IP company. Our unique technology meets the needs for cache coherent and non-coherent on-chip communications, on-chip data caching, and on-chip data protection to meet functional safety requirements. ARTERIS IP PRODUCTS AND SOLUTIONS Our on-chip NoC-based interconnect IP products make systems-on-chip easier to develop, perform better, and faster to get to market.
The Arteris IP product portfolio meets the needs of design teams creating nearly any type of digital logic SoC with any type of communications semantics. Our seminal FlexNoC Interconnect IP pioneered the market for NoC interconnects and is the industry leader. The highly configurable Ncore Cache Coherent Interconnect IP allows optimal integration of cache-coherent Arm -based processor IP with other cache-coherent and non-coherent IP. The growth of Artificial Intelligence (AI) and Machine Learning (ML) has inspired the creation of two innovative products. The Arteris IP AI Package is an option to Arteris FlexNoC that provides automated means to create complex topologies (meshes, rings, and tori) while adding multicast/broadcast communications, virtual channels, and source-synchronous communications to meet the unique needs of AI/ML chips. The CodaCache Last Level Cache provides a highly configurable cache that can be instantiated anywhere within an SoC interconnect, providing data locality wherever needed. To meet the needs of the new generation of multibillion-transistor chips for automated systems with functional safety requirements, Arteris IP also offers Resilience Packages that provide hardware-based data protection technologies as well as automated diagnostic coverage analysis to help meet requirements ISO 26262 and IEC 61508 functional standards. Resilience Packages are available for FlexNoC, Ncore and CodaCache IP products. Timing closure has become a key design schedule constraint as chips have grown in size and complexity and semiconductor manufacturing process critical dimension have shrunk. To address this, Arteris IP created the PIANO Timing Closure Package which provides physical and timing information about the interconnect to back-end synthesis place and route tools to help ensure faster timing closure.

Founder

10x Group

Ventech

Crescendo Ventures

TVM Capital

Arm Holdings

Synopsys

Qualcomm

DoCoMo Capital

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Chairman, President and Chief Executive Officer

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Rank	City	Avg. salary	Hourly rate
1	Campbell, CA	$176,778	$84.99
2	Austin, TX	$147,961	$71.14

Rank	Job title	Average salary	Hourly rate	Job openings
1	Principal Hardware Engineer	$140,453	$68	-
2	Senior Staff Engineer	$138,301	$66	-
3	Staff Design Engineer	$136,972	$66	-
4	Principal Engineer	$134,769	$65	-
5	Principle Engineer	$132,943	$64	-
6	Lead Hardware Engineer	$131,701	$63	-
7	Senior Principal Engineer	$131,327	$63	-
8	Design Verification Engineer	$127,275	$61	-
9	Senior Hardware Engineer	$121,183	$58	-
10	Principal Electrical Engineer	$121,072	$58	-

Arteris IP principal design engineer salary

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$144,520yearly

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