Senior verification engineer jobs in La Mesa, CA - 486 jobs

A semiconductor technology leader in San Diego seeks a Verification Engineer for its FPGA Prototyping team. This role involves designing verification strategies, collaborating on subsystem requirements, and automating test cases. Ideal candidates should have a strong understanding of SoC verification methods and proficiency in hardware description languages like SystemVerilog.Competitive salary range is between $241,100 and $326,100, with opportunities for hybrid working and a supportive environment for all employees. #J-18808-Ljbffr

Architects, designs, implements, verifies, and optimizes performance and power of GPU cores. Responsible for verification of Graphics IP, and performing pre- and post-silicon verification to verify correctness and ensure performance and power goals are met. Responsibilities Owning and executing on key independent tasks towards program requirements Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area. Working within prescribed timeline requirements and resource constraints Applying independent creative thought to troubleshoot technical problems or deal with novel circumstances. Research through available resources and engagement with various inter-disciplinary teams Using deductive problem solving to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be required. Principal Duties and Responsibilities Applies Graphics knowledge and experience to architect, design, implement, and verify the structure and performance of GPU hardware, drivers, features, applications, and tools. Creates and maintains verification test benches and environments in System Verilog/UVM Create and leverage advanced testing frameworks to generate and recreate real-world system integration conditions Collaborates with Architecture, Software, Firmware, Design, Modeling, Emulation and Post-silicon validation teams to define and develop test methodology and content Participate in GPU architecture, micro-architecture reviews Collect, organize and execute various forms of system level test content including directed testcases, gaming benchmarks, standards compliance testsuites, and system level scenarios Build automation for continue integration and testing based on latest GPU IP Help collect and analyze test results using straightforward statistics and data predictions to track benchmarks and identify issues Works with team members to understand and align on narrow scope of feature development and meet targets. Write technical documentation and feature descriptions for straightforward projects under the direction of a supervisor. Minimum Qualifications Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. OR PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience. Preferred Qualifications 5+ years Hardware Engineering, Software Engineering, Systems Engineering, or related work experience Verification skills: Test planning, Scripting, Simulation, problem solving and debug. System Verilog, UVM, Verilog or VHDL, C/C++ skills required. Constrained random, Functional Coverage development, design debug experience required. Exposure to Emulation/Prototyping Platforms (Veloce, Palladium, Zebu, FPGA) Master's Degree in Electrical or Computer Engineering, Computer Science, or related field. 2+ years relevant GPU experience (either external or internal). Preferred Skills Experience in GPU based verification Experience in system or sub-system level verification Concurrency, Preemption, Stress testing frameworks Testbench Architecture and Implementation GFX API Exposure : Vulkan/DX11/DX12 Exposure Scripting and automation skills (Python, Make, Airflow etc) Embedded FW Development and Debugging Benchmarking and Performance Analysis Windows and/or Linux OS Kernel Architecture C/C++, GNU Toolchain, Visual Studio Formal verification - FPV and DPV experience is a plus Experience with emulation/prototyping/hybrid build and execution flows (Veloce, Palladium, Zebu, Protium, HAPS, qemu) Development of synthesizable transactors, monitors, scoreboards for emulation platforms Embedded FW and/or Kernel level development and debugging skills (C/C++, Makefile, gdb, uboot, uefi, kernel-mode drivers) This role is available in multiple locations at different levels. The compensation range will be determined upon the offer location and title. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may omail disability-accomodations@qualcomm.com for accommodations. Qualcomm will provide reasonable accommodations to support individuals with disabilities to participate in the hiring process. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Pay range and Other Compensation & Benefits: $161,800.00 - $273,400.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is one component of total compensation; Qualcomm also offers a discretionary bonus program and RSU grants. For more details about US benefits, see the internal benefits information. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A leading aerospace company is looking for a Senior Principal Engineer Software in San Diego, CA, to design and develop embedded software systems. Candidates should have a strong background in C/C++ and Python, with at least 8 years of relevant experience. This position requires collaboration in an Agile environment and an active Secret DoD Security Clearance. The salary range is $118,600 - $178,000, plus bonuses and benefits. #J-18808-Ljbffr

pSemi Corporation is a Murata company driving semiconductor integration. pSemi builds on Peregrine Semiconductor's 30‑year legacy of technology advancements and strong IP portfolio but with a new mission-to enhance Murata's world‑class capabilities with high‑performance semiconductors. With a strong foundation in RF integration, pSemi's product portfolio now spans power management, connected sensors, optical transceivers, antenna tuning and RF frontends. These intelligent and efficient semiconductors enable advanced modules for smartphones, base stations, personal computers, electric vehicles, data centers, IoT devices and healthcare. From headquarters in San Diego and offices around the world, pSemi's team explores new ways to make electronics for the connected world smaller, thinner, faster and better. Job Summary We are seeking an experienced Senior Staff Engineer to lead pSemi's internal prototyping assembly laboratory. The laboratory operates in a very high‑mix low‑volume environment and supports the assembly of R&D prototypes, reliability test samples and engineering samples shipped to customers for testing. The role requires expertise in the assembly processes required for fully packaged, single die flip‑chip LGA, multi‑chip modules (MCM) and System‑in‑Package devices. Assembly processing includes paste / flux screen printing for SMT components, SMT pick‑and‑place, flip‑chip attach, mass re‑flow, underfill dispense, potting or encapsulation via dam & fill, laser marking and package singulation. The ideal candidate will have extensive hands‑on experience with automated semiconductor assembly equipment such as paste / flux printers, SMT pick‑and‑place, plasma clean, underfill / potting compound dispensers, plasma cleaner, laser markers and saw singulation equipment. The candidate should also be knowledgeable of the different semiconductor industry standards based on IPC, JEDEC, MIL spec, EIA and SMTA, as well as expertise in product qualification, process development, and team leadership. In addition, the candidate should be aware of developments in assembly and packaging technologies like WLFO, CoWos, etc. Key Responsibilities Cross‑Functional Leadership: Guide cross‑functional teams in making critical packaging mechanical decisions throughout the product development stages. Process Development & Risk Mitigation: Define and develop manufacturing processes by performing detailed design analysis (tolerance analysis, RMS, FMEA, etc.) and guiding risk assessments. Design Documentation & Oversight: Coordinate preparation of design documentation, BOM, and assembly process flows, ensuring all aspects meet technical specifications and quality standards. Team Mentorship: Mentor junior engineers and lead technical development efforts across packaging and assembly disciplines. Failure Analysis & Problem Resolution: Root cause analysis and resolution of issues during both the development and production phases. Minimum Qualifications (Experience and Skills) Education: Bachelor's degree in Engineering (Mechanical, Electrical, Packaging, Materials, or Chemical), Physics, or Chemistry. MS preferred. Experience: At least 12 years in electronics packaging, including 5 years of hands‑on experience in the assembly of LGA, MCM and SiP‑specific assembly processes and packaging‑related technologies. Document Management systems: experience working with document management systems, e.g. Agile, the ECO process and Product Life Cycle management. Process Documentation: Ability to document the assembly process flow via standard process descriptions, detailed work instructions, quality specifications based on JEDEC & MIL standards. Design & Development Tools: Proficient with design tools such as AutoCAD, Cadence Allegro, CAM350 or similar. Hands‑on experience with Solidworks for basic 3D model generation. Experience setting up and overseeing operation of a semiconductor proto‑assembly lab for quick‑turn customer sampling. Packaging Knowledge: In‑depth understanding of microelectronic packaging technologies, including flip‑chip bumping, wafer backend processing and SMT. Cross‑Functional Team Leadership: Experience leading cross‑functional teams in a fast‑paced, deadline‑driven environment. Process & Risk Management: Ability to assess design feasibility, conduct cost‑risk analysis and mitigate technical risks during NPI product development. Preferred Qualifications RF Product Design: Experience with the design and packaging of RF products. Statistical Analysis Tools: Familiarity with statistical software or tools for analysis. Automated Task Management: Experience with Excel macros or automation for process optimization, Jira for task management. LGA Package Assembly: Knowledge of the assembly process flow and quality requirements per industry standards. Ability to continuously improve the assembly process flow based on concepts of DfM, DfR and similar. PCB Fabrication: Understanding of PCB fabrication and design processes. Package Reliability & Quality Assurance: Knowledge of semiconductor quality and reliability standards and failure modes. Education Requirements Bachelor's in Engineering (Packaging, Electrical, Mechanical, Materials or Chemical), Physics or Chemistry; MS preferred. Work Environment This job operates in a professional office environment. This role routinely uses standard office equipment. Physical Demands The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk or hear. The employee frequently is required to stand, walk, use hands to finger, handle or feel and reach with hands and arms. Specific vision abilities required by this job include close vision, distance vision, color vision, peripheral vision, depth perception and ability to adjust focus. This position requires the ability to occasionally lift office products and supplies, up to 20 pounds. Compensation USD $172,201.96 - $223,874.95 per year EEO Statement pSemi Corporation supports a diverse workforce and is committed to a policy of equal employment opportunity for applicants and employees. pSemi does not discriminate on the basis of age, race, color, religion (including religious dress and grooming practices), sex/gender (including pregnancy, childbirth, or related medical conditions or breastfeeding), gender identity, gender expression, genetic information, national origin (including language use restrictions and possession of a driver's license issued under Vehicle Code section 12801.9), ancestry, physical or mental disability, legally‑protected medical condition, military or veteran status (including “protected veterans” under applicable affirmative action laws), marital status, sexual orientation, or any other basis protected by local, state or federal laws applicable to the Company. pSemi also prohibits discrimination based on the perception that an employee or applicant has any of those characteristics, or is associated with a person who has or is perceived as having any of those characteristics. Trademarks and Patents Note: The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries. All other trademarks are the property of their respective companies. pSemi products are protected under one or more of the following U.S. Patents: ************************ #J-18808-Ljbffr

A leading laboratory organization in San Diego is seeking a Machine Learning Engineer I/II to contribute to the development of foundation models for biology. This role involves training and optimizing large-scale machine learning systems in a collaborative environment with a diverse team. Ideal candidates will have relevant degrees and practical experience in large-scale ML tools, with strong communication skills. The position offers competitive compensation with a salary range from $150,450 to $203,550 for Machine Learning Engineer I. #J-18808-Ljbffr

Senior Systems Engineer Gilero is a leading medical device design, development, and manufacturing partner. We specialize in creating innovative solutions that improve patient care and enhance lives. Our growing dynamic team of professionals works across disciplines to bring ideas to life, from concept to commercialization. We are seeking a highly skilled Senior Systems Engineer to lead and contribute to the development of complex medical devices and combination products. The ideal candidate will bring a systems-level perspective, integrating mechanical, electrical, and software components while ensuring compliance with regulatory and quality standards. You will be responsible for leading systems engineering project activities for medical device and drug delivery applications. This role is pivotal in bridging engineering disciplines to deliver safe, effective, and innovative healthcare solutions. Join us in a collaborative and innovative environment where your contributions will make a real difference. You'll work with multiple clients across a variety of cutting-edge products to help shape the future of healthcare technology, ensuring products meet the highest standards and positively impact patient outcomes across the globe. Responsibilities: Acts as technical lead throughout the full product development lifecycle from initial concept to release to market of new medical devices; primarily class I and class II electro-mechanical devices. Provides expertise in various Systems Engineering principles including user and stakeholder need definition; requirements definition; risk management, product architecture, configuration management, traceability, change management, and reliability. Plans systems engineering projects by identifying appropriate system development lifecycles. Develops product development strategies for large or complex systems integrations. Generates system architecture definitions, integrations, development viewpoints, and models. Manages the system architecture and relates it to the design throughout the lifecycle. Defines requirements hierarchy and how it relates to verification and validation planning. Performs functional system decompositions to solve complex design challenges. Prepares detailed component and assembly drawings. Leads and participates in writing product and customer requirements, design and phase reviews, product and process risk assessments, root cause investigations, and corrective action planning. Plans, authors, and executes test methods and protocols for design verification and validation. Analyzes test data, interprets results, and formulates conclusions. Maintains the Design History File (DHF) and ensures documents are complete, accurate, current, and compliant with regulations. Contributes to developing systems engineering tools and processes and trains others to use those systems. Identifies technical opportunities and generates work for themselves within their assigned project teams. Defines objectives, participates in, and oversees the quality of output for large or complex projects. Contributes to solving open-ended problems and tasks with a high level of decision-making. Formulates and develops detailed project deliverables with some management oversight. Communicates technical risks and proposed solutions clearly and directly with the customer. Sources and interfaces with third-party vendors. Acts as subject matter expert (SME) lead in one or more areas and is aware of industry trends. Supports business development efforts as a SME to potential customers and providing input on engineering estimations. Establishes a proven track record of building trust and rapport with new clients. Acts as mentor demonstrating strong leadership skills. Participates in recruitment activities including interview panels. Travel will be required, as necessary (typically less than 5%). Skills/Qualifications: BS in Engineering or equivalent technical degree. Work onsite in the Carlsbad, CA office four days per week. 5+ years relevant experience. Experience developing electro-mechanical medical devices. Proven ability to lead a product development program from concept to market release. Working knowledge of system modeling tools and methodologies (e.g., UML, SysML). Working knowledge of working in both agile and waterfall methodologies. Proficiency with SolidWorks or other 3D CAD (Computer Aided Design) modeling software. Working knowledge of requirements management software (e.g., Jama, Polarion, Doors). Working knowledge of developing products for compliance with IEC 60601 for electrical safety and for software development. Working knowledge of developing products for compliance with FDA 21 CFR Part 820.30, 21. CFR Part 4, ISO14971, ISO 13485 and EU MD. Personal Attributes: Meets Gilero Core Values: Collaboration, Innovation, Excellence, Integrity. Productive in a fast-paced, entrepreneurial environment. Commits to excellence and quality service to external and internal customers. Adheres to established policies and procedures, while contributing to continuous improvements. Eligibility To Work: Applicants must be permanently authorized to work in the United States without the need for employer sponsorship now or in the future. Gilero does not offer sponsorship for employment authorizations (work visas). We are an E-Verify employer and confirm work authorization for all new hires. Why work at Gilero: Founded in 2002, Gilero, a Sanner Group company, is an international contract engineering firm that specializes in the design, development, and manufacturing of novel medical devices and drug delivery products. At Gilero we are proud of the culture we have built that directly reflects our values of excellence, integrity, innovation, and collaboration. Motivated by our purpose to benefit people and improve patient outcomes, our team continues to grow at a rapid pace. US locations include Carlsbad, CA; Chicago, IL; as well as NC locations in Raleigh, Durham, Greensboro, and Pittsboro. You will enjoy an annual bonus plan, Medical (3 BCBS plans to choose from), Guardian dental and vision, company provided life insurance, short-term and long-term disability, 401(k) with a match the first month you start with a zero-vesting period, and access to LinkedIn learning for personal and professional development.

Our Team: Semtech Corporation is a leading supplier of analog and mixed-signal semiconductors for high-end consumer, enterprise computing, communications, and industrial equipment. As our future market opportunities have increased in recent years, we have continued to invest in disruptive analog platforms and have created innovative new solutions for a wide range of leading edge products. The Sensing Product Group located in our San Diego office has unique expertise in system level platform solutions for Sensing Products including Touch & Proximity. These are leading edge low power touch-interface solutions integrated with highly accurate ADCs for enhanced sensing performance. These ultra-small, feature-rich sensing systems are optimized for a wide range of battery-powered, portable applications such as smartphones, laptops, tablets, wearables, handheld devices and other consumer or ITA control applications. Job Summary: The Sr. Integrated Circuit (IC) Verification Engineer is responsible for developing and implementing verification plans for a variety of mixed-signal integrated circuit blocks and systems. The Sr. Integrated Circuit (IC) Verification Engineer will closely collaborate with system, digital & physical design, embedded firmware, analog, and cross functional teams. The role also includes technical leadership, mentoring and supervision of junior verification engineers, pre-silicon validation, and support to silicon validation, production test and application engineers. Responsibilities: * Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%) * Design and implement complex testbenches using SystemVerilog and UVM methodology. Perform block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Debug complex simulation failures and identify root causes in design or verification environments. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Generate and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (30%) * Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%) * Supervise and mentor junior verification engineers. (15%) * Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%) * Support silicon lab evaluation, performance characterization and debug. (5%) * Technical support to test, product and application engineers. (5%) Minimum Qualifications: * 8+ years of industry experience in integrated circuit design verification (DV) * B.S. or M.S. in Electrical or Computer Engineering * Strong analytical, synthesis and problem solving skills * In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals. * Proficiency in SystemVerilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens) * Demonstration of technical leadership * Experience with standard hardware protocols (I2C, I3C, SPI, MIPI) * Independent, self-motivated, rigorous, innovating, team player and able to follow through * Excellent verbal and written communication skills Desired Qualifications * Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application * Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL * Experience with consumer and/or ITA market circuit developments The intent of this job description is to describe the major duties and responsibilities performed by incumbents of this job. Incumbents may be required to perform job-related tasks other than those specifically included in this description. All duties and responsibilities are essential job functions and requirements and are subject to possible modification to reasonably accommodate individuals with disabilities. We are proud to be an EEO employer M/F/D/V. We maintain a drug-free workplace. A reasonable estimate of the pay range for this position is $130,000 - $183,206. There are several factors taken into consideration in determining base salary, including but not limited to: job-related qualifications, skills, education and experience, as well as job location and the value of other elements of an employee's total compensation package. #li-hybrid #LI-RB1

The Senior V&V Engineer plays a critical role in ensuring Carlsmed's medical device software systems meet safety, performance, and regulatory requirements. This role is responsible for planning, executing, and documenting verification and validation activities across software systems. The engineer will collaborate closely with R&D, Software Engineering, Mechanical Engineering, Operations, and Regulatory teams to ensure products comply with FDA, ISO, and IEC design control standards. The ideal candidate has deep experience in software based medical device V&V, strong technical test skills, exceptional documentation discipline, and the ability to work across complex, multidisciplinary product architectures. Key Responsibilities Test Strategy & Planning Develop and maintain comprehensive V&V plans, including Verification Plans, Validation Plans, Test Protocols, Test Reports, and Traceability Matrices. Define system-level test strategies for software, hardware, and integrated platforms in compliance with FDA 21 CFR 820.30, ISO 13485, IEC 62304, etc. Contribute to risk management activities (hazard analysis, FMEA) and ensure test coverage aligns with risk controls. Execution & Documentation Execute verification and validation test protocols, including functional, regression, performance, and usability testing. Document objective evidence and maintain high-quality engineering records suitable for regulatory audits and submissions. Ensure full traceability between user needs, system/software requirements, risk controls, and test cases. Cross-Functional Collaboration Work closely with Mechanical Engineering and Operations to clarify requirements and ensure they are testable and unambiguous. Partner with Software, Clinical, and Quality teams to identify defects early and improve design robustness. Support Regulatory and Quality teams by contributing to 510(k) and technical documentation packages. Tools & Process Ownership Manage test environments-including configurations for hardware, imaging datasets, and software builds. Use and improve test management tools such as Jira, TestRail, Jama, etc. Drive continuous improvement in V&V processes, including automation opportunities, documentation templates, and design control workflows. System-Level Testing Conduct integrated testing across imaging, planning software, and hardware subsystems. Support image-based testing (CT, MRI, X-ray) and anatomical model validation as needed. Perform root-cause analysis in collaboration with engineering teams for system failures or anomalies. Qualifications Bachelor's or Master's degree in Biomedical Engineering, Systems Engineering, Computer Science, Mechanical Engineering, or related field. 5+ years of experience in V&V for medical devices or other regulated industries. Strong knowledge of FDA, ISO 13485, IEC 62304, etc. standards and Design Controls. Hands-on experience writing V&V documentation (test plans, protocols, reports, trace matrices). Proficiency in testing complex systems that combine software, hardware, and clinical workflows. Familiarity with defect tracking and test management tools (e.g., Jira, TestRail, Jama). Strong analytical, troubleshooting, and communication skills. Experience with imaging-based systems, surgical workflows, or cloud-connected devices is a plus. (Preferred) Background supporting regulatory submissions such as 510(k). Equal Opportunity Employer Carlsmed is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran, or disability status. Carlsmed is committed to providing reasonable accommodation for candidates with disabilities in our recruitment process. If you need assistance or accommodation due to a disability, please let us know. Compensation We are pleased to provide a competitive salary and benefits. Our benefits reflect our investment in the overall health and well-being of our employees and their families. including paying 100% of monthly healthcare, dental and vision insurance premiums, a 401(k) plan with employer matching, and unlimited PTO. The expected pay range is $145,000 to $165,000. Compensation may vary based on related skills, experience, and relevant key attributes.

Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software. Job Title : Design Verification Engineer Job Type : Full time Location : San Diego And Bay Area Job Description : Strong verification skills: test planning, problem solving, debug, adversarial testing. Multimedia Camera Image processing, Video or graphics hardware experience is preferred. Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C. Experience with methodologies like RVM/VMM/OVM/UVM. RTL design experience and/or very strong OOPs programming experience is also a plus. Good written and oral communications skills required. Experience with simulation acceleration tool like Veloce/Palladium is a plus. Skill required: CPU, (MC: middle core, ARM architecture) Decent knowledge of assertions. SV and decent UVM knowledge Code coverage. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. Additional Information All your information will be kept confidential according to EEO guidelines.

Responsibilities MaxLinear is seeking a Staff ASIC Verification Engineer to join our team. In this role, you will focus on the following: Define SoC verification strategies, test plans, and execution plan with ASIC Verification team Own IP level ASIC verification efforts toward SOC T/O Implement best industry practices for SoC verification; improve and harmonize verification methodologies across the organization to maximize efficiency and predictability of outcome Deliver test bench architecture, functional models, complete test environments, and test suites meeting coverage targets to ensure first-time silicon success Collaborate with design team and project stakeholders on testability improvements and on debug process during test bench bring up Qualifications Track record in verification strategy development and execution for large SoCs and signoff with coverage metrics Hands-on knowledge of UVM methodology, System Verilog, C/C++ Implementation of directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, PCIE and multi-CPU environments Knowledge of verification IP and functional coverage techniques Experience with gate level simulations of delay annotated netlists Exposure to FPGA emulation and lab validation Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment BS in Electrical Engineering or related + 5 years of experience, or MS + 3 years of experience, or Ph.D. Compensation and Benefits MaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation. MaxLinear expects to offer a starting base salary within the range of: $104,728 to $162,656 Annually We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off. The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience. Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status. Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world's communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world's most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world's first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn't achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we've developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we've expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel's Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers' needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore. We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.

Description About the Company Balboa Water Group is the health and wellness industry's leading provider of electronic control systems, electronic accessories, pumps, jets, and other therapy products. Our dedication to excellence and quality for five decades has made us the premier, single-source provider of innovative and reliable designs, state-of-the-art manufacturing, and outstanding customer service worldwide. Due to our rapid growth, we are looking for passionate and talented team members that want to work in an organization that values integrity, diversity, intellectual curiosity and accountability. Job Summary As a Design Validation Engineer, you will be responsible for designing, developing, and executing test plans and procedures to ensure the quality and reliability of our products. You will work closely with the engineering team to identify, analyze, and resolve issues throughout the development lifecycle. Key Job Responsibilities * Develop and execute test plans, test cases, and procedures for software and hardware products. * Perform functional, regression, integration, and system testing to verify product requirements. * Generate report from Design Validation Plan (DVP) * Identify, document, and track defects using tools like Azure DevOps or Jira, and collaborate with engineering teams to resolve them. * Collaborate with software and hardware engineers to troubleshoot and resolve issues. * Participate in design and code reviews to assess product testability and quality. * Maintain comprehensive test documentation, including test reports, specifications, and metrics. * Contribute to continuous improvement by refining testing methodologies and identifying process improvements. * Coordinate DFMEA (Design Failure Mode and Effects Analysis) and ECN (Engineering Change Notice) processes. * Engineering documentation drawing, specifications * Special characteristics: Fit, form, function, durability * Ensure compliance with industry regulations and safety standards. * Establish lines of communication with customers, suppliers and R&D Qualifications Education Requirements BSEE degree in a related science or technology field of study. Experience Requirements * 3+ years of professional experience in product design process and life of product support. * Proven experience in software and hardware verification and validation testing (V&V). * Proficiency in writing technical engineering documents, test plans, and test cases. * Experience with agencies regulation, and compliance test and certification process (UL,FCC,CE). Required Skills/Abilities * Hands-on experience with end-to-end product testing, from concept to design completion. * Working knowledge of APQP methodology * Understand NPI Gate Process * Ability to interpret product requirements, propose test strategies, and identify risks. * Expertise in developing and executing functional, regression, and performance tests. * Proficient in using issue-tracking tools such as Azure DevOps, Jira, or similar platforms. * Excellent verbal and written communication skills, with the ability to convey technical details clearly. * Strong attention to detail, problem-solving skills, and a sense of urgency. * Ability to learn new tools and testing methodologies quickly. * Comfortable working independently and collaboratively with minimal supervision. Salary Range: $85,000 - $105,000 EEO Statement Balboa Water Group is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. **Meet the Team** The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. **Your Impact** ** ** Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. **Minimum Qualifications** ** ** + Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degreeprogram.Familiaritywith hardware description languages (HDLs), such as Verilog or VHDL. + Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). + Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. + Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) + Understanding of physical design and DFT (Design for Test) principles + Familiarity with Linux-based development environments + Ability to adapt to new technologies and problem-solve sophisticated engineering challenges + Excellent organizational, teamwork, and communication skills **Why Cisco** ** ** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to work in the U.S. and/or Canada:** Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: + 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees + 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco + Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees + Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) + 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next + Additional paid time away may be requested to deal with critical or emergency issues for family members + Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: + .75% of incentive target for each 1% of revenue attainment up to 50% of quota; + 1.5% of incentive target for each 1% of attainment between 50% and 75%; + 1% of incentive target for each 1% of attainment between 75% and 100%; and + Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.

Responsibilities MaxLinear is seeking a Staff ASIC Verification Engineer to join our team. In this role, you will focus on the following: Define SoC verification strategies, test plans, and execution plan with ASIC Verification team Own IP level ASIC verification efforts toward SOC T/O Implement best industry practices for SoC verification; improve and harmonize verification methodologies across the organization to maximize efficiency and predictability of outcome Deliver test bench architecture, functional models, complete test environments, and test suites meeting coverage targets to ensure first-time silicon success Collaborate with design team and project stakeholders on testability improvements and on debug process during test bench bring up Qualifications Track record in verification strategy development and execution for large SoCs and signoff with coverage metrics Hands-on knowledge of UVM methodology, System Verilog, C/C++ Implementation of directed and constrained random test benches for communication physical layer, Ethernet networking, packet processing, PCIE and multi-CPU environments Knowledge of verification IP and functional coverage techniques Experience with gate level simulations of delay annotated netlists Exposure to FPGA emulation and lab validation Self-motivated, excellent communication skills, and ability to excel and to provide leadership in a fast-paced environment BS in Electrical Engineering or related + 5 years of experience, or MS + 3 years of experience, or Ph.D. Compensation and Benefits MaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation. MaxLinear expects to offer a starting base salary within the range of: $104,728 to $162,656 Annually We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off. The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience. Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status. Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world's communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world's most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world's first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn't achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we've developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we've expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel's Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers' needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore. We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market. We can recommend jobs specifically for you! Click here to get started.

Mindlance is a national recruiting company which partners with many of the leading employers across the country. Feel free to check us out at ************************* Job Description · 3years minimum experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies. · Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using reg Model (UVM_REG) API, drivers, monitors, scoreboard, functional coverage, assertions (SVA), simulations, regression, debug, bug reporting/tracking. · Experience in debugging RTL & Gate level simulations · Part of multiple tapeouts with high quality verification. Qualifications · Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering or equivalent experience Additional Information To discuss on this opportunity feel free to reach Praveen and My Number is ************. Thanks

We are the makers of possible BD is one of the largest global medical technology companies in the world. Advancing the world of health is our Purpose, and it's no small feat. It takes the imagination and passion of all of us-from design and engineering to the manufacturing and marketing of our billions of MedTech products per year-to look at the impossible and find transformative solutions that turn dreams into possibilities. We believe that the human element, across our global teams, is what allows us to continually evolve. Join us and discover an environment in which you'll be supported to learn, grow and become your best self. Become a maker of possible with us. Job Summary: The Staff Design Quality Engineer will play a crucial role in ensuring the quality and regulatory compliance of CareFusion 303, Inc.'s medical devices throughout their entire product lifecycle, from design and development through to market release. This position will involve active participation in design control activities, risk management, and fostering a culture of quality within the engineering teams. Job Responsibilities Design Control & Development: * Actively participate in product design and development activities, providing quality engineering support and guidance. * Review and approve design inputs, design outputs, design verification, and design validation plans and reports. * Ensure compliance with design control procedures, medical device regulations (e.g., FDA 21 CFR Part 820, ISO 13485), and company policies. * Contribute to the development and maintenance of Design History Files (DHFs). Risk Management: * Lead and facilitate risk management activities, including the development and maintenance of risk management plans, hazard analyses, and FMEAs (Failure Mode and Effects Analyses). * Ensure appropriate risk mitigation strategies are implemented and verified. Post-Market Surveillance & CAPA: * Support post-market surveillance activities by analyzing complaint data and identifying potential quality issues. * Participate in root cause analysis and corrective and preventive action (CAPA) investigations related to design quality. * Contribute to the effectiveness verification of CAPA actions. Compliance & Audits: * Support internal and external audits (e.g., FDA, ISO) by providing documentation and technical expertise related to design quality. * Ensure ongoing compliance with all applicable quality system regulations and standards. Training & Mentorship: * Provide guidance and training to engineering teams on design control, risk management, and quality system requirements. * Act as a mentor to junior quality engineers. Job Qualifications Education: * Bachelor's degree in Engineering (Biomedical, Mechanical, Electrical, or related field) required. Master's degree preferred. Experience: * 5+ years of experience in Design Quality Engineering within the medical device industry. * Demonstrated experience with medical device design controls (21 CFR Part 820.30) and risk management (ISO 14971). * Strong understanding of ISO 13485 quality management system requirements. * Experience with Design Verification and Validation activities including software, system, and human factors testing. * Experience in requirements decomposition, traceability, and test strategy development. * Understanding of change impact analysis and regression test scoping methods. Skills: * Excellent analytical and problem-solving skills. * Strong communication (written and verbal) and interpersonal skills, with the ability to effectively collaborate with cross-functional teams. * Proficiency in statistical analysis and quality tools. * Ability to interpret and apply complex regulatory requirements. * ASQ certifications (e.g., CQE, CRE) preferred. * Proficiency in relevant software tools (e.g., TeamCenter, Polarion, AzureDevOps, PLM systems). At BD, we prioritize on-site collaboration because we believe it fosters creativity, innovation, and effective problem-solving, which are essential in the fast-paced healthcare industry. For most roles, we require a minimum of 4 days of in-office presence per week to maintain our culture of excellence and ensure smooth operations, while also recognizing the importance of flexibility and work-life balance. Remote or field-based positions will have different workplace arrangements which will be indicated in the job posting. For certain roles at BD, employment is contingent upon the Company's receipt of sufficient proof that you are fully vaccinated against COVID-19. In some locations, testing for COVID-19 may be available and/or required. Consistent with BD's Workplace Accommodations Policy, requests for accommodation will be considered pursuant to applicable law. Why Join Us? A career at BD means being part of a team that values your opinions and contributions and that encourages you to bring your authentic self to work. It's also a place where we help each other be great, we do what's right, we hold each other accountable, and learn and improve every day. To find purpose in the possibilities, we need people who can see the bigger picture, who understand the human story that underpins everything we do. We welcome people with the imagination and drive to help us reinvent the future of health. At BD, you'll discover a culture in which you can learn, grow, and thrive. And find satisfaction in doing your part to make the world a better place. To learn more about BD visit ********************** Becton, Dickinson, and Company is an Equal Opportunity Employer. We evaluate applicants without regard to race, color, religion, age, sex, creed, national origin, ancestry, citizenship status, marital or domestic or civil union status, familial status, affectional or sexual orientation, gender identity or expression, genetics, disability, military eligibility or veteran status, and other legally-protected characteristics. Required Skills Optional Skills . Primary Work Location USA CA - San Diego TC Bldg C&D Additional Locations Work Shift At BD, we are strongly committed to investing in our associates-their well-being and development, and in providing rewards and recognition opportunities that promote a performance-based culture. We demonstrate this commitment by offering a valuable, competitive package of compensation and benefits programs which you can learn more about on our Careers Site under Our Commitment to You. Salary or hourly rate ranges have been implemented to reward associates fairly and competitively, as well as to support recognition of associates' progress, ranging from entry level to experts in their field, and talent mobility. There are many factors, such as location, that contribute to the range displayed. The salary or hourly rate offered to a successful candidate is based on experience, education, skills, and any step rate pay system of the actual work location, as applicable to the role or position. Salary or hourly pay ranges may vary for Field-based and Remote roles. Salary Range Information $124,700.00 - $205,800.00 USD Annual

Turning Space into a Transportation Layer for Earth Who We Are: Eras of humanity can often be defined by a dominant transportation mode - horse-drawn chariots, ocean-going boats, or aircraft. These were spurred by a small group of people rigorously focused on building technology to achieve faster access to more of the world. We seek to usher in a new era of humanity defined by universal access to the whole globe, free of borders and the presence of a routine way from space to Earth. To do this, we are building highly maneuverable re-entry vehicles that can loiter in orbit before precision landing back on Earth. What you'll do: Inversion's lifting-body reentry platform will create a highly maneuverable, highly accurate, and low-cost vehicle that will be industry-first. The Staff Mission Design Engineer will be responsible for developing a workflow to support the flight simulation data products required for flight safety analysis. This role will also aid in designing and executing system-level performance trade studies to drive key architecture decisions for current and conceptual reentry vehicles. You will own customer-facing performance predictions and safety analysis and be a key contributor to Inversion's advanced development efforts. Required Qualifications: Bachelor's degree in Aerospace or Mechanical Engineering or equivalent experience Typically 12+ years of aerospace system performance analysis Strong knowledge of 3-DOF and 6-DOF flight simulation Experience using flight simulation environments to determine impact dispersions and estimated casualty values in support of flight safety analysis. Familiarity with debris catalog generation Familiarity with trajectory design for space launch, reentry, or hypersonic systems Familiarity with handbook and medium fidelity aerodynamic prediction tools (e.g,. DATCOM, CBAERO, Cart3D, etc.) Familiarity with trajectory optimization tools (POST, OTIS, QuickShot, etc.) Experience using programming languages like Python, MATLAB, etc. to automate workflows and accelerate data analysis. Proven ability to work in a fast-paced environment, including prototyping and rapid iteration of new products. Desired Qualifications: Master's degree in Aerospace or Mechanical Engineering, or equivalent experience End-to-end space mission analysis includes launch, orbital operation, and reentry Strong knowledge of low / mid / high fidelity estimation of aerodynamics of hypersonic vehicles. Significant experience with trajectory optimization tools, including their modification and the creation of custom toolchains around them to accelerate workflows. Experience driving space system architectures using trajectory optimization software tools Space constellation design experience, including familiarity with STK (Systems Tool Kit) for space mission design and ground coverage assessments Our office headquarters is located in Playa Vista, CA. This position requires in-office presence. The California annual base salary for this role is currently $169,000-$199,000. Pay Grades are determined by role, level, location, and alignment with market data. Individual pay will be determined on a case-by-case basis and may vary based on the following considerations: interviews and an assessment of several factors that are unique to each candidate, job-related skills, relevant education and experience, certifications, abilities of the candidate and internal equity. ITAR Compliance: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here. Equal Employment Opportunity: Inversion provides equal employment opportunities to all employees and applicants without regard to race, color, religion, age, sex, gender identity, sexual orientation, national origin, veteran status, or disability. Inversion collects and processes personal data in accordance with applicable data protection laws. If you are a US Job Applicant see the CCPA Privacy Policy Notice for further details.

Job Description: Top 5 Required Skills 1. 12+ years actively involved in PWB design for high-density electronics packaging. 2. 10+ years' experience in a PWB design role designing consumer-grade mobile products or low volume test products utilizing latest generation processor chips & ICs. 3. Design for Manufacture (DFM) analysis experience utilizing Valor and/or CAM350 tools. 4. Experience with micro-vias (stacked), sequential lamination stack-ups and design rules using .5mm pitch and smaller packages 5. Experience working include working with US and India teams to provide PWB design solutions for high performance electronic assemblies for Mobile, Modem, Auto, Compute, Infrastructure and IOT Education Requirement * Associate's degree in a Technical Field, Electronics preferred Keywords * PWB, RF, radio circuits as well as power control devices. * Preferred design experience: RF, Analog, High-speed digital circuits - DDR2, 3 & 4, LPDDR5, HDMI, PCIe, SATA, MIPI, USB 2,3.x, GigE Technologies * Siemens/Mentor Xpedition, * PADS and / or Cadence Allegro PWB design software Years of Experience Requirement * 10 Physical Requirements * Push Max Weight Limit - n/a * Pull Max Weight Limit - n/a * Lift Max Weight Limit - n/a * Forklift Required (Y/N) - n/a Driving Requirements * Are there driving responsibilities no matter how minimal with this role? No * If yes, how many hours per week? n/a * How many rounds of interviews should be expected? 1-2 * Interview Method? Video conference * Work Location: Home Building: AY - 10001 Pacific Heights Blvd - San Diego, CA 92121 (USA) * Work Requirement: 80% Onsite, 20% WFH (must be local in San Diego) * Shift: 1 * Work Days: Mon-Fri * Shift Time: 7:30am - 4:00pm PST * Hours: 40 weekly / 8 hourl Comments for Suppliers: 11/4: Supplier link should be scheduled by 2:00pm PST, no link sent yet. Hoping to conduct by 11/5

This position requires office presence of a minimum of 5 days per week and is only located at customer's site. No relocation is offered. AT&T Global Public Sector is a trusted provider of secure, IP enabled, cloud-based, network solutions and professional services to the Federal Government. We are dedicated to recruiting, developing and empowering a diverse, high-performing workforce that is passionate about what they do, committed to our shared values and dedicated to our customers' mission. AT&T will deliver systems engineering and technical support to the US Navy providing software, hardware, cybersecurity, installation, and logistical services in support of current and future programs. AT&T has an opening for a Senior System Engineer supporting the development, integration, and testing of software systems for a government customer. This role focuses on designing software tools and subsystems that enable software reuse and domain analysis while interpreting requirements and design specifications into functional, tested software components. Job Duties/Responsibilities: Designs software tools and subsystems to support software reuse and domain analysis. Interprets software requirements and design specifications to code and integrates and tests software components. Required Clearance: TS/SCI or Secret clearance (#tssci) (#secret) Required Qualifications: Bachelor's degree and 3 years of professional experience in systems engineering Must have three years' experience of which at least one year must be specialized. Specialized experience includes: analytically solving workflows, organization, and/or planning problems. General experience includes increasing responsibilities in systems engineering Our Senior System Engineer's earn between $98,100 - $228,600. Not to mention all the other amazing rewards that working at AT&T offers. Individual starting salary within this range may depend on geography, experience, expertise, and education/training. Joining our team comes with amazing perks and benefits: Medical/Dental/Vision coverage 401(k) plan Tuition reimbursement program Paid Time Off and Holidays (based on date of hire, at least 23 days of vacation each year and 9 company-designated holidays) Paid Parental Leave Paid Caregiver Leave Additional sick leave beyond what state and local law require may be available but is unprotected Adoption Reimbursement Disability Benefits (short term and long term) Life and Accidental Death Insurance Supplemental benefit programs: critical illness/accident hospital indemnity/group legal Employee Assistance Programs (EAP) Extensive employee wellness programs Employee discounts up to 50% off on eligible AT&T mobility plans and accessories, AT&T internet (and fiber where available) and AT&T phone Candidates with arrest or convictions records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers, , the Los Angeles Fair Chance Initiative for Hiring Ordinance, and the California Fair Chance Act. Relevant Material Job Duties for which Criminal History may have a direct adverse, and negative relationship potentially resulting in the withdrawal of the Conditional Offer of Employment Contact with Customers/Candidates/Clients Safety Sensitivity (Vehicle/Tool/Machine Operation - if applicable) Handling/Proximity to Sensitive Information Weekly Hours: 40 Time Type: Regular Location: San Diego, California It is the policy of AT&T to provide equal employment opportunity (EEO) to all persons regardless of age, color, national origin, citizenship status, physical or mental disability, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, genetic information, marital status, status with regard to public assistance, veteran status, or any other characteristic protected by federal, state or local law. In addition, AT&T will provide reasonable accommodations for qualified individuals with disabilities. AT&T is a fair chance employer and does not initiate a background check until an offer is made.

Senior System Engineer Why Bird Rock Systems At Bird Rock Systems, we take pride in being named one of the Inc. 5000 Fastest Growing Private Companies. Our dynamic journey to success is fueled by a team of passionate individuals who thrive in a fast-paced environment. We're more than a workplace; we're a community of fun-loving people dedicated to excellence. What Sets Us Apart: Best Workplace Awards: Bird Rock Systems is proud to be recognized for our commitment to fostering a positive, collaborative, and innovative culture. Our honors include: Inc.s Best Workplaces San Diego Business Journals Best Places to Work San Diego SHRM Workplace Excellence Award Fast-Paced Growth:As an Inc. 5000 honoree, we're committed to driving innovation and pushing boundaries. Join us to be part of a dynamic and ever-evolving company. Vibrant Company Culture:We believe in creating an environment where work feels like fun. Our team is more than colleagues we're friends who collaborate, support, and celebrate together. Core Values:Our values define us. Loyalty, work/life balance, kaizen (continuous improvement), unwavering integrity, exceptional customer service, and giving back to our community are the cornerstones of Bird Rock Systems. Your Opportunity: At Bird Rock Systems, you're not just an employee you're an essential part of our growth story. Join our team of driven professionals who embrace challenges, value camaraderie, and thrive on making a difference. If you're ready to work in an exciting atmosphere that blends passion, innovation, and purpose, we invite you to apply and embark on a rewarding journey with us. Take the next step towards an inspiring career. Apply now and become a proud contributor to Bird Rock Systems' exceptional trajectory! Join us on our journey. Apply today. Position Summary We are seeking a skilled and motivated Senior System Engineer to join our dynamic team. This hands-on role involves designing, implementing, and maintaining systems infrastructure for our clients, while also supporting sales efforts through technical consultation. This is a hybrid position, requiring onsite work at customer locations in Southern California 12 days per week. Location Must be based in San Diego or Orange County, CA. Visits to our San Diego office may be required at the managers discretion. Main Duties Design, deploy, and maintain enterprise systems infrastructure (servers, storage, virtualization, cloud platforms). Monitor system performance and troubleshoot issues to ensure optimal operation. Implement security measures and compliance controls across systems. Collaborate with clients to assess needs and deliver tailored solutions. Support sales team with technical expertise during client engagements. Develop and maintain system documentation and architecture diagrams. Automate system tasks using scripting languages (e.g., PowerShell, Python). Provide training and documentation for newly implemented solutions. Stay current with emerging technologies and industry trends. Deliver exceptional service to customers, coworkers, and partners. What You Bring Education & Experience Bachelors degree in computer science, Information Technology, or related field- or equivalent experience. Qualifications & Key Skills 5+ years of experience in systems engineering or related role. Proficiency in scripting (PowerShell, Python) for automation. Strong understanding of Windows server environments. Experience with virtualization platforms (VMware, Hyper-V). Familiarity with cloud platforms (Azure, AWS, GCP). Hands-on experience with system security tools and practices. Solid understanding of network troubleshooting concepts, including switching, routing, firewalls, and wireless technologies. To show us youve read this posting carefully, please answer the following question in your application: Youre in a race and you pass the person in second place. What place are you in now? Effective troubleshooting using logs and diagnostic tools. Certifications such as MCSA, MCSE, Azure Administrator or equivalent. Excellent problem-solving and communication skills. Ability to work independently and collaboratively. Preferred Skills Experience with backup and disaster recovery solutions. Knowledge of identity and access management (IAM). Familiarity with containerization (Docker, Kubernetes). Experience with monitoring tools (e.g., SolarWinds, Nagios). Understanding of compliance frameworks (e.g., HIPAA, SOC 2). Compensation Compensation Range: $115,000 - $175,000 The above represents the expected compensation range for this job requisition. Ultimately, in determining pay, well consider location, experience, and other job-related factors. Our compensation structure is designed to recognize performance, drive growth, and align personal success with company success. When you contribute to the companys success, you share in that success - creating a culture that rewards innovation, accountability, and excellence through performance-based compensation. Benefits At Bird Rock Systems, we make sure you have the support and resources to leverage and develop your skills, secure your financial future, and take care of your health and well-being. Bird Rock Systems continually seeks to provide a workplace where everyone can be their authentic self. Through Bird Rock Systems competitive benefits offerings and various training and development opportunities, we have you covered with our Benefits Program which includes: Medical, Dental, and Vision Insurance Unlimited Paid Time Off Paid Family Leave Benefits Flexible Spending Accounts Pet Insurance Employee Assistance Program 100% Employer-Paid Life & AD&D Insurance, Short- and Long-Term Disability Insurance Monthly Wellness Reimbursement Cell Phone Reimbursement