Astera Labs jobs in Santa Clara, CA

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* About Astera Labs Global leader in purpose-built connectivity solutions for AI and cloud infrastructure Pioneering software-defined architecture that is scalable and customizable PCIe , CXL , and Ethernet semiconductor-based solutions to solve data, memory, and networking bottlenecks Trusted relationships with hyperscalers and the data center ecosystem Are you passionate about driving new architectures with the world's leading AI platform providers and hyperscalers in order to drive the successful adoption of semiconductor-based solutions for AI and cloud infrastructure? Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? We are seeking a Director of Corporate Development to lead and support strategic transactions including acquisitions and strategic partnerships. This role will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and business and executive leadership to identify and evaluate opportunities that align with Astera Labs' long-term growth strategy. You will be responsible for conducting market research, opportunity sizing, competitive analysis, and build/buy/partner evaluations. You will also lead financial modeling, valuation analysis, and develop executive presentations to support strategic decision-making. Key Responsibilities Define and continually enhance the company's strategy to acquire new business opportunities at both a high level and in-depth with a specific focus on our leading hyperscaler customers and AI platform partners Lead and support corporate development transactions through all phases of the transaction lifecycle. Research adjacent and new market opportunities, including opportunity and market sizing, target landscaping, and competitive analysis. Partner with business and engineering teams to evaluate opportunities to address strategic gaps and conduct build/buy/partner analysis. Conduct detailed financial analyses including valuation and pro forma modeling to assess deal alignment and investment needs. Develop presentation materials to provide recommendations to the executive team and board. Collaborate with PMO and broader cross-functional teams to drive diligence and validate key assumptions and value drivers. Support post-merger integration to help ensure long term value capture. Qualifications Bachelor's degree in Electrical Engineering, Computer Science, Business Administration, Economics, or related field; MBA preferred 10+ years of experience in strategy, corporate development, investment banking, private equity, venture capital, or related roles within the semiconductor or high-tech industry or financial services. Experience leading strategic transactions and working with executive leadership. Strong analytical skills with experience in valuation, financial modeling, and strategic analysis. Excellent communication and presentation skills with the ability to convey complex concepts clearly. Proven ability to collaborate effectively within an organization and drive cross-functional initiatives. Results-oriented mindset with a focus on achieving business objectives. Willingness to travel as needed for customer meetings, company training, industry events, and conferences. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in 2.5D/3D integration, chiplet technology, fan-out wafer-level-packaging (e.g., FOWLP/FoCoS/Info), and heterogeneous integration. The successful candidate will lead strategic roadmap execution and scale innovative package solutions into production through close collaboration with OSATs, foundries and key suppliers Basic Qualifications: M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline. 10+ years of experience in IC packaging development and NPI for high-speed SerDes and high-performance SoCs, ASICs, or memory products Deep hands-on expertise with FCBGA, fc CSP, co-packaged optics (CPO), and 2.5D/3D integration technologies such as CoWoS, RDL and silicon interposers, and chiplet-based architectures (e.g., BoW, UCIe); along with experience in fan-out wafer-level packaging (FOWLP/WLFO). Strong understanding of packaging material selection, substrate stack-up, bump/RDL design, and DFM for advanced nodes Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of tasks. Required Experience: Led multiple end-to-end advanced packaging NPI programs, from concept definition, pathfinding, design, supplier engagement, process development, and successful transition to HVM. Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G/448G PAM4. Experience defining RDL and bump architectures to enable die-to-die chiplet integration using interconnect standards such as BoW (Bunch of Wires) and UCIe (Universal Chiplet Interconnect Express). Demonstrated ability to lead collaboration with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development. Deep understanding of mechanical (e.g., warpage, CTE mismatch), thermal (e.g., heat dissipation, TIM), and electrical (e.g., parasitics, signal integrity) design trade-offs in advanced package development, with a proven ability to deliver robust and manufacturable packaging solutions. Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation. Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing teams. Preferred Experience: SI/PI knowledge is a plus: SI/PI concepts, S-parameter extraction, and PDN optimization using HFSS, SIwave, or Ansys Designer Knowledge of EDA design tools is a plus: Cadence Allegro/APD, Altium, etc. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Job Description We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. Basic Qualifications * Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred. * ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing. * Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc. * Professional attitude with ability to execute on multiple tasks with minimal supervision. * Strong team player with good communication skills to work alongside a team of high caliber engineers. * Entrepreneurial, open-mind behavior and can-do attitude. Required Experience * Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms. * Collaboration with design team to define test strategy, create and own test plan. * Tester platform selection, design, and development of ATE hardware for wafer sort and final test. * Familiar with high-speed load board design techniques. * Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality. * Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage - SCAN, MEMBIST, SerDes and other functional tests. * Skilled in control interfaces - I2C, I3C, SPI, MDIO, JTAG etc. * Expertise in production test of high speed SerDes operating at 16Gbps and higher. * Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug. * Experience with lab equipment including protocol analyzers and oscilloscopes. * Experience with using Advantest 93k ATE platform. * Proficiency in, at least, one modern programming language such as C/C++, Python. Preferred Experience * Fluent in data processing using high level programming languages. * Experience in running External loopback at wafer sort. * Familiarity with modern databases The base salary range is $209,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: As a Sr. Principal DSP Architect, you will join a team of DSP/Systems experts, digital designers, and mixed-signal design engineers developing advanced DSP SerDes for next generation 400G per lane wireline and optical interconnect for AI systems. The DSP architecture team is responsible for the following job functions. Research novel modulation, equalization, and FEC techniques for 400G per lane wireline and optical systems. Create DSP and FEC algorithms, bit/cycle accurate C/C++ models, and hardware block specifications appropriate for RTL implementation. Work with digital team/firmware team to optimize and implement DSP algorithms in hardware/firmware. Hands-on involvement in post-silicon performance tuning and optimization. Provide guidance on test plans for lab characterization. Provide support for internal customers deploying SerDes IP. Basic Qualifications: Master's degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5-10 years of experience with DSP architectures and algorithm development. Required Skills: Solid understanding of and experience with designing adaptive DSP algorithms. Solid understanding of and experience with the practical aspects of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation. Good programming skills in C/C++, Matlab or Python. Experience in guiding and testing the transfer of high-speed numerical algorithms from C/C++ to Verilog. Additional Useful Skills: Familiarity with high-speed optical and electrical channels and the DSP algorithms for compensating their impairments. Reading knowledge of Verilog RTL and the ability to assist with the assessment of Verilog implementations of DSP algorithms. Experienced with modern version control and software management systems. Experience with error correction (Reed-Solomon, BCH, soft decoding) in high-throughput, low-latency systems. The base salary range is $160,000.00 USD - $260,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* As an Astera Labs Field Applications Engineer, you will be a trusted technical advisor to the world's leading cloud service providers, server hardware designers, and networking OEMs, as you work closely with them to design solutions that use Astera Labs' portfolio of connectivity products. In this role, you will identify and understand customer requirements, propose Astera Labs solutions, and provide hands-on design-in support. You will have an important role in driving innovation, partnering with customers as well as with our world-class engineering teams. Your feedback will help drive the product roadmap to deliver results and value to the customer. Basic Qualifications BS in electrical engineering. Master's degree in engineering is preferred. Minimum of 5 years' experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server & Storage. Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites. Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind! Required Experience Hands-on, thorough knowledge of high-speed protocols like 25G, 50G, 100G Ethernet etc. Experience with QSFP, QSFP-DD, and OSFP pluggable modules development/support. Silicon/System bring-up and debug experience in customer systems. Experience working with Contract Manufactures to support NPI and Volume Production. Experience with high-speed Signal Integrity issues. Experience with lab equipment including protocol analyzers and oscilloscopes. Experience with Python scripting or other equivalent programming languages. Preferred Experience Development/support for Ethernet Switch products. Understanding and Capturing performance metrics like Latency, Bandwidth, Power for CPU, Memory, PCIe, DDR. Knowledge of simulation, schematic capture, and PCB layout tools from Cadence, Altium and others etc. Development/support for Ethernet, PCIe, CXL, DDR4/ DDR5 in Data Center Systems. Strong working knowledge of PCIe LTSSM at a physical layer level, associated standards, and debug We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Basic qualifications Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred. ≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications. Knowledge of industry-standard simulators, revision control systems, and regression systems. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required Experience Experience with full verification lifecycle based on System Verilog/UVM/C/C++. Proven ability to mix and deploy hybrid techniques as in both directed and constrained random. Experience with different ways to bug and coverage hunting. Experience in formal methods is a plus. Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures. Identify and write all types of coverage measures for stimulus and corner-cases. Close coverage to identify verification holes for high quality tape-out. Preferred Experience Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc. Working experience with scripting tools (Perl/Python) to automate verification infrastructure. Experience with directed test based methodologies, cache verification and formal methods. The base salary range is USD 147,000.00 - USD 195,000.00. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Overview Astera Labs Inc. is seeking a skilled and proactive Hardware Lab Technician to join our dynamic team in developing world class connectivity products. Job Description This role works closely with and supports various teams within our lab, including hardware engineering, validation, product apps, quality assurance, and more. The ideal candidate will have hands-on technical skills, a strong work ethic, and the ability to manage various responsibilities in a fast-paced, collaborative environment. Key Responsibilities Manage critical inventories of Astera products, tools, consumables, and peripherals, including purchasing, organizing, monitoring, and forecasting Assemble, inspect, and test modules/subassemblies while upholding a high standard of quality Assemble and disassemble server racks, wire shelves, and tradeshow materials Optimize and maintain lab organization Monitor compliance with lab policies, including ESD, cleanliness, food/drink, etc. Assist engineers with various other hands-on tasks, including soldering and rework of high-density PCBAs Required Qualifications 2 or more years of experience in a hardware lab Associate's degree or equivalent technical certification in electronics engineering, electrical engineering, computer engineering, or similar field OR an additional 2+ years of experience 2+ years of inventory management experience Self-starter with a bias towards action Proficiency in Microsoft Excel and Word Strong organizational skills and attention to detail Keen analytical problem-solving skills Effective and clear communication, both written and verbal Ability to lift and move up to 40lbs safely Preferred Qualifications 4 years of experience in a hardware lab Comfortable performing solder rework on 0201 components, micro-coax cables, and fly line/magnet wire Fluent in interpreting circuit schematics and board layouts Ability to troubleshoot and debug PCBAs using oscilloscopes, multimeters, power supplies, etc. Ability to clearly document and communicate findings and measurement results Experience setting up and troubleshooting rack-mounted servers Familiarity with Python, Bash, Linux, and Raspberry Pi The base salary range is $46-$67 Per Hour. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Role Overview We are seeking a highly motivated and experienced Internal Controls Manager to join our dynamic SOX Compliance function. This role will be responsible for the design, implementation and monitoring of the Company's internal controls over financial reporting. This position is in our San Jose, California office. As SOX Manager, you'll be the second hire into our SOX team - a foundational leader helping us build and mature our compliance program. This role reports to Dir. SOX Compliance. As the function grows, this role will provide an opportunity to shape the SOX program and expand the scope to include broader responsibilities. Key Responsibilities Manage the Company's internal controls compliance and risk assessment efforts across key financial and operational processes Update internal controls documentation, risk control matrix, and flowcharts, and evaluate controls on new systems or process changes Continuously rationalize and refine the SOX program relative to company changes and emerging risks Partner with the external co-sourced team across all aspects of the SOX program, including walkthroughs, testing and reviewing controls, and remediation guidance Collaborate with control owners, operational groups on process enhancements and partner with IT to evaluate IT general controls (ITGCs) and automate business process controls (ITACs) Work with the stakeholders by providing guidance on best practices, risk and awareness on SOX compliance requirements Serve as a point of contact on internal controls with external auditors and build strong working relationships with stakeholders to facilitate the audit process Assist with the review of third-party SOC 1 reports Design test plans, perform testing of controls, document results and identify opportunities for improvements Perform assigned projects or ad hoc duties as required Qualifications 5+ years of SOX or internal audit experience, ideally with both public company environment and a Big 4 or large regional public accounting firm Strong understanding of governance and internal control regulations including COSO Proven track record of designing, implementing and monitoring internal controls Strong project management skills and the ability to drive accountability in a cross-functional environment Leadership mindset, hands on approach; you're able to step up, build trust, and mentor others Ability to manage and execute multiple projects Excellent interpersonal and communication skills, with the ability to build relationships with internal and external stakeholders Bachelor's degree in accounting, finance or related field (Master's degree or CPA preferred) We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs' SoC and systems products. As a Principal Firmware Engineer you are responsible for implementing the major differentiating features of Astera Labs' products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended. Basic Qualifications Strong academic and technical background in electrical engineering. At a minimum, a Bachelor's in EE or Computer Science is required, and a Master's is preferred. Minimum 8 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC). Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act fast with the customer in mind! Authorized to work in the US and start immediately. Required Experience Experience working on PCIe-Express (Gen-3 and above) protocol, including working with analyzers and exercisers to debug protocol issues. High level of proficiency in C (preferred) or C++, including development of C-based SDKs. High level of proficiency in Python for automating pre-processors/post-processors and FW QC. Working knowledge of software/firmware build environments, gcc/Make, Doxygen, and GitHub. Familiarity with SoC interfaces to common IP blocks such as PCIe Controllers, DDR Controllers, NVME Controllers, AMBA/AHB interfaces, on-chip memory interfaces, and other similar interfaces. Preferred Experience Experience with PAM4 SerDes with working knowledge of Tx/Rx equalization, adaptation, CDR and SerDes link budgets. Hands-on experience with PCIe devices in Server, Storage, and/or Networking equipment. Experience developing embedded firmware for PCIe or Ethernet Switch products. The base salary range is $203,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* As an Astera Labs Principal Lab Validation Engineer, you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions. You will: Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions. Collaborate with design, validation, and system engineering teams as needed. Modify device firmware to test out engineering theories leading to potential fixes or production screens. Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems. Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability. Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports. Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures. Develop and run stress tests and margining experiments to identify weak design or process corners. Provide feedback on system-level integration challenges for retimers and PCIe switches (e.g., board layout, equalization tuning, firmware interactions). Drive physical failure analysis to isolate and image defects using methods such as fault isolation, probing, de-processing, FIB, thermal/voltage stress testing. Document debug findings, propose design/process/test improvements, and contribute to FA methodologies. Participate in new product development process to ensure readiness for customer returns before products are launched. Collaborating in the development of evaluation hardware (boards and sockets, including FA friendly sockets) and scripts. Basic qualifications: Minimum of a Bachelor's in Electrical Engineering while a Master's degree is preferred. Minimum of 10 years relevant experience of which 5 years' is hands-on mixed high-speed lab experience working with equipment such as protocol analyzers, BERT, real-time scopes, sampling scopes, TDR, and VNA. Python programming. Deep understanding of PCIe protocol (up through Gen6), retimer architecture, and SerDes signal integrity. Hands-on experience debugging retimers (equalization tuning, pass-through mode, clocking, reset/link sequencing). Hands-on experience debugging PCIe switches (lane bifurcation, hot-plug, multi-port link stability, compliance failures). Strong background in NRZ/PAM4 architectures, investigating issues with jitter, CDR/PLL behavior, equalization (DFE, CTLE, FFE), crosstalk, and power integrity. Experience in post-silicon validation and bring-up of high-speed PHYs or retimers. Solid problem-solving and analytical skills with ability to narrow down complex multi-layer failures. Strong written and verbal communication skills. Preferred experience (ideal candidate has some of this, but OJT is also possible): C (not C++). Experience with optics. Experience with chip-level security and RAS features. ATE (Automated Test Equipment) Advantest V93K. Understanding of system-level architecture for servers, storage, and AI/ML platforms where PCIe retimers/switches are deployed. Based in San Jose, this position requires an in-person presence, offering a unique opportunity to impact our global operations directly. The base salary range is $203,000 USD - $230,000 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Are you passionate about driving business growth for the next generation of data infrastructure with hyperscale and AI platform providers - through customer intimacy, deal negotiation and commercial strategies? We are seeking a highly proficient and experienced business manager to join our team at Astera Labs. As a key member of our business management team, you will work closely with customers, sales, product marketing, operations and other internal cross-functional teams to accelerate revenue and execute on our deal pipeline for critical opportunities. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of commercial expertise and customer insight across our product portfolio. Based in San Jose, CA, this position requires an in-person presence with travel to customers. Key Responsibilities Lead customer deal pipeline: Work closely with sales and lighthouse customers secure strategic design-wins and progress pipeline towards design-in and conversion to contracts and purchase orders. Own commercial frameworks: Set, align and approve pricing and commercial terms for key deals and establish consistent pricing strategies and methodologies across products in partnership with product marketing teams. Facilitate customer and segment playbooks: Leverage commercial, market and product expertise to support strategy definition and partner with sales to develop playbooks for key customers, segments and regions - covering key elements such as customer insights, relationship mapping, competitive analysis, win/loss analysis solution positioning and negotiation plans. Support business process innovation: Work closely with business functions to enable the next phase of scale through identifying, prioritizing and executing key operational improvements such as new operating procedures, tools or organizational clarity. Qualifications Bachelor's degree in engineering, computer science or business/marketing 10+ years of experience in, product marketing, sourcing, supply chain, operations, sales or other customer-facing product roles within the semiconductor industry Strong strategic thinking and analytical skills, with the ability to translate customer pain points into innovative solutions (deals, partnerships, or product adoption) Proven track record of negotiating and influencing customers, leading to key agreements, contracts or purchase orders Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner Broad understanding of high-speed protocols (PCIe is required; Ethernet, CXL, and other protocols are a plus) and system architectures used in cloud and AI infrastructure Results-oriented mindset with a focus on driving measurable impact and achieving business objectives Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment Willingness to travel as needed for customer meetings, industry events, and trade shows We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: As an Astera Labs New Product Introduction (NPI) / Electrical Product (EPE) Engineer, you will be part of a Hardware Engineering team that designs and manufactures products featuring Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server, and network OEMs. In this role, you will be responsible for NPI-taking products from the design stage to volume manufacturing. You will work closely with designers, manufacturing teams, suppliers, and contract manufacturers to ensure that hardware product test flows are properly introduced, released to manufacturing, and supported past production. This role will also require engagement in activities such as Bill of Materials (BOM) management, Design for Manufacturability (DFM), validation, and process documentation. Additionally, the EPE is expected to drive continuous improvements in manufacturing test flow, product yield, and cost efficiency. While your focus will be on NPI/EPE, you will have the opportunity (and be expected-depending on your experience) to contribute to adjacent areas such as test engineering, validation, and quality. Being part of a growing manufacturing team, we welcome the diverse experience you bring. Key Responsibilities Own manufacturing NPI/EPE activities, ensuring successful product transition from design to volume manufacturing. Manage PCBA BOM structuring and risk assessment to improve manufacturability and minimize changes late in the cycle. Lead BOM release through ECO and PLM tools, ensuring alignment with cross-functional teams. Analyze end-to-end manufacturing capacity and work with operations teams for future planning. Collaborate with cross-functional partners on developing Contract Manufacturer (CM) capabilities to prototype, launch, and transition products to high-volume production. Identify and mitigate contract manufacturer gaps in capabilities, process readiness, and documentation. Work with factory and engineering teams to troubleshoot failures, perform root cause analysis, and implement corrective actions. Participate in and help define key manufacturing processes, including NPI, product engineering, validation, and quality control. Drive improvements in SMT process flow, quality control, and inline inspections. Develop clear, precise manufacturing instructions, rework, and deviation documentation. Work cross-functionally to understand and resolve issues throughout product lifecycle with emphasis in hardware design and manufacturing. Basic Qualifications 5+ years of experience in NPI/EPE roles. Strong academic and technical background in electrical engineering or electronic manufacturing. Bachelor's in EE or equivalent experience required. Minimum of 5 years' experience in test engineering or electronics manufacturing. Entrepreneurial, open-minded behavior with a strong "customer-first" mindset. Ability to travel to CMs as needed to support production ramp-up and troubleshooting. Required Experience Strong understanding of high-tech manufacturing processes, NPI activities, and product development lifecycle. Experience working with off-shore contract manufacturers. Track record of successfully launching complex electronic products. Demonstrated ability to analyze and optimize manufacturing test data to improve yields and efficiency. Experience with DFM, Design for Testability (DFT), and Design for Assembly (DFA) methodologies. Bill of Material (BOM) structuring and risk management experience with PLM tools (e.g., Arena, Agile). Strong debugging experience for hardware design and production failures. Root cause analysis of contract manufacturing issues. Experience implementing process documentation and manufacturing best practices. Preferred Experience Familiarity with optical/electrical networking module manufacturing and testing (e.g., SFP+, QSFP, OSFP), data center class products such as servers, network switches, modular chassis, and/or PCIe add-in cards SMT process improvement and quality control methodologies. Data analysis and reporting using Python. Ability to assess and close Contract Manufacturing gaps in capability. Proficiency with EE design tools, including schematic capture and PCB layout (Cadence, Altium, etc.). Technical writing experience for generating clear and precise manufacturing documentation. Exposure to ASIC/silicon development and hardware validation processes. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Astera Labs' firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems. Job Description Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs' game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance. Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs' solutions. Basic Qualifications Strong academic and technical background in electrical or computer engineering. At a minimum, a Bachelor's is required, and a Master's is preferred. ≥12 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-minded behavior and can-do attitude. Think and act with the customer in mind! Required Experience ≥3 Years experience leading a team in a “lead by example” manner-planning sprints, assigning tasks based on individuals' strengths and career aspirations, providing constructive/encouraging feedback, maintaining a “dashboard” view of project status, chipping into shore up gaps in execution as needed. ≥5 Years hands-on experience with Silicon/System bring-up, validation, and debug experience, including in customer systems. Thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet. Good understanding of x86/ARM architecture, UEFI/Linux boot sequence. A strong background in developing bench automation techniques, especially using Python, with emphasis on execution efficiency, repeatability, data analysis and reporting. Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites. Preferred Experience Working knowledge of C or C++ for embedded FW and device drivers. Familiarity with PCIe compliance standards and the ability to follow and be involved in compliance and standard consortiums. Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis. Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, clock recovery and SerDes link budgets. Experience with PAM4 SerDes is a huge bonus! We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Role Overview As a Distinguished Product Quality Engineer, you will be responsible for ensuring the quality and reliability of Astera Labs' advanced high-speed (SerDes PAM4 and optical-integrated) semiconductor products across their lifecycle - from design through high-volume semiconductor manufacturing. You will be the primary quality interface for integrated circuit (IC) NPI-related activities, including assessing test coverage, design quality risks, and other NPI quality considerations. This NPI role will also lead the development and implementation of IC diagnostic test strategies, collaborate in defining diagnostic coverage metrics, and work with internal engineering teams to enable robust debug methodologies across leading-edge process technologies (16nm to Key Responsibilities Driving Product Quality Engineering: Work with operations, firmware, and other internal engineering teams to drive product quality improvements both as part of NPI activities and volume manufacturing. This role will participate in various NPI engineering reviews to ensure exit criteria are met, new product issues and learnings are addressed, and production issues are driven to root cause. Work with the operations engineering teams to build data systems and infrastructure to eliminate outliers, predict quality trends, and identify product quality opportunities that will improve customer outcomes. Develop signature analysis techniques to identify systemic root causes by leveraging advanced AI and/or ML techniques where appropriate. Leading NPI Quality-Related Validation & Issue Debugging: Lead the debugging of complex hardware, firmware, and software issues as part of quality team activities during NPI and high-volume production, leveraging diagnostic hooks and advanced debug tools. Develop and maintain automated diagnostic tools to scale and drive reuse across multiple product families. Partner with operations engineering to improve diagnostic efficiency, reduce overkill/retest, and improve product yield and quality. Integrate diagnostics into silicon lifecycle management, firmware release, and reliability tracking to proactively detect degradation or field reliability risks. Interoperability & System-Level Support: Work with field, firmware, and internal engineering teams to ensure interoperability, diagnostic transparency, and robust field debug capability. Diagnostic Test Development: Define and drive the deployment of diagnostic test plans, fixtures, tools, and methodologies needed for fault isolation of customer returns in PCIe, CXL, UCIe, Ethernet, and other high-speed switching products. Fan out the most successful tools for broader application in high-volume manufacturing and troubleshooting of NPI (New Products) qualification failures or field application issues. Embedded Silicon Agent Champion: Drive the external selection or internal development of embedded silicon agents to monitor temperature, voltage, noise, process, timing, etc., at the block level on-chip. Work with design teams on implementation. Collaborate with validation and design teams to debug these features in the lab during the post-silicon phase. Partner with firmware teams to leverage these features for real-time adaptive behavior. Partner with software teams to process the data and create accessible and actionable diagnostic conclusions. Design DFT Review: Work with design, operations engineering, and system validation teams to drive early Design-for-Testability (DFT) and diagnostic capabilities with design and product engineering teams. Coordinate block-by-block-level reviews to ensure no gaps in coverage and that all prior lessons learned are applied. Advanced Packaging Diagnostics: Develop diagnostic methodologies for MCM, 3DIC, and optical interconnect packages, including die-to-die and heterogeneous integration interfaces needed to diagnose, isolate, and ensure high-quality products. Skills and Experience Deep experience with digital and SerDes high-speed protocols (PCIe Gen5/Gen6, CXL, UCIe, Ethernet/SerDes) and system-level validation methodologies. Direct and deep experience working with embedded silicon diagnostic agents. Experience working with engineering teams creating product characterization and test plans, test programs, and collaborating with the greater engineering community to obtain and analyze data across process, voltage, and temperature to evaluate semiconductor products. Hands-on experience with lab debug tools (protocol analyzers, oscilloscopes, BERTs, error injection frameworks). Proficiency in scripting and software development (Python, C/C++, Java, or similar) for diagnostic automation and data analysis. Proven ability to analyze complex test data, identify root causes, and implement systemic solutions. Familiarity with semiconductor test flows (ATE, system-level test, characterization, production validation). Experience with advanced packaging technologies (MCM, 3DIC, optical) and their diagnostic/test challenges. Strong communication skills for collaborating across design, product, test, and customer teams. Demonstrated ability to influence cross-functional decisions and drive quality improvements at the organizational level. Preferred Qualifications Minimum of 5 years of experience leading a high-caliber product engineering team. Minimum of 10 years within a product or diagnostics engineering team with successful deployment of semiconductor devices into production. Strong academic/technical background in electrical engineering; Bachelor's required, Master's preferred. Experience with diagnostic firmware and test development methodologies. Knowledge of advanced techniques for anomaly detection in diagnostic/test data. Track record of leadership in new product introduction (NPI) for complex, high-speed semiconductor products. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing and other cross-functional teams to define and deliver competitive silicon, hardware and software solutions. With high visibility to the executive team and customers, this role requires strong leadership and communication skills, and a blend of technical expertise and market insight within your product domain. This is a unique opportunity to play a pivotal role in the success of our Leo Smart Memory Controller or Scorpio Smart Fabric Switch portfolio. We are scaling our product team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team. Based in San Jose, CA or Vancouver, BC, this position requires an in-person presence with travel to customers. Key Responsibilities * Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based on business goals and customer feedback. * Lead customer technical engagement: Work closely with lighthouse customers to translate their needs to competitive product requirements and secure new design-wins throughout the product lifecycle. * Support go-to-market: Leverage technical and product expertise to support product marketing and corporate marketing teams on go-to-market planning and execution, sales enablement, competitive analysis, and product positioning. * Lead product planning: Work closely with product marketing to translate product strategy into executable product plans and collaborate with Astera Labs cross-functional teams to drive products from ideation to launch. Qualifications * Bachelor's degree in engineering or compute science * 5-10 years of experience in product management, technical product marketing, applications or other customer-facing product roles within the semiconductor industry * Proven track record of defining and launching successful semiconductor products (switch products are a plus) * Deep understanding of high-speed protocols (PCIe/CXL and/or UALink are required; Ethernet and other protocols are a plus) and system architectures used in cloud and AI infrastructure * Strong strategic thinking and analytical skills, with the ability to translate customer pain points into competitive products * Excellent communication and presentation skills, with the ability to articulate complex technical concepts in a clear and compelling manner * Proven ability to collaborate effectively with cross-functional teams and drive consensus in a fast-paced, dynamic environment * Results-oriented mindset with a focus on driving measurable impact and achieving business objectives * Experience working with customers and partners to understand their needs and drive product definition * Willingness to travel as needed for customer meetings, industry events, and trade shows If you are passionate about driving innovation and shaping the future of data center connectivity through world-class products, we encourage you to apply. Join Astera Labs in unleashing the potential of cloud and AI infrastructure! Compensation will be based on leveling and experience. Base Salary Range $210,000 - $255,000 We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on projects from conception to the final production stage at contract manufacturer. The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in smaller areas with the desire to learn. Depending on your experience, you may be focusing on design/validation or automation/manufacturing. Key Responsibilities Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product Bring-up newly manufactured boards and develop the first level of software. Isolate and perform root-cause analysis of reported failures Support new platform software and hardware features Coordinate with the hardware engineering team on bring-up schedules and feature delivery Participate proactively in design discussions, design review, and project management Work independently as well as in team roles, mentor younger team members Basic Qualifications/Required Experience Bachelor's in CS/CE or equivalent experience. 8+ years of Experience in subset of diagnostic, hardware bring-up, test or manufacturing automation Knowledge of modern software development Proficiency in Python Preferred experience Experience working with datacenter-level complex electronic equipment bring-up/diagnostic/manufacturing Ability to read schematic/layout System debug experience Embedded programming and good knowledge of OS internals (Linux/Unix) Has knowledge of common interconnecting buses and interfaces such as PCIe, I2C, XAUI, 10G Ethernet drivers, FPGA, Switch chips, SSL offload, TCAM programming. Experience with DDR5 The base salary range is $203,000 - $230,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at ******************* As an Astera Labs Product Applications Engineer, you will be part of a team that supports design-in of Astera Labs' portfolio of connectivity products by the world's leading cloud service providers and server and network OEMs. In this role, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by providing insightful feedback to other internal teams to continuously improve products and processes. You will investigate and duplicate issues reported by customers, and drive critical issues to resolution. There are opportunities to support key customers directly, and also to dive deep in the lab to address the challenges associated with leading edge semiconductor products. Basic Qualifications Strong academic and technical background in electrical, electronics, or computer engineering or a closely related field. At a minimum, an engineering bachelor's degree is required. A master's degree is preferred. A minimum of 12 years' experience working with cloud service providers or server or network OEM customers to design in complex SoC/silicon products for server, storage, and/or networking applications. Entrepreneurial spirit, open-minded approach, and can-do attitude. Think and act with the customer in mind! Required Experience Silicon/system bring-up and debug experience in customer systems. Strong knowledge of embedded FW development and in-system debug Firmware development with C-language, scripting with Python or other equivalent programming languages. Strong knowledge of NRZ/PAM4 SerDes-based protocols like PCIe, Ethernet (25G and above), etc. and/or memory interfaces such as (LP) DDR5/4/3. Firsthand experience with lab equipment including traffic generators, analyzers, and high-speed oscilloscopes. Broad knowledge of NRZ/PAM4 SerDes-based protocols such as PCIe or Ethernet (25G and above). Understanding of Data Center systems such as servers, compute nodes, JBOGs/JBODs, and networking switches/routers/interconnects, etc. Technical writing skills and the ability to generate clear, precise documentation including datasheets, application notes, and similar guides for both internal audiences and customers. Preferred Experience Broad knowledge of signal processing and ECC coding for communications Device driver development Development/support for PCIe or Ethernet switch products Working with silicon characterization/validation teams to ensure desired device performance is readily achievable in customer systems. Knowledge of simulation/modeling, schematic capture, and PCB layout tools from Cadence, Altium and others. Knowledge of simulation tools such as Keysight ADS, SiSoft QCD, and others, for IBIS-AMI analysis. A strong background in high-speed board design and techniques for preserving signal integrity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Job Description: We are seeking an experienced and hands-on IC Packaging Technologist to lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions. The ideal candidate will bring a proven track record of deep technical contributions in 2.5D/3D integration, chiplet technology, fan-out wafer-level-packaging (e.g., FOWLP/FoCoS/Info), and heterogeneous integration. The successful candidate will lead strategic roadmap execution and scale innovative package solutions into production through close collaboration with OSATs, foundries and key suppliers Basic Qualifications: * M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline. * 10+ years of experience in IC packaging development and NPI for high-speed SerDes and high-performance SoCs, ASICs, or memory products * Deep hands-on expertise with FCBGA, fc CSP, co-packaged optics (CPO), and 2.5D/3D integration technologies such as CoWoS, RDL and silicon interposers, and chiplet-based architectures (e.g., BoW, UCIe); along with experience in fan-out wafer-level packaging (FOWLP/WLFO). * Strong understanding of packaging material selection, substrate stack-up, bump/RDL design, and DFM for advanced nodes * Entrepreneurial, open-minded behavior and hands-on work ethic with the ability to prioritize a dynamic list of tasks. Required Experience: * Led multiple end-to-end advanced packaging NPI programs, from concept definition, pathfinding, design, supplier engagement, process development, and successful transition to HVM. * Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G/448G PAM4. * Experience defining RDL and bump architectures to enable die-to-die chiplet integration using interconnect standards such as BoW (Bunch of Wires) and UCIe (Universal Chiplet Interconnect Express). * Demonstrated ability to lead collaboration with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development. * Deep understanding of mechanical (e.g., warpage, CTE mismatch), thermal (e.g., heat dissipation, TIM), and electrical (e.g., parasitics, signal integrity) design trade-offs in advanced package development, with a proven ability to deliver robust and manufacturable packaging solutions. * Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation. * Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing teams. Preferred Experience: * SI/PI knowledge is a plus: SI/PI concepts, S-parameter extraction, and PDN optimization using HFSS, SIwave, or Ansys Designer * Knowledge of EDA design tools is a plus: Cadence Allegro/APD, Altium, etc. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at ******************* Job Description Are you passionate about pushing the boundaries of AI software, and AI system management architecture? Do you thrive when pitching cutting-edge technology solutions to customers and industry partners? We are seeking a creative customer facing Technologist to help facilitate Astera's development of our COSMOS software solutions. In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in software architecture, SOC architecture, PCIe/CXL/Ethernet/UALink technologies, system management, and AI hardware-software co-design. You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers challenges in hyperscale data centers This role is fully in person, in San Jose, CA. Some travel may be required. Basic qualifications BS in Computer Science, or Electrical/Computer engineering, MS or PhD preferred. ≥10 years' experience with software architecture developing datacenter software solutions for AI systems and switches Experience working in a customer-facing role with the ability to articulate technical concepts, influence decision-making, and build business cases for new software products, features, or services Ability to dig deeply into technical challenges and use cases Software architect for full stack silicon-based solutions including FW development, drivers, SDK, and application development Experience with Linux kernel and driver development/debug Experience with AI system software and management stacks including GPU drivers and collective libraries Strong understanding of datacenter system and rack management solutions using industry standards from DMTF, OpenBMC, OCP (e.g. SAI), and the Linux Foundation. Strong understanding of “full stack” solutions from silicon to application integration Excellent communication and interpersonal skills with the ability to collaborate effectively with internal teams and external partners. Demonstrated leadership capabilities with a track record of driving technical initiatives and delivering results in a fast-paced environment. Willingness to travel occasionally for customer meetings and industry events. Preferred experience Expertise in PCIe, CXL, UALink, and/or Ethernet management interfaces Expertise in switch, fabric, and device management Experience in product integration with BIOS, kernel, OS, tooling, and BMCs Experience with benchmarking and performance optimization Existing engagement and robust network within industry organizations such as PCI-SIG, OCP, DMTF, CXL, IEEE, etc. Deep experience driving silicon definition based on customer requirements and managing product exploration internally. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.