Research and development engineer jobs in Gilroy, CA - 5,801 jobs

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page. Optical Engineer Responsibilities: Collaborate with Meta engineers on the next generation optical communication technology with a particular focus on the testing of optical modules and subsystems for Data Center applications. Work in a collaborative environment across Meta teams including SW, Thermal, Mechanical, and EE. Develop test and simulation methodologies relevant for next-generation, high-speed optical technologies. Develop automation practices and solutions for lab testing. Lead new optical communication NPI programs, working closely with optics vendors and ODMs. Interface with the industry and contribute to the RFI/RFP process for optical solutions. Communicate complex optical hardware requirements to non-experts both internally and to industry-facing stakeholders. Minimum Qualifications: Master's degree (or foreign degree equivalent) in Electrical Engineering, Computer Engineering, Optical Engineering, Physics, or a related field and 3 years of experience in the job offered or in a computer-related occupation Requires 3 years of experience in the following: Imaging optics for both photographic and computer vision applications Both sequential and non-sequential optical design software (e.g. Zemax, Code V, LightTools, FRED and/or ASAP) Image quality evaluation, imaging sensor operation and characterization, stray light modeling and analysis, camera module or lens testing and characterization, imaging and illumination optics design and manufacturing Theoretical analysis using MATLAB, Python or similar programs Statistical analysis using MATLAB Public Compensation: $181,390/year to $189,200/year + bonus + equity + benefits Industry: Internet Equal Opportunity: Meta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com. #J-18808-Ljbffr

Physical Design Engineer - New College Grad 2026 page is loaded## Physical Design Engineer - New College Grad 2026locations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2009983We are now looking for a Physical Design Engineer!NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life's work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.**What you will be doing:*** As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.* Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.* This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc\_shell, Innovus, SeaHawk.* You will interact with a diverse team engineers.**What we need to see:*** Completing an BSEE, MSEE or PhD (or equivalent experience).* Deep understanding of VLSI and Physical Design related basics & concepts.* Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.* Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.* Previous internship or project experience in physical design implementation With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until December 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

About Commonwealth Fusion Systems: Commonwealth Fusion Systems is on a mission to deliver the urgent transition to fusion energy. Combining decades of research, top talent, and new technologies, we're designing and building commercially viable fusion power plants. And working with policymakers and suppliers to build the energy industry of the future. We're in the best position to make it happen. Since 2018, we've raised nearly $3 billion in capital, making us the largest and leading private fusion company in the world. Now we're looking for more thinkers, doers, builders, and makers to join us. People who'll bring new perspectives, solve tough problems, and thrive as part of a team. If that's you and this role fits, we want to hear from you. Principal Mechanical Engineer We're looking for a Principal Mechanical Engineer to join our R&D and equipment design team to help build the next generation of thin‑film deposition technology. The Principal Mechanical Engineer will be responsible for the design and implementation of advanced R&D equipment and complex machinery. This role requires strong technical expertise, procedural discipline, and the ability to collaborate across engineering and technology functions to ensure safe, reliable, and high‑performance equipment. If you enjoy working on complex design problems, mentoring others, and solving problems in a collaborative, fast‑paced environment, this is your opportunity to make an impact. What you'll do: Lead the design and implementation of advanced R&D equipment for thin‑film processing, including ownership of key mechanical modules and sub‑systems Define system level requirements and drive innovative design concepts to meet these requirements Lead design reviews for overall mechanical system and key mechanical subsystems Generate and maintain interfaces with other engineering subsystems Report on and be accountable for project progress to stakeholders Work effectively within a multi‑disciplinary team of top scientists and engineers Mentor engineering staff for effectiveness and delivery of on‑time & in‑spec outcomes Get things done: drive projects, consistently deliver, act with speed What we're looking for: Master's degree in Mechanical Engineering or related field (or equivalent industrial experience) 15+ years of experience with at least 7 years of experience working as a principal mechanical design engineer or engineering team lead in a relevant context: design and implementation of R&D systems and manufacturing equipment Ability to conceive of novel solutions for complex engineering systems in challenging environments Expertise with 3D modeling; preferred experience with SolidWorks and NX Experience with COMSOL, ANSYS or other FEA tools Ability to select and qualify vendors for components or subsystems Demonstrated ability to lead in either direct or matrix structures Strong verbal and written communication skills and a dedication to high‑quality documentation Bonus points for: Ph.D. in Mechanical Engineering or related field (or equivalent industrial experience) Prior success building first‑of‑kind or experimental tools for material science or semiconductor R&D Familiarity in applying Semi‑S8, ASME, ACI, ASTM, and other mechanical standards to design solutions Experience with the operation of equipment in a manufacturing environment Must‑have Requirements: Ability to occasionally lift up to 50 lbs Perform activities such as stooping, climbing, standing, or sitting for extended periods of time Dedication to safety to mitigate industrial hazards that may include heat, cold, noise, fumes, strong magnets, lead (Pb), high voltage, and cryogenics Willingness to travel or work required nights/weekends/on‑call occasionally $150,000 - $225,000 a year Benefits Competitive compensation with equity 12.5 Company‑wide Holidays Flexible vacation days 10 sick days Generous parental leave policy Health, dental, and vision insurance 401(k) with employer matching Professional growth opportunities Team‑building activities #LI‑Onsite At CFS, we excel in fast‑paced environments, driven by our values of integrity, execution, impact, and self‑critique. As we grow, we're eager to bring on mission‑driven folks who offer diverse perspectives and fresh ways to tackle challenges. We value diversity deeply and are proud to be an equal opportunity employer by choice. We consider all qualified applicants equally, regardless of race, color, national origin, ancestry, citizenship status, protected veteran status, religion, physical or mental disability, marital status, sex, sexual orientation, gender identity or expression, age, or any other basis protected by law. This role requires compliance with U.S. laws concerning the export of controlled or protected technologies or information (collectively, “Export Control Laws #J-18808-Ljbffr

A leading tech company invites applications for a Machine Learning Engineer to advance AI research in California. The role focuses on Generative AI and requires a PhD or Master's degree, with a minimum of 3 publications in AI. The candidate will collaborate across teams and publish findings, contributing to networking solutions and AI innovations. This full-time position offers a competitive salary and benefits, fostering an inclusive workplace culture. #J-18808-Ljbffr

Join Us in Building the Future of Home Robotics At Sunday, we're developing personal robots to reclaim the hours lost to repetitive tasks. We're focused on an ambitious goal to make generalized robots broadly accessible, enabling households to take back quality time. We have spent the last 18 months building a talented team, securing capital, and validating our technology. We are now seeking passionate individuals to join us in the next phase of our growth. If you are ready to apply your skills to the forefront of robotics innovation, we'd love to hear from you. What to Expect In building robots for the home, we are tackling a true grand challenge in robotics: dexterous and safe mobile manipulation in unstructured environments. To make this possible, we are building across the entire robotics stack. We're training state-of-the-art AI models that leverage our large-scale, high-quality, real-world data collection system. At the same time, we're building a new kind of consumer hardware product, which will be deployed into homes and delivering real value for real customers. As an early member of a small, cross-functional team, you'll play a key role in pushing both our technology and product forward: advancing the frontier of embodied AI, and soon giving countless hours back to our customers so they can spend more time on the things they value most. As a Machine Learning Research Engineer, you will work on the software and algorithms that enable our robots to complete dexterous manipulation tasks in home environments. You will leverage our unique large-scale in-the-wild data collection operation and our growing robot fleet to continuously add new behaviors and improve robustness across tasks and environments. What You'll Do Design and develop state-of-the-art robot learning algorithms for manipulation and controls Leverage large-scale in-the-wild data collection to develop generalizable robot behaviors Own the end-to-end loop from task definition and data curation to model training, evaluation, and on-robot deployment Collaborate closely with a full-stack robotics team to develop a consumer personal robot Write maintainable, production quality code for research and deployment What You'll Bring 3+ years (or equivalent) working on machine learning for robotics, controls, or perception Proficiency with Python and any deep learning framework (PyTorch preferred) Hands-on experience with robot learning for real-world tasks, including offline/online training and evaluation Implement tooling for visualization, debugging, and evaluation of data and learning pipelines Communicates clearly and collaborates effectively, thriving in fast-moving, cross-functional teams Nice to Have Familiarity with classical robotics fundamentals (e.g. controls, planning, state estimation) Comfortable profiling and optimizing for latency, memory, and compute on edge devices Experience with large-scale model training pipelines (LLM/VLM/VLA) At Sunday Robotics, we're building technology shaped by real people - curious, creative, and diverse. We're proud to be an equal opportunity employer and consider all qualified applicants regardless of race, color, religion, gender, gender identity or expression, sexual orientation, national origin, genetics, disability, age, or veteran status. Even if you don't meet every single requirement, we encourage you to apply. Studies show that women and underrepresented groups often hold back unless they meet 100% of the criteria - we don't want that to be the reason we miss out on great talent. #J-18808-Ljbffr

A cutting-edge robotics company in Palo Alto is seeking an engineer to develop advanced humanoid technologies. The role involves research, design, and prototyping critical components of robots. Candidates should have strong engineering principles and a background in Mechanical or Electrical Engineering. This position requires in-person collaboration to foster innovation. Competitive compensation and inclusive work culture are offered. #J-18808-Ljbffr

A technology firm specializing in integrated task systems seeks a Machine Learning Researcher / ML-Ops Engineer to advance computer vision and sensor fusion capabilities. The role involves implementing machine learning pipelines and optimizing models for deployment. Candidates should have a strong Python background and experience in deep learning frameworks like PyTorch and TensorFlow. This position in Palo Alto, California, offers competitive compensation and a collaborative work environment. #J-18808-Ljbffr

A leading scientific institution in Palo Alto is seeking an experienced machine learning research engineer to advance biological modeling capabilities. The ideal candidate will have a strong background in machine learning and deep learning, as well as excellent communication skills to work within a multidisciplinary team. The position offers a base salary range of $168,000-$242,500 and involves collaboration with biologists on innovative projects. #J-18808-Ljbffr

Meet the Team Splunk, a Cisco company, is building a safer, more resilient digital world with an end‑to‑end, full‑stack platform designed for hybrid, multi‑cloud environments. The Splunk AI Platform and Services team provides the core runtime and developer experience that power AI across Splunk and Cisco. We manage large-scale, multi-tenant LLM inference across major cloud providers and build platform services to support these workloads. We also provide VectorDB/RAG services and MCP services that make AI workloads secure, observable, and cost-efficient for product teams. On top of this foundation, we deliver agentic frameworks, SDKs, tools, and evaluation/guardrail capabilities that help teams quickly build reliable GenAI assistants and automation features. You'll join a group that sits at the intersection of distributed systems, ML, and developer experience, grounded in operational excellence and a culture of impact‑driven, cross‑functional collaboration. Your Impact Implement features for GenAI services and APIs that power chat assistants, and automation workflows across Splunk products. Help build and maintain RAG pipelines: retrieval orchestration, hybrid search, chunking & embeddings, and grounding with logs/events/metrics. Contribute to agentic and multi‑agent workflows using frameworks like LangChain or LangGraph, integrating with MCP tools, internal APIs, and external systems. Develop and refine developer‑facing SDKs, templates, and reference apps (primarily Python/TypeScript) that make it simple for other teams to compose tools, chains, and agents on top of it. Integrate with LangSmith or similar eval stacks to instrument prompts, capture traces, and run evaluations under the guidance of more senior engineers and scientists. Collaborate with product managers and UX to turn user stories into GenAI experiences, iterate based on feedback, and ship features that move customer and business metrics. Apply and advocate responsible AI practices in day‑to‑day work: grounding, guardrails, access controls, and human‑in‑the‑loop flows. Minimum Qualifications: Bachelor's degree in computer science, Engineering, or equivalent practical experience. 5+ years of hands‑on experience building and operating backend or distributed systems in production or 2+ years of experience with a Master's degree Proficiency in at least one modern programming language (e.g., Python, TypeScript/JavaScript, Go, or Java) and solid software design/debugging skills. Some hands‑on experience with LLM APIs and ecosystems (e.g., OpenAI, Claude, Bedrock, or OSS models such as Llama) and related production features. Familiarity with web APIs and microservices (REST/gRPC), including testing, deployment, and basic observability (logs/metrics). Demonstrated ability to work end‑to‑end on features: collaborate on design, implement, write tests, help deploy, and iterate based on metrics or feedback. Preferred Qualifications: Experience or strong interest in RAG systems and vector databases (Weaviate, Qdrant, Milvus, FAISS, etc.). Exposure to agentic frameworks (LangChain, LangGraph, LlamaIndex, Semantic Kernel, or similar) and tool/agent orchestration patterns. Familiarity with LangSmith or similar evaluation platforms, or experience instrumenting prompts/pipelines for quality and debugging. Background contributing to platform or Developer experiences capabilities: internal libraries, SDKs, templates, or shared components that other engineers use. Experience with full‑stack development for GenAI interfaces (React/TypeScript), including prompt UX or conversation flows, is a plus. Understanding basic AI safety and governance concepts (guardrails, data privacy, RBAC) and how they apply in an enterprise environment. Strong communication skills and a growth mindset, comfortable asking questions, giving/receiving feedback, and learning from more senior teammates. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $181,000.00 to $235,000.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $181,000.00 - $270,300.00 Non‑Metro New York state & Washington state: $165,300.00 - $240,600.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr

A leading optical technology startup is seeking a Senior MEMS Design Engineer to design and optimize MEMS devices crucial for optical circuit switches. The role involves collaboration with multidisciplinary teams and the expertise in multi-physics modeling is essential for ensuring performance and reliability. Candidates should have a Master's or PhD in Applied Physics or related fields, with over 5 years of experience in MEMS design and a solid understanding of semiconductor processes. The position offers a salary ranging from $180,000 to $260,000 based on experience and skills. #J-18808-Ljbffr

Physical Design Engineer Job at Apple, Cupertino, CAJob Description Physical Design Engineer Department: Hardware Imagine what you can do here. Apple is a place where extraordinary people gather to do their best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Description Apple Inc. has the following available in Cupertino, California, and various unanticipated locations throughout the USA. Responsible for physical design and implementation of partitions. Build partition architecture and drive physical aspects early in the design cycle. Physically implement design partitions (from netlist to tape-out) for a highly complex System-on-Chip (SoC) utilizing state-of-the-art process technology. Work on partition-level place and route (P&R) implementation, including floor planning, clock and power distribution, timing closure, physical and electrical verification. Complete netlist to GDSII implementation for partitions meeting schedule and design goals. Oversee timing, physical, and electrical verification, and drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $151,091 - $214,500/year, depending on skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees have the opportunity to participate in Apple's stock programs, receive benefits including medical and dental coverage, retirement benefits, discounts, free services, educational reimbursement, and potential bonuses or relocation assistance. Learn more about Apple Benefits. Minimum Qualifications Master's degree or foreign equivalent in Electrical Engineering or related field. 2 years of relevant experience. 1 year of experience with each of the following: Encounter Design System tool, QRC, Calibre, Voltus, Primetime. Preferred Qualifications N/A Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Note: Apple benefits, compensation, and employee stock programs are subject to eligibility and other terms. This job posting appears to be active and does not indicate it is expired. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.Join us in our journey to becoming the world's #1 FPGA company!Altera is seeking a **Senior Design Automation Engineer** to join our Design Methodology Automation and Infrastructure Team.The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next-generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross-functional teams to deliver world-class automation solutions.**Key Responsibilities:*** Architect next-generation unified FPGA/SoC design methodologies spanning Front-End, handoff to Backend, Design Verification, Design-For-Test (DFT), Design Data Management/Release flows, and FPGA-specific flows such as Design Intent and Configuration Management.* Develop and integrate state-of-the-art EDA solutions, including ML/AI-enhanced tools, flows, and methodologies-sourced externally or developed internally-to create sustainable, scalable automation solutions for multiple chip design programs.* Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.* Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn-around time, and enhance design optimization.* Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.* Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.* Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.* Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross-functional initiatives to streamline FPGA design execution.* Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.* Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimizations.* Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next-generation capabilities.* Mentor and provide technical leadership to junior engineers within the Design Automation organization.#LI-MD1**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$142,600 - $206,500 USDWe use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 10 years of experience in IC Design or Design Automation and experience in the following:* Extensive experience with industry-standard EDA tools and hands-on expertise in design methodologies across multiple domains, such as Front-End Logic Design flows, Design Intent and FPGA-specific flows, Design Verification flows, and Design-for-Test (DFT) flows (with Back-End flow knowledge considered a plus).* Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.* Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimizations.* Proven leadership skills for driving collaborative, cross-functional projects, with strong communication and influencing abilities### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

An automotive giant is seeking a Staff ML Engineer for their ML Compute Platform to scale backend services and contribute to AI infrastructure. Responsibilities include designing software components, improving system efficiency, and leading initiatives. Candidates should have 7+ years of experience and expertise in languages like Go, C++, or Python, as well as a solid background in distributed systems. Join a team that's transforming mobility and tackling complex engineering challenges with AI applications. #J-18808-Ljbffr

Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams Chip/Block Level Floorplanning and pin assignment Review top-level/block-level clock specifications for completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing) Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification) Presentations and Customer Interaction in customer meetings Necessary Qualifications: BSEE, with 9+ years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes. Hands-on Experience with implementation EDA tools like ICC2/Innovus. Scripting (Perl/Tcl/Python) is required. Good understanding of ASIC frontend design. Experience in both Flat and Hierarchical layouts. Strong problem‑solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required. Experience with power analysis and IR‑drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime). Experience with Physical Verification and fix PV errors in layout. Expert handling of Verilog HDL based Netlists, Physical design libraries. Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings. Compensation: $190,000.00 - $200,000.00 per year MAKING THE INDUSTRY'S BEST MATCHES DBSI Services is widely recognized as one of the industry's fastest growing staffing agencies. Thanks to our longstanding experience in various industries, we have the capacity to build meaningful, long‑lasting relationships with all our clients. Our success is a result of our commitment to the best people, the best solutions and the best results. Our Story: Founded in 1995 Privately Owned Corporation Managing Partner Business Model Headquartered in New Jersey US Based Engineers Only Methodology and Process Driven Top performing engineers are the foundation of our business. Our priority is building strong relationships with each employment candidate we work with. You can trust our professional recruiters to invest the time required to fully understand your skills, explore your professional goals and help you find the right career opportunities. #J-18808-Ljbffr

Credo is engineering the future of high-speed connectivity for the AI-driven world. With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers. Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure. At Credo, you'll be part of a team of world-class technologists and engineers that thrive on pushing the limits of what's possible for some of the world's most important companies. Our portfolio includes cutting edge solutions including our software, optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables (AECs) all designed for maximum performance, energy efficiency, and scalability. We foster a culture of technical excellence, collaboration, and continuous learning, where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale. Join us and help us architect the next generation of disruptive networking technologies - because at Credo, We Connect. About the Role As a Senior Physical Design Engineer, you will manage all aspects of physical design and implementation for Credo SoC designs. This role involves close collaboration with the local frontend team and PD/integration teams in China and Taiwan to ensure successful tapeouts. Responsibilities Lead and drive top-level, IP, and block-level physical implementation from RTL to GDSII. Focus on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems. Establish and maintain physical design methodologies, flow automation, chip floorplanning, power/clock distribution, chip assembly, P&R, and timing closure. Perform static timing analysis, power and noise analysis, and physical verification. Collaborate closely with frontend and integration teams to ensure successful tapeouts. Basic Qualifications BS/MS in EE/CS with 10+ years of hands-on experience in back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies. Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure. Experience with 5nm and lower technology nodes. Strong proficiency with EDA tools such as Cadence Innovus and Synopsys Fusipn Compiler. Solid knowledge on static timing analysis (PrimeTime/Tempus), EM/IR-Drop/crosstalk analysis (PTSI/Voltus/Redhawk), extraction (Quantus/StarRC). Preferred Qualifications Familiarity with DRC, Antenna, LVS, ERC tools like Calibre. The base salary range for this position is $140,000 - $170,000 a year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits. Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email ********************. #J-18808-Ljbffr

As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison, congestion & DRC analysis, and design optimization. You may also do synthesis, debugging & data analysis, scripting, STA or timing analysis. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, California and joining a team of engineers dedicated to pushing the envelope for the world's leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office. Responsibilities Responsible for the physical implementation on TSMC's most advanced process nodes. Netlist-to-GDS flow including block/soc-level placement, clock tree synthesis, routing, and design optimization. Evaluate flow and methodologies to optimize power, performance, and area (PPA). Analyze standard cell library utilization and route congestion data. CAD development including customizing design flows and creating comparison tables using scripting language such as TCL, Python, Perl and Shell. Minimum Qualifications Master's degree in Electrical Engineering or Computer Science with a minimum of 4 years of relevant industry experience. In depth knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation. Knowledge on physical design implementation flows, auto placement and routing (APR), static timing analysis (STA), layout design, physical design verification (PDV), IREM signoff, and CAD development. Experiences in research projects or internship related to RTL coding, synthesis, digital design and testing, physical implementation or design verification. In depth knowledge of major EDA tools/design flows. Experience in Python/Perl/TCL language programming and CSH script. Ability to work regularly at a customer site in the South Bay area. Preferred Qualifications Able to independently complete Netlist-GDS P&R. Excellent communication skills and strong problem-solving skills. Positive, Active, Collaborative, Self-motivated, Adaptable and Flexible. TSMC N16 and below technology. Experience in software programming is a plus. Company Description As a trusted technology and capacity provider, TSMC is driven by the desire to be: The world's leading dedicated semiconductor foundry. The technology leader with a strong reputation for manufacturing excellence. Advancing semiconductor manufacturing innovations to enable the future of technology. TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world's leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry's leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting‑edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity. Diversity statement TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law. TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at G_Accommodations@tsmc.com. TSMC confirms to all applicants its commitment to meet TSMC's obligations under applicable employment law. Reasonable accommodations will be determined on a case‑by‑case basis. For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC Technology, Inc. may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC Technology, Inc. obtaining any export license or other approval that may be required by the U.S. Government. Pay Transparency Statement At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $108,000/yr and $167,500/yr. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC's total compensation package consists of market competitive pay, allowances, bonuses and comprehensive benefits. We also offer extensive development opportunities and programs. #J-18808-Ljbffr

DataVisor is a next generation security company that utilizes industry leading unsupervised machine learning to detect fraudulent activity for financial transactions, mobile user acquisition, social networks, commerce and money laundering. Our solution is used by some of the largest internet properties in the world, including Pinterest, Synchrony Financial, AirAsia and PingAn, to protect them from the ever-increasing risk of fraud. Our award-winning software is powered by a team of world‑class experts in big data, security, and scalable infrastructure. Our culture is open, positive, collaborative, and results driven. Come join us! The modeling / data science team holds the secret sauce of DataVisor. We run our advanced core unsupervised analytics engine and machine learning models on hundreds of billions of events from hundreds of millions of users. We are a mix of machine learning engineers and inquisitive data scientists. We love finding beautiful patterns in big data to catch and prevent malicious attacks against good users. We're also not afraid to get our hands dirty; we get deep satisfaction coming up with and implementing new ideas for improvements to our detection engine. If you have a knack for wrangling big data, are excited by the idea of being part of new technological frontiers, and want to work on a team that impacts the company's bottom line, we'd love to talk to you. 2+ years experience with Java/C++ Familiar with common data structures and algorithms. Be able to write efficient and optimized computer programs 1+ years experience with web backend or Hadoop/MapReduce/Spark 1+ years experience with machine learning/data science preferred Anti‑fraud modeling in financial industry a plus Bachelor degree required, Master/PhD degree preferred We offer a flexible schedule with competitive pay, equity participation and health benefits, along with catered lunch, company off‑sites, and game nights, as well as the opportunity to work with a world class team. #J-18808-Ljbffr