Research and development engineer jobs in Santa Cruz, CA - 6,143 jobs

AOSense, Inc. is the leading developer and manufacturer of innovative quantum technologies employing atom optics. Our products use frequency-stabilized lasers and atoms in a vacuum cell to measure accelerations, rotations, magnetic fields, and time with unparalleled accuracy and stability. Our staff includes physicists, engineers, and technicians with expertise covering a wide array of disciplines. Our teams are dynamic and fast paced since our hardware is cutting edge. POSITION SUMMARY: We are seeking an R&D technician who specializes in precision assembly and testing. As a hands-on R&D Technician at AOSense, you will work with physicists and engineers to build and test high-performance, fieldable accelerometers, gyroscopes, gravimeters, atomic clocks, frequency standards, and magnetometers, as well as component technologies that we sell commercially to the R&D community. RESPONSIBILITIES: Collaborate with physicists and engineers to assemble and test complex quantum sensor and atomic clock hardware Procure and track inventories of mechanical, optical, vacuum, and electrical components Coordinate component and subsystem fabrication, assembly, and test Assemble precision mechanical systems Align lasers through optical systems Procure and maintain laboratory equipment and supplies Collaborate with engineers to define and implement test plans Bake out and leak test vacuum systems Document and report results of validation testing Requirements Demonstrated success in precision mechanical assembly of prototypes and products Enthusiasm for developing expertise in new fabrication disciplines Proven organizational skills and attention to detail Hands-on experience with test equipment Excellent troubleshooting skills Applicants should thrive in a dynamic environment U.S. Government contracts require applicants to be U.S. citizens or permanent residents DESIRED EXPERIENCE: Expertise aligning and securing micro-optical components Hands-on experience with vacuum system assembly and testing Adept in glovebox assembly work Sensitivity to cleanliness requirements of vacuum and optical assemblies Skilled in mechanical prototyping, including basic machining and finishing operations Practical experience with advanced bonding methods, including soldering, brazing, and adhesives Proficiency with SolidWorks mechanical design software Familiarity with electronics prototyping, including reading schematics, PCB fabrication, assembly, soldering, and rework Experience testing low-noise analog, mixed-signal, and rf electronics Basic knowledge of data acquisition and analysis software such as LabVIEW, MATLAB, and Python EDUCATION AND EXPERIENCE: Associate degree in a relevant technical field or equivalent professional experience, with experience in an R&D environment Benefits Salary depends on qualifications and experience Medical and dental Retirement Stock plan AOSense is an equal opportunity employer (EOE) and considers qualified applicants for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran or disability status, or any other federal, state or local protected class. AOSense is committed to providing equal employment opportunity to qualified individuals with disabilities. If you are disabled and require special assistance or a reasonable accommodation while seeking employment with AOSense, then please contact us via email at ******************* or call ************** x210

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

Reports to: Managing Principle Mechanical Engineer, R&D Workplace Type: Hybrid, on-site in Santa Cruz an average of 4-days per week Capstan Medical:Creating a new standard for minimally invasive structural heart treatment Who we are: At Capstan Medical, we're driven by an unwavering commitment to transforming the treatment of heart valve disease. By merging surgical robotics with catheter-based technology and next generation implants, we've pioneered a patient-optimized approach to repair and replace heart valves. Our innovative technology offers a significantly less invasive alternative to traditional open-heart surgery while ensuring precise and reliable placement of the heart valve implant. With these advancements, we may be able to provide patients with a solution to their heart valve disease while significantly reducing recovery time and minimizing the risk of complications. With a dedicated team of heart valve device experts and robotics engineers, we are fully committed to developing a comprehensive and transformative solution that will positively impact the lives of individuals affected by this condition. Capstan Medical is uniquely positioned in Santa Cruz. This gives us access to the amazing technical talent of the Bay Area, but in an environment that we feel is conducive to doing our best creative work. Our office is adjacent to large tracts of open space with bicycle trails straight from the office doors offering access to the hills and beaches of Wilder Ranch State Park for road/mountain bicycle riding, hiking, and surfing. Come join us and become part of a team revolutionizing heart valve treatment! The Opportunity: We are building a novel medical robotic application, bringing together an exciting set of hardware and software into an elegant product. We are looking for someone who can take a mechanical system of the robot design from initial concept all the way to product. What You'll Do: Collaborate with Manufacturing and Clinical teams on designs, incorporating this input into quick and effective design iterations. Lead and set direction for system and subsystem architectures and mechanical design efforts while owning cross-functional mechanical deliverables and technical strategy Participate in building and bringing up prototype robotic systems and support all things mechanical in their pre-clinical lab use. Lead alignment of complex technical topics and hardware architecture across the Mechanical Engineering team and broadly across the R&D organization and Capstan. Document and communicate learnings on design manufacturability and reliability to the broader hardware team, mentoring others in best practices and scalable design approaches Document and communicate your work through design reviews and as appropriate released documents as part of the product development process Identify gaps and pitch in as needed to ensure that the team meets their goals and objectives, driving alignment across teams when priorities conflict Strengthen the team by providing leadership and mentorship on best practices and design strategies as they grow in their abilities to develop performant, scalable, and elegant designs. Be a valuable partner with feedback and collaboration in brainstorming and design reviews. What You'll Need: BS in Mechanical Engineering or related engineering discipline, or equivalent work experience Expecting 12+ years of relevant experience (medical device experience preferred) Comfort working with high levels of ambiguity and an ability to convert that into tangible outcomes Experience with designing, manufacturing transfer, and shipping of medical device capital equipment or equivalent complexity systems Deep expertise in areas particular to robotic system design: kinematics, mechanisms, bearings, gears, sensors, actuators. Experience with medical device (or equivalent) development process, design control, design verification, and regulatory processes Ability to work in a hybrid work environment, working onsite in Santa Cruz on average 4 days a week Ways To Stand Out: Experience with the full commercial lifecycle from concept through reacting to and addressing field issues with your designs. Skills with Python or Matlab for data analysis, simulation, and interacting with robotic equipment. Excessive nerdiness about manufacturing, mechanisms, robots, or any other adjacencies. Leadership experience. While this role is as an individual contributor, it is a position of significant technical and thought leadership within the company. Why Join Us: We offer a fun, fast-paced, collaborative environment where you will be working on transformational technologies in the cardiac healthcare space. We offer outstanding benefits with medical, dental, and vision covered at 100% for you and your family, as well as flex time off. We thrive in our work-hard, play-hard environment. Bring your bike or running shoes if you'd like or just be ready to enjoy a fun office outing. We enjoy time inside the office and out! We are an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, sex, sexual orientation, gender identity, veteran status, and disability, or other legally protected status. #J-18808-Ljbffr

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page. Optical Engineer Responsibilities: Collaborate with Meta engineers on the next generation optical communication technology with a particular focus on the testing of optical modules and subsystems for Data Center applications. Work in a collaborative environment across Meta teams including SW, Thermal, Mechanical, and EE. Develop test and simulation methodologies relevant for next-generation, high-speed optical technologies. Develop automation practices and solutions for lab testing. Lead new optical communication NPI programs, working closely with optics vendors and ODMs. Interface with the industry and contribute to the RFI/RFP process for optical solutions. Communicate complex optical hardware requirements to non-experts both internally and to industry-facing stakeholders. Minimum Qualifications: Master's degree (or foreign degree equivalent) in Electrical Engineering, Computer Engineering, Optical Engineering, Physics, or a related field and 3 years of experience in the job offered or in a computer-related occupation Requires 3 years of experience in the following: Imaging optics for both photographic and computer vision applications Both sequential and non-sequential optical design software (e.g. Zemax, Code V, LightTools, FRED and/or ASAP) Image quality evaluation, imaging sensor operation and characterization, stray light modeling and analysis, camera module or lens testing and characterization, imaging and illumination optics design and manufacturing Theoretical analysis using MATLAB, Python or similar programs Statistical analysis using MATLAB Public Compensation: $181,390/year to $189,200/year + bonus + equity + benefits Industry: Internet Equal Opportunity: Meta is proud to be an Equal Employment Opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com. #J-18808-Ljbffr

Physical Design Engineer - New College Grad 2026 page is loaded## Physical Design Engineer - New College Grad 2026locations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2009983We are now looking for a Physical Design Engineer!NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life's work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.**What you will be doing:*** As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.* Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.* This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc\_shell, Innovus, SeaHawk.* You will interact with a diverse team engineers.**What we need to see:*** Completing an BSEE, MSEE or PhD (or equivalent experience).* Deep understanding of VLSI and Physical Design related basics & concepts.* Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.* Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.* Previous internship or project experience in physical design implementation With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until December 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. The Role This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The Person Strong analytical and problem solving skills with a pronounced attention to detail Strong communication, mentoring and leadership skills Self-driven, Methodical and attention to detail in troubleshooting and problem-solving Can work well with cross functional teams Excellent verbal and written communication skills Responsibility Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.) Create RTL designs using Verilog/SystemVerilog for high-performance applications Perform FPGA prototype design, implementation, and bring‑up activities Create comprehensive design documentation, specifications, and technical reports Perform timing analysis, closure, and optimization using Vivado tools Conduct board-level bring‑up and system integration testing Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements Independently troubleshoot and resolve challenging technical issues Work closely with hardware, software, and systems engineering teams Participate in design reviews and technical discussions Communicate project status, risks, and technical challenges to stakeholders Preferred Skill Set & Experience Extensive experience in field of FPGA hardware prototyping Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc Experience with Xilinx Versal ACAP or UltraScale+ devices Knowledge of FPGA synthesis tools and methodologies Familiarity with Python/TCL scripting for design automation Knowledge of FPGA-based system architecture and hardware/software co‑design Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers) Fluent in System Verilog and a familiarity with simulation and debug Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus EDUCATION BS (or higher) degree in Electrical or Computer Engineering desired LOCATION Santa Clara, CA This role is not eligible for visa sponsorship. #LI‑SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

About Commonwealth Fusion Systems: Commonwealth Fusion Systems is on a mission to deliver the urgent transition to fusion energy. Combining decades of research, top talent, and new technologies, we're designing and building commercially viable fusion power plants. And working with policymakers and suppliers to build the energy industry of the future. We're in the best position to make it happen. Since 2018, we've raised nearly $3 billion in capital, making us the largest and leading private fusion company in the world. Now we're looking for more thinkers, doers, builders, and makers to join us. People who'll bring new perspectives, solve tough problems, and thrive as part of a team. If that's you and this role fits, we want to hear from you. Principal Mechanical Engineer We're looking for a Principal Mechanical Engineer to join our R&D and equipment design team to help build the next generation of thin‑film deposition technology. The Principal Mechanical Engineer will be responsible for the design and implementation of advanced R&D equipment and complex machinery. This role requires strong technical expertise, procedural discipline, and the ability to collaborate across engineering and technology functions to ensure safe, reliable, and high‑performance equipment. If you enjoy working on complex design problems, mentoring others, and solving problems in a collaborative, fast‑paced environment, this is your opportunity to make an impact. What you'll do: Lead the design and implementation of advanced R&D equipment for thin‑film processing, including ownership of key mechanical modules and sub‑systems Define system level requirements and drive innovative design concepts to meet these requirements Lead design reviews for overall mechanical system and key mechanical subsystems Generate and maintain interfaces with other engineering subsystems Report on and be accountable for project progress to stakeholders Work effectively within a multi‑disciplinary team of top scientists and engineers Mentor engineering staff for effectiveness and delivery of on‑time & in‑spec outcomes Get things done: drive projects, consistently deliver, act with speed What we're looking for: Master's degree in Mechanical Engineering or related field (or equivalent industrial experience) 15+ years of experience with at least 7 years of experience working as a principal mechanical design engineer or engineering team lead in a relevant context: design and implementation of R&D systems and manufacturing equipment Ability to conceive of novel solutions for complex engineering systems in challenging environments Expertise with 3D modeling; preferred experience with SolidWorks and NX Experience with COMSOL, ANSYS or other FEA tools Ability to select and qualify vendors for components or subsystems Demonstrated ability to lead in either direct or matrix structures Strong verbal and written communication skills and a dedication to high‑quality documentation Bonus points for: Ph.D. in Mechanical Engineering or related field (or equivalent industrial experience) Prior success building first‑of‑kind or experimental tools for material science or semiconductor R&D Familiarity in applying Semi‑S8, ASME, ACI, ASTM, and other mechanical standards to design solutions Experience with the operation of equipment in a manufacturing environment Must‑have Requirements: Ability to occasionally lift up to 50 lbs Perform activities such as stooping, climbing, standing, or sitting for extended periods of time Dedication to safety to mitigate industrial hazards that may include heat, cold, noise, fumes, strong magnets, lead (Pb), high voltage, and cryogenics Willingness to travel or work required nights/weekends/on‑call occasionally $150,000 - $225,000 a year Benefits Competitive compensation with equity 12.5 Company‑wide Holidays Flexible vacation days 10 sick days Generous parental leave policy Health, dental, and vision insurance 401(k) with employer matching Professional growth opportunities Team‑building activities #LI‑Onsite At CFS, we excel in fast‑paced environments, driven by our values of integrity, execution, impact, and self‑critique. As we grow, we're eager to bring on mission‑driven folks who offer diverse perspectives and fresh ways to tackle challenges. We value diversity deeply and are proud to be an equal opportunity employer by choice. We consider all qualified applicants equally, regardless of race, color, national origin, ancestry, citizenship status, protected veteran status, religion, physical or mental disability, marital status, sex, sexual orientation, gender identity or expression, age, or any other basis protected by law. This role requires compliance with U.S. laws concerning the export of controlled or protected technologies or information (collectively, “Export Control Laws #J-18808-Ljbffr

A tech innovation company in Mountain View, California, is seeking a Machine Learning Research Engineer. You'll design sophisticated robot learning algorithms to enhance dexterous manipulation in home environments. The role requires 3+ years in machine learning for robotics and proficiency with Python, particularly PyTorch. This is an opportunity to join a passionate team working at the forefront of robotics technology, ensuring personal robots are accessible for everyday households. #J-18808-Ljbffr

A technology firm specializing in integrated task systems seeks a Machine Learning Researcher / ML-Ops Engineer to advance computer vision and sensor fusion capabilities. The role involves implementing machine learning pipelines and optimizing models for deployment. Candidates should have a strong Python background and experience in deep learning frameworks like PyTorch and TensorFlow. This position in Palo Alto, California, offers competitive compensation and a collaborative work environment. #J-18808-Ljbffr

A cutting-edge robotics company in Palo Alto is seeking an engineer to develop advanced humanoid technologies. The role involves research, design, and prototyping critical components of robots. Candidates should have strong engineering principles and a background in Mechanical or Electrical Engineering. This position requires in-person collaboration to foster innovation. Competitive compensation and inclusive work culture are offered. #J-18808-Ljbffr

A leading scientific institution in Palo Alto is seeking an experienced machine learning research engineer to advance biological modeling capabilities. The ideal candidate will have a strong background in machine learning and deep learning, as well as excellent communication skills to work within a multidisciplinary team. The position offers a base salary range of $168,000-$242,500 and involves collaboration with biologists on innovative projects. #J-18808-Ljbffr

A leading tech company invites applications for a Machine Learning Engineer to advance AI research in California. The role focuses on Generative AI and requires a PhD or Master's degree, with a minimum of 3 publications in AI. The candidate will collaborate across teams and publish findings, contributing to networking solutions and AI innovations. This full-time position offers a competitive salary and benefits, fostering an inclusive workplace culture. #J-18808-Ljbffr

Meet The Team Cisco Webex is the world's #1 business collaboration and customer engagement platform. It is used across all industries in the world being used to support governments, business, education, and more, including use by 85% of Fortune 500 business. The workplace of the future will be powered by AI, and we, Collaboration AI, is the team responsible for building AI/ML intelligent experiences within Cisco's Webex portfolio. The team is made up of multiple major AI fronts to enrich the collaboration use cases. This, in the order of processing pipeline, includes audio codec technologies, automatic speech recognition (ASR), text-to-speech (TTS), natural language processing (NLP) using and training LLMs and beyond, and gen‑AI evaluation methodologies, both metric-based and subjective testing. In addition, videos are empowered via computer vision (CV) and additional contextual information by employee graphs, and much more. We aim to build the next-generation AI solutions in collaboration software, devices, and APIs - from digitizing the in‑meeting, enhancing distributed team efficiency and improving all aspects of people connection. Your Impact In this role, you will be responsible for conducting applied NLP research to advance our Language AI features. This includes, but not limited to, hierarchical summarization, internationalization, evaluation of generated texts, human alignment, and more fundamentally, a crucial set of techniques that can utilize the existing pre‑/mid‑/post‑trained LLM model checkpoints to the best extent, by, for instance, fine‑tuning, adaptation, model surgery/editing, and reinforcement learning to customize models for the business need, for cloud, on‑prem, and on‑device deployment. Your duties will include innovating and employing cutting‑edge technologies with the consideration of practical product launch, which concerns optimization of performance, scalability, safety, reliability, and measurable generation quality. Staying up to date with the latest advancements in AI and machine learning (ML) is expected, as is suggesting how new technologies might be implemented. Addressing and resolving any modeling issues that arise from product applications will be an integral part of your responsibilities: Advance Collaboration AI's Language AI capabilities by researching, prototyping, and implementing next‑generation LLM technologies Conduct rigorous applied NLP research following systematic methodology: establish benchmarks, evaluate baselines, perform ablation studies, and deliver actionable recommendations Develop and evaluate NLP models that address specific business requirements Balance technical trade‑offs (performance, latency, cost, quality) to determine optimal production solutions Collaborate with product managers and stakeholders to translate research into production features Write production‑ready code with appropriate testing, documentation, and deployment considerations Pursue publication opportunities at top‑tier NLP and ML conferences Minimum Qualifications Recent graduate or in your final year of studies toward a PhD, or Master's degree with 3+ years of post‑graduation work experience in related fields. Relevant fields include Computer Science, Data Science, Statistics, Mathematics, Engineering, or a related STEM program Strong foundation in machine learning and natural language processing, including familiarity with transformer architectures, common training schemes, and evaluation methodologies Proficiency in Python and experience with at least one deep learning framework Demonstrated NLP or ML research experience through publications, technical reports, thesis work, or significant contributions to related projects Preferred Qualifications At least one NLP or ML research paper published in a top‑tier conference, such as ACL, EMNLP, ICLR, ICML, NeurIPS, etc. Experience in using cloud services such as AWS, Google Cloud Platform, and Azure, for model training and deployment. Experience writing production‑quality Python code including testing, documentation, and code review practices Familiar with LLM benchmarking methods and experience analyzing benchmark datasets Experience collaborating with cross‑functional teams to deliver production ML solutions Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $181,000.00 - $270,300.00 Non‑Metro New York state & Washington state: $165,300.00 - $240,600.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status or any other legally protected basis. Cisco will consider for employment, on a case‑by‑case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr

A leading optical technology startup is seeking a Senior MEMS Design Engineer to design and optimize MEMS devices crucial for optical circuit switches. The role involves collaboration with multidisciplinary teams and the expertise in multi-physics modeling is essential for ensuring performance and reliability. Candidates should have a Master's or PhD in Applied Physics or related fields, with over 5 years of experience in MEMS design and a solid understanding of semiconductor processes. The position offers a salary ranging from $180,000 to $260,000 based on experience and skills. #J-18808-Ljbffr

Physical Design Engineer Job at Apple, Cupertino, CAJob Description Physical Design Engineer Department: Hardware Imagine what you can do here. Apple is a place where extraordinary people gather to do their best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Description Apple Inc. has the following available in Cupertino, California, and various unanticipated locations throughout the USA. Responsible for physical design and implementation of partitions. Build partition architecture and drive physical aspects early in the design cycle. Physically implement design partitions (from netlist to tape-out) for a highly complex System-on-Chip (SoC) utilizing state-of-the-art process technology. Work on partition-level place and route (P&R) implementation, including floor planning, clock and power distribution, timing closure, physical and electrical verification. Complete netlist to GDSII implementation for partitions meeting schedule and design goals. Oversee timing, physical, and electrical verification, and drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $151,091 - $214,500/year, depending on skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees have the opportunity to participate in Apple's stock programs, receive benefits including medical and dental coverage, retirement benefits, discounts, free services, educational reimbursement, and potential bonuses or relocation assistance. Learn more about Apple Benefits. Minimum Qualifications Master's degree or foreign equivalent in Electrical Engineering or related field. 2 years of relevant experience. 1 year of experience with each of the following: Encounter Design System tool, QRC, Calibre, Voltus, Primetime. Preferred Qualifications N/A Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity for all applicants regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Note: Apple benefits, compensation, and employee stock programs are subject to eligibility and other terms. This job posting appears to be active and does not indicate it is expired. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.Join us in our journey to becoming the world's #1 FPGA company!Altera is seeking a **Senior Design Automation Engineer** to join our Design Methodology Automation and Infrastructure Team.The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next-generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross-functional teams to deliver world-class automation solutions.**Key Responsibilities:*** Architect next-generation unified FPGA/SoC design methodologies spanning Front-End, handoff to Backend, Design Verification, Design-For-Test (DFT), Design Data Management/Release flows, and FPGA-specific flows such as Design Intent and Configuration Management.* Develop and integrate state-of-the-art EDA solutions, including ML/AI-enhanced tools, flows, and methodologies-sourced externally or developed internally-to create sustainable, scalable automation solutions for multiple chip design programs.* Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.* Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn-around time, and enhance design optimization.* Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.* Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.* Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.* Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross-functional initiatives to streamline FPGA design execution.* Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.* Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimizations.* Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next-generation capabilities.* Mentor and provide technical leadership to junior engineers within the Design Automation organization.#LI-MD1**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$142,600 - $206,500 USDWe use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 10 years of experience in IC Design or Design Automation and experience in the following:* Extensive experience with industry-standard EDA tools and hands-on expertise in design methodologies across multiple domains, such as Front-End Logic Design flows, Design Intent and FPGA-specific flows, Design Verification flows, and Design-for-Test (DFT) flows (with Back-End flow knowledge considered a plus).* Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.* Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimizations.* Proven leadership skills for driving collaborative, cross-functional projects, with strong communication and influencing abilities### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

An automotive giant is seeking a Staff ML Engineer for their ML Compute Platform to scale backend services and contribute to AI infrastructure. Responsibilities include designing software components, improving system efficiency, and leading initiatives. Candidates should have 7+ years of experience and expertise in languages like Go, C++, or Python, as well as a solid background in distributed systems. Join a team that's transforming mobility and tackling complex engineering challenges with AI applications. #J-18808-Ljbffr

Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams Chip/Block Level Floorplanning and pin assignment Review top-level/block-level clock specifications for completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing) Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification) Presentations and Customer Interaction in customer meetings Necessary Qualifications: BSEE, with 9+ years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes. Hands-on Experience with implementation EDA tools like ICC2/Innovus. Scripting (Perl/Tcl/Python) is required. Good understanding of ASIC frontend design. Experience in both Flat and Hierarchical layouts. Strong problem‑solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required. Experience with power analysis and IR‑drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime). Experience with Physical Verification and fix PV errors in layout. Expert handling of Verilog HDL based Netlists, Physical design libraries. Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings. Compensation: $190,000.00 - $200,000.00 per year MAKING THE INDUSTRY'S BEST MATCHES DBSI Services is widely recognized as one of the industry's fastest growing staffing agencies. Thanks to our longstanding experience in various industries, we have the capacity to build meaningful, long‑lasting relationships with all our clients. Our success is a result of our commitment to the best people, the best solutions and the best results. Our Story: Founded in 1995 Privately Owned Corporation Managing Partner Business Model Headquartered in New Jersey US Based Engineers Only Methodology and Process Driven Top performing engineers are the foundation of our business. Our priority is building strong relationships with each employment candidate we work with. You can trust our professional recruiters to invest the time required to fully understand your skills, explore your professional goals and help you find the right career opportunities. #J-18808-Ljbffr

About Treering Treering, a Silicon Valley-based tech company, helps people preserve and celebrate their memories. By combining just-in-time digital printing with the power of AI tools, Treering delivers personalized keepsakes that celebrate important milestones and events. About the Role We are seeking a highly skilled AI Engineer to lead the maintenance and enhancement of our existing AI solutions. This role will be crucial in ensuring the smooth operation and continuous improvement of our AI-driven product generation process. You will be working with a suite of APIs designed to analyze, score, and rank photos, making critical decisions to automatically generate photobooks, yearbooks, and other print-on-demand products. Responsibilities AI Systems Maintenance: Maintain and optimize existing AI solutions, including APIs for photo analysis, scoring, and ranking. Enhancement and Development: Develop and enhance AI models and algorithms to improve the accuracy and efficiency of automated product generation. API Management: Oversee and manage the suite of APIs used in our AI solutions. Cloud Infrastructure: Utilize and manage AWS services such as Rekognition, Lambda, SageMaker, Step Functions, SQS, OpenSearch, S3, and RDS. State Machine Management: Design, implement, and manage state machines for orchestrating AI processes. Programming: Write and maintain Python code for AI models and API development. Monitoring and Troubleshooting: Monitor AI system performance, troubleshoot issues, and implement solutions. Collaboration: Work closely with cross-functional teams to integrate AI solutions into the overall product workflow. What We're Looking For Bachelor's or higher degree in Computer Science, Data Science, Artificial Intelligence, or a related field. 6+ years of experience in AI development and deployment. Strong proficiency in Python programming. Extensive experience with AWS services, including Rekognition, Lambda, SageMaker, Step Functions, State Machines, SQS, OpenSearch, S3, and RDS. Experience with API development and management. Solid understanding of machine learning algorithms and techniques. Excellent problem-solving and analytical skills. Strong communication and collaboration skills. Strong leadership and mentoring abilities. Why Join Treering? Impact: Your work directly contributes to modernizing the yearbook industry. Innovation: Work with cutting-edge technologies in an agile environment. Growth: Opportunities for career advancement and professional development. Culture: A collaborative, inclusive, and supportive team environment. Benefits Comprehensive medical, dental, vision, life/AD&D, and disability coverage Pre-tax savings/spending plans, including HSA employer contributions Parental Leave Benefits Pre-tax and Roth 401(k) plan with an employer contribution Flexible vacation for salaried Twelve paid holidays throughout the year $180,000 - $200,000 a year If you are an experienced software engineer who thrives in a dynamic environment and is passionate about designing and implementing innovative web solutions, we invite you to apply. #J-18808-Ljbffr