Senior verification engineer jobs in Austin, TX - 309 jobs

Top must haves: - Zephyr OS working knowledge - Bare metal bring up with Zephyr - MCTP/PLDM knowledge - BMC or equivalent working knowledge open - BMC experience is plus KEY RESPONSIBILITIES: • Contribute to firmware for supporting next generation interconnect technologies both for client proprietary and industry standards like PCIe, CXL, MCTP, UBM, and USB4. • Engage as a teammate and work closely with multi-functional teams such as BMC, power management, architecture, design and verification on delivery of integrated firmware solutions. • Develop low level firmware for embedded systems in an RTOS environment. • Engage in pre-silicon validation activities such as co-simulation with IP and SOC emulation • Support post- silicon enablement and production cycle efforts • Develop and support full design cycle of embedded firmware solutions including pre-si, post-si and production REQUIREMENTS: • Specialist in C, strong in C++ or Python • Highly Proficient in developing firmware based on industry standard initiatives PLDM, MCTP, SPDM. • Knowledge of low-level protocols including I2c, I3c, PCIe, JTAG, SPI, eSPI, UART expected • Hands on experience with end-to-end Firmware from pre to post-silicon and production cycle. • 5+ years device driver or embedded firmware development experience • Experience with Zephyr RTOS • Demonstrated proficiencies with firmware lab debug, triaging and implementation of bug fixes for silicon bring-up, through production. • Comfortable in Linux build environment PREFERRED QUALIFICATIONS: • Previous BMC Firmware development experience mandatory (Dell iDRAC, Dell CMC, HP iLo, etc) • Understanding of Security concepts - Root of Trust, verified boot, measured boot • Experience with Open Source Baseboard Management Controller (BMC) Software Stack (OpenBMC) • Proficient with Source version control systems like Git, Review tools like Gerrit • Experience in Arm architecture • Experience reading and understanding digital schematics • Strong analytical skills and debug methodology expected. ACADEMIC CREDENTIALS: • BSEE, BSCS, or BSCE degree or higher • 5+ years or more of firmware development • 3+ years or more of manageability firmware experience • Candidates should enjoy working in a dynamic team environment

KEY RESPONSIBILITIES: The position entails firmware development in conjunction with coordination with architects, BIOS developers, vendors, and quality assurance teams to develop robust, innovative OpenBMC firmware releases for customer reference boards. Responsibilities include BMC firmware development in an OpenBMC environment, upstreaming work to the OpenBMC community and troubleshooting existing designs. A successful candidate will employ solid software methodologies, manageability design expertise, debug capabilities, and strong process practices to ensure on-schedule, defect-free firmware deliveries with focus on continuous feature and code improvement. PREFERRED EXPERIENCE: • Previous BMC Firmware development experience mandatory (Dell iDRAC, Dell CMC, HP iLo, etc) • Highly Proficient in developing User Interface based on Java Scripts, Network socket concepts • Experience with Open Source Baseboard Management Controller (BMC) Software Stack (OpenBMC) • Programming experience (JavaScript , Shell Scripting, Python, C, C++) • Knowledge of low-level protocols including I2c, I3c, JTAG, SPI, eSPI, UART, PCIe expected • Proficient with Source version control systems like Git, Review tools like Gerrit • Working knowledge of Linux Kernel programming and Linux driver development experience (JTAG, I2C, SPI) • Hands on experience working with Reference Boards. • Experience with Linux gcc build and debug tools. • Strong debug methodology and skills mandatory • Experience in server manageability architecture mandatory • Intimate knowledge of software development process methodology expected • Knowledge of industry standard initiatives such as Redfish, PLDM, MCTP desirable and manageability protocols such as IPMI expected DESIRED: • Experience in x86 architecture • Understanding of Security concepts - Root of Trust, verified boot, measured boot • Experience in Arm architecture • Experience reading and understanding digital schematics • Strong analytical skills and debug methodology expected. ACADEMIC CREDENTIALS: • BSEE, BSCS, or BSCE degree or higher • 5+ years or more of firmware development • 3 years or more of manageability firmware experience • Candidates should enjoy working in a dynamic team environment

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, GPU. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. The DFT Design Verification Engineer will be on a team which is responsible for the complete DFT pre-silicon verification and support for silicon bring-up of GPU core. In this highly transparent and interactive role, your primary responsibilities will include: • Reviewing Architecture and Design Specifications • Extracting design features and developing attributes and verification plans • Working with designers to verify DFT implementation and run various checks • Implementing test benches, generating advised/constrained random tests • Debugging failures, running gate level simulations, supervising bugs, and closing coverage • Handling schedules and supporting multi-functional engineering effort • Assisting in verification flows, automation scripts and regressions • Working with test engineers to bring up test patterns on silicon. Proven experience in large processors and/or GPU/SOC designs Hands-on experience in directed or random verification, coverage analysis and assertions Proficient in scripting languages such as Perl, Python or TCL Strong Object-Oriented Programming skills Solid Understanding of Design Verification (DV) methodologies for verifying DFT implementation in pre-silicon Excellent skills in problem solving, communication and desire to seek new challenges Experience working under strict schedule deadlines with the ability to manage multiple priorities Good knowledge of general logic design, and exposure to DFT is a plus Bachelors Degree + 0 Years of Experience

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Design Verification Engineer - Graphics IP THE ROLE: The focus of this role is to plan, create, and maintain the functional verification model used to verify new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design. THE PERSON: An analytical thinker with problem-solving skills and excellent attention to detail Possesses excellent comprehension, communication, and interpersonal skills Enjoys working in a fast-paced, multi-project team environment using state of the art tools and technology KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features being implemented Plan and implement the required changes to the fuctional model so that the model accurately represents the new and modified hardware Work with the architecture modeling team to incorporate the updated functional model in the performance model Participate in debugging failing verification tests to determine if the root cause is an error in the RTL, verification model, or the test. Fix all identified failures in the verification model. PREFERRED EXPERIENCE: Strong C/C++ programming and debug in a Linux environment Knowledge of ASIC design and functional modeling Graphics pipeline knowledge a plus Proficiency in debugging RTL code using simulation tools a plus Proficient in using UVM testbenchs a plus Experienced with Verilog, System Verilog a plus ACADEMIC CREDENTIALS: BS/MS degree in Electrical Engineering, Computer Engineering, or Computer Science LOCATION: This position is located in Austin, TX #LI-PH1 Requisition Number: 183227 Country: United States State: Texas City: Austin Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence. The NVIDIA System-On-Chip (SOC) group is looking for an entry level ASIC Verification Engineer! In this position you will have the chance to create a high-level and broad impact at NVIDIA working on a system-level IP responsible for measuring performance on multiple projects. Your focus will be on verifying and improving the related verification methodologies for the corresponding design (RTL). For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC). What you'll be doing: Design and maintain the unit level/sub-system Verification environment. Understand the architecture specifications, develop and carry out the test plan to verify the design. Create the UVM components, sequences, tests and scoreboards. Sign off on the verification efforts with very high quality code and functional coverage. Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets Automate the manual steps involved in launching build, regression, and triages. Collaborate with architects, designers, and software engineers to achieve the project goals. Pro-actively contribute to improving the efficiency of the testbenches by embracing the latest techniques. What we need to see: Completing an MS or higher in Computer or Electrical Engineering (or equivalent experience). Experience in System Verilog, UVM and in general OOPS based programming. Strong coding skills in Python or other industry-standard scripting languages. Strong understanding of RTL design (Verilog). Good understanding of computer architecture fundamentals. Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi. With industry-leading salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. The most forward-thinking engineers in the world do their life's work at NVIDIA. If you're creative and autonomous, with a real passion for technology, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 13, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Job Details:Job Description: Altera is one of the world's leading providers of programmable solutions. With a renewed focus on agility, software-first, and AI-driven solutions, Altera is shaping the future of computing by providing flexible technology, empowering innovators with scalable products, from high-performance to power- and cost-optimized devices for cloud, network, and edge applications. Join us in our journey to becoming the #1 FPGA provider in the world as we redefine the next era of programmable innovations! About the Team & About the Role The HPS Design Verification Team is responsible for validating the processor subsystem of Altera FPGA products. As a SoC Design Verification Engineer you will have the opportunity to; Perform functional logic verification of an integrated SoC to ensure design will meet specifications. Define and develop scalable and re-usable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Execute verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicate, root causes, and debugs issues in the pre-silicon environment. Find and implement corrective measures to resolve failing tests. Collaborate and communicate with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Document test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporate and execute security activities within test plans, including regression and debug tests, to ensure security coverage. Maintain and improve existing functional verification infrastructure and methodology. Absorb learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages, and proliferates to future products. Salary Range Our compensation reflects the cost of labor within the US market. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance. $128.9k - $205.9k USD Qualifications: What We Want to See 7+ years of work experience in logical hardware design and verification. Must be fully knowledgeable of programming in SystemVerilog and UVM hardware descriptive languages. Must possess a background of unit or block ownership in a full hardware design life cycle. Bachelor's degree in electrical engineering, computer engineering, computer science or similarly related fields. Ways to Stand Out from the Crowd 10+ years of work experience in logical hardware design and verification. A strong background in Design for Debug verification is strongly needed. Specifically, experience with ARM Coresight debugger verification will be valuable. Objected oriented programming in languages like C++, Java. Scripting in languages like Python, Perl and Tcl is desired. A background in using AI techniques in design and verification is very much desired. Job Type: RegularShift:Shift 1 (United States of America) Primary Location:Austin, Texas, United StatesAdditional Locations:San Jose, California, United StatesPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our custom dataflow architecture that is the backbone of our chip design. DV engineers collaborate with many teams, including RTL design, architecture modeling, custom analog IP, compiler, emulation and post-silicon to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Further responsibilities will depend on background and skills. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 3+ years of industry experience developing verification testbenches. Knowledge of verification methodologies. Knowledge of computer architecture. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a agile team working with the best in the industry, focused on developing ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer, Design Verification Responsibilities: 1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop functional tests based on verification test plan 3. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage 4. Debug, root-cause and resolve functional failures in the design, partnering with the Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality 6. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry **Minimum Qualifications:** Minimum Qualifications: 7. Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8. 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies 10. Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments **Preferred Qualifications:** Preferred Qualifications: 11. Experience with revision control systems like Mercurial(Hg), Git or SVN 12. Experience with verification of ARM/RISC-V based sub-systems or SoCs 13. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation 14. Experience in development of UVM based verification environments from scratch 15. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle 16. Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, Ethernet, DDR, HBM 17. Experience with micro-architectural performance verification 18. Experience verifying GPU/CPU designs 19. Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs 20. Experience working across and building relationships with cross-functional design, model and emulation teams 21. Track record of 'first-pass success' in ASIC development cycles **Public Compensation:** $146,000/year to $209,000/year + bonus + equity + benefits **Industry:** Internet **Equal Opportunity:** Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment. Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Responsibilities and Description: The Physical Design and Verification Engineer will be responsible for RTL to GDSII Physical Design Implementation, including Synthesis, Placement, Clock Tree Synthesis, Detailed Routing and Optimization, in addition to Physical Signoff Verification. Required Qualifications: Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Minimum 5 years of experience in digital physical design and verification. Excellence in complete RTL to GDSII flow with strong experience in the usage of industry-standard Electronic Design Automation (EDA) tools for both physical design and timing signoff. Deep knowledge on industry standards and practices in physical design including physically-aware synthesis flow, floor-planning, and place & route, metal fill, chip finishing, signal integrity checks, and dynamic EMIR-Drop analysis, and formal ESD verification. Experience in Signoff ECO flow to fix timing, noise, IR-Drop and EMIR violations. Experience in physical design verification to debug LVS/DRC/PERC issues at the chip/block level using industry standard tools. Experience in developing automation flow and scripts using Python, Perl, Makefile, Tcl and UNIX shell. Preferred Qualifications: Master of Science (M.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience. Experience working on physical design and implementation of complex ASIC systems at advanced technology nodes, preferably 16nm and below. Experience in DFT (Design For Test) flows and ATPG. Experience in I/O design flow in multi-voltage power domain. Experience in building chip floor-plan including pin placement, partitions and power grid. Experience in hierarchical synthesis, place-and-route and design closure to meet timing, area, and UPF-driven low power constraints. Experience with build tools such as CMake and Bazel. Experience with code coverage and regression setup. Expected Compensation: The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees' success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees. Base Salary Range: $158,000 - $243,000 USD What We Offer: Full-time employees are eligible for the following benefits listed below. An opportunity to change the world and work with some of the smartest and most talented experts from different fields Growth potential; we rapidly advance team members who have an outsized impact Excellent medical, dental, and vision insurance through a PPO plan Paid holidays Commuter benefits Meals provided Equity (RSUs) *Temporary Employees & Interns excluded 401(k) plan *Interns initially excluded until they work 1,000 hours Parental leave *Temporary Employees & Interns excluded Flexible time off *Temporary Employees & Interns excluded

Sr Design Verification Engineer (Remote) Full-time: Salary + Benefits + Bonuses / Contractor Work Status: US citizen or Lawful Permanent Resident. About the Role: The ASIC Verification Engineer will play a crucial role in executing a comprehensive test strategy for future ASIC development. You will be part of a team creating automated regression suites, executing verification methodologies. As our ASIC Design Verification Engineer, you will: Test Strategy & Development Collaborate with design and other verification engineers to develop and execute test strategies. Write testbenches and test cases based on test plans. Develop and improve UVM frameworks. Contribute to unit-level and system-level verification deliverables. Become a key contributor to our ASIC verification framework, methodology, and test automation. Implement DSP verification environments to facilitate testing of the RTL against reference MATLAB and Python models Testing & Automation: Run and automate regression tests. Analyze code and functional coverage and provide actionable feedback to the development and verification team. Prepare and present detailed reports on testing outcomes and verification strategies. Qualities of a Successful Candidate: BS or MS in Electrical/Computer Engineering or equivalent. 10+ years of experience in ASIC verification. Proficiency in SystemVerilog and UVM for verification. Knowledge of verification for DSP algorithms and Mixed Signal systems. Nice to Have: Familiarity with Cadence Xcelium simulators or similar tools. Knowledge of scripting languages such as Python or TCL. Experience working on Linux-based systems. The anticipated annual base salary for this position is between $135,000 to $165,000, which also includes a comprehensive benefits package. Full-Time Benefits: • 15 days of PTO per calendar year • 10 paid Holidays per calendar year • Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents • Dental & Vision: Company covers 50% of premiums for Employee and Dependents • Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance • Employee Assistant Program (EAP) • 401k - Traditional & Roth • Life/AD&D and Long-Term Disability • Tuition reimbursement Equal Opportunity Policy Statement Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances. Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status. LinkedIn:: ************************************

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators. These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb. FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary. Responsibilities Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment Writing detailed verification plans Quickly root-cause RTL bugs Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs Managing test suites and continuous integration infrastructure Developing and improving open-source and internal tools Qualifications Superb debug and analytical skills Professional experience (2+ years) in RTL functional verification for FPGA or ASIC Experience with code and functional coverage collection/analysis Experience with SystemVerilog and industry-standard frameworks such as UVM Experience with Python Comfortable in a Linux environment Familiarity with Verilator and/or Cocotb preferred C++ experience is a plus A bachelor's degree in computer science, electrical engineering, or a related field The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package. Culture Hudson River Trading (HRT) brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading. At HRT we welcome a variety of expertise: mathematics and computer science, physics and engineering, media and tech. We're a community of self-starters who are motivated by the excitement of being at the cutting edge of automation in every part of our organization-from trading, to business operations, to recruiting and beyond. We value openness and transparency, and celebrate great ideas from HRT veterans and new hires alike. At HRT we're friends and colleagues - whether we are sharing a meal, playing the latest board game, or writing elegant code. We embrace a culture of togetherness that extends far beyond the walls of our office. Feel like you belong at HRT? Our goal is to find the best people and bring them together to do great work in a place where everyone is valued. HRT is proud of our diverse staff; we have offices all over the globe and benefit from our varied and unique perspectives. HRT is an equal opportunity employer; so whoever you are we'd love to get to know you. Please be advised: Use of AI tools during interviews or assessments is strictly prohibited, unless otherwise instructed or agreed upon. We employ various methods to evaluate the authenticity of candidate responses. If we determine that AI assistance was used during any stage of the hiring process, we reserve the right to immediately disqualify your candidacy or rescind any job offers extended.

Condor Computing is a brand-new member of the RISC-V revolution. Condor is aiming to fly high by building the industry's highest performance licensable RISC-V core. Our team of highly experienced CPU designers will create a new benchmark for power efficiency in high performance open-source computing. We are pleased to announce that Condor is seeking a skilled and personable Sr. DV Engineer to become a valuable member of our team. In this position, you will have the opportunity to investigate innovative strategies to enhance the performance of our high-performance RISC-V processors, with a focus on all functions within the CPU core and memory systems. You will work collaboratively with a talented team, including engineers from RTL design, verification, and software groups, to propose enhancements, optimizations, and features based on performance assessments and PPA impact. Here is what you will do: Architect and implement testbenches utilizing UVM-based methodologies Design and develop Verification Components using UVM-based techniques Conduct block-level verification to ensure optimal block performance and compliance with requirements Generate and execute verification plans based on specifications Define, implement, and analyze coverage metrics Architect and implement Formal Verification processes Create automation tools to streamline testing Perform testing for design performance evaluation Here is the background we hope you have: A Master's or Bachelor's degree in Electronic/Electrical Engineering or Computer Science 8+ years of experience in Verification Proven industry experience in developing testbenches and verification components with SystemVerilog and UVM from inception In-depth knowledge of event-driven simulator-based modeling techniques Experience with low-power implementation (UPF) Familiarity with scripting languages such as Python, Ruby, or Perl A comprehensive understanding of chip and/or computer architecture These would be nice to have but are not required: Strong written and verbal communication abilities Exceptional collaboration skills across sites and functions Condor Computing is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application!

Description Ventana is building the highest-performance RISC-V CPUs on the planet-designed for data center, AI, and edge workloads, with real silicon, not slideware.Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64-bit ARM server processor (X-Gene at AppliedMicro)-bringing decades of CPU innovation to a clean-slate, open-standards future. You can check us out here: Ventana Micro - YouTubeWe are looking to fill multiple Design Verification openings to continue the development of its innovative RISC-V processors and subsystems.Role: Develop and execute verification plans for units and features. Construct testbenches, scoreboards, and stimulus generators. Implement functional coverage models. Debug designs in simulation, prototyping platforms, and silicon. Qualifications Required: Roles requiring both 4+ and 8+ years industry experience Bachelor's or Master's degree in related engineering field Ability to work independently and across geographies Strong domain knowledge of computer architecture Skills and Qualifications Desired: SystemVerilog verification development experience Testbench construction using UVM or analogous methodologies Scoreboards and stimulus generators for complex units Industry experience with CPU microarchitecture (e.g. x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems Software development experience in compiled (C/C++) and interpreted (Python) languages Unit or feature ownership throughout the project lifecycle Post-silicon validation EEOE Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law.COVID-19 Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/ business partners. NOTICE: External Recruiters/ Staffing Agencies: Ventana Micro instructs agencies not to engage with its employees to present candidates. Employees are not authorized to enter into any agreement regarding the placement of candidates. All unsolicited resumes received as gratuitous submissions. We reserve the right to directly contact any candidate speculatively submitted by a third party. Such contact will not constitute acceptance of any contractual arrangement between Ventana and the agency, and Ventana will not be liable for any fees should it choose to engage the candidate's services. All external recruiters and staffing agencies are required to have a valid contract executed by Ventana's CFO.Please Note: Fraudulent job postings/job scams are increasingly common. Our open positions can be found through the careers page on our website.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This is a technical position. Be part of the world's leading Design Verification Methodology team developing applications for functional and behavior verification of state-of-the-art graphics accelerators, generative AI (Artificial Intelligence) accelerators, servers, and Systems on Chips (SoCs). In this role, you will be analyzing methodology flows and data, identify the pain points in various design, pre and post Silicon verification efforts, and adapt this methodology to address these pain points. Also, as the designs and their methodologies mature, you will be ensuring methodologies evolve to match up scalability. You will coordinate with Hardware Architects, Logic Designers, experts, and technical leaders from various validation teams, to tackle functional issues present in the proposed methodology and tool. THE PERSON: * Will demonstrate strong analytical thinking and problem-solving skills with excellent attention to detail. * Will have effective communication and writing skills, * Will have good teamwork and interpersonal skills, . KEY RESPONSIBILITIES: * Deploying Industry-Leading Verification Methodologies such as UVM and Formal Verification. * Driving technical innovation to improve AMD's capabilities in IP validation/verification, including tool and script development, technical and procedural methodology improvement, and various internal and cross-functional technical initiatives. * Developing Testbenches and Verification Components such as UVCs, models, BFMs, and Re-usable Verification Environments. * Working closely with supporting teams in design, diagnostics, emulation, firmware, and driver to adopt and deploy new verification methodologies and tools. PREFERRED EXPERIENCE: * DV planning for Metric Driven Verification and TB architecture. * Deep knowledge of DV infrastructure, Make flow and other automation flows, shell, Perl, python, ruby. * Machine Learning is a plus. * Prior experience with System Verilog HVL and UVM methodology is a plus * Familiarity with emulation and post-Si validation is a plus. ACADEMIC CREDENTIALS: * Bachelor, Master or PhD in Electrical Engineering, Computer Engineering or Computer Science. LOCATIONS: * Austin, TX #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence. The NVIDIA System-On-Chip (SOC) group is looking for an entry level ASIC Verification Engineer! In this position you will have the chance to create a high-level and broad impact at NVIDIA working on a system-level IP responsible for measuring performance on multiple projects. Your focus will be on verifying and improving the related verification methodologies for the corresponding design (RTL). For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC). What you'll be doing: * Design and maintain the unit level/sub-system Verification environment. * Understand the architecture specifications, develop and carry out the test plan to verify the design. * Create the UVM components, sequences, tests and scoreboards. * Sign off on the verification efforts with very high quality code and functional coverage. * Launch regressions, resolve the issues, and make forward progress towards achieving the DV milestone targets * Automate the manual steps involved in launching build, regression, and triages. * Collaborate with architects, designers, and software engineers to achieve the project goals. * Pro-actively contribute to improving the efficiency of the testbenches by embracing the latest techniques. What we need to see: * Completing an MS or higher in Computer or Electrical Engineering (or equivalent experience). * Experience in System Verilog, UVM and in general OOPS based programming. * Strong coding skills in Python or other industry-standard scripting languages. * Strong understanding of RTL design (Verilog). * Good understanding of computer architecture fundamentals. * Familiarity with verification tools such as VCS or equivalent simulation tools, and debug tools like Verdi. With industry-leading salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. The most forward-thinking engineers in the world do their life's work at NVIDIA. If you're creative and autonomous, with a real passion for technology, we want to hear from you. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 13, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Job DescriptionWe're hiring experienced Design Verification Engineers to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us:Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications - whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from -40 °ree;C to +125 °ree;C, making it ideal for industrial, automotive, aerospace, and defense. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets. The salary range for this position is $120,000-$225,000+ annually. Actual compensation depends on experience, skills, qualifications, and location. Design Verification at Mythic:At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. DV engineers collaborate closely with RTL design, architecture modeling, custom analog IP, compiler, emulation, and post-silicon teams to ensure the full system operates as intended. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We welcome engineers at all levels of experience who are eager to tackle challenging verification problems and contribute to the success of our breakthrough AI hardware.Responsibilities Hands-on system-level and block-level verification. Development of test plans and coverage plans. Testbench development and execution using UVM or other advanced DV methodologies. Creation of verification infrastructure and flows. Leverage architecture models and emulation environments to help verify large AI network functionality on the design. Collaborate with RTL designers and architects to verify subsystems such as scheduling fabrics, interconnects, DMA engines, and memory controllers. Requirements Bachelor's, Master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or Computer Science. 8+ years of industry experience developing verification testbenches. Knowledge of verification methodologies (UVM or similar). Solid understanding of computer architecture, including datapaths, memory hierarchies, and interconnects. Experience verifying one or more of the following: scheduling subsystems, high-performance interconnects, DMA engines, or memory subsystems. Understanding of Verilog, SystemVerilog, and UVM. Proven track record of first-pass silicon success. Strong communication skills, both written and spoken. Preferred Qualifications Experience with emulation or FPGA prototyping for large-scale designs. Knowledge of coverage-driven verification and advanced stimulus generation techniques. Exposure to formal verification methods and tools. Familiarity with power-aware and performance-driven verification flows. Prior experience verifying AI, DSP, or other highly parallel architectures. Strong scripting skills (Python or similar) for automation and infrastructure development. At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.

Reality Labs focuses on delivering Meta's vision through AI-first devices that leverage our wearable technologies. The compute performance and power efficiency requirements require custom silicon. We are driving the state-of-the-art forward with highly integrated SoCs that leverage breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable Meta's Wearable devices that blend our real and virtual worlds throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. Minimum Qualifications * Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta * 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification * 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies * Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments Preferred Qualifications * Experience with revision control systems like Mercurial(Hg), Git or SVN * Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle * Experience in development of Universal Verification Methodology (UVM) based verification environments from scratch * Experience verifying ARM/RISC-V based sub-systems and SoCs * Experience verifying CPU/GPU designs * Experience in one or more of the following areas: SystemVerilog Assertions (SVA), Formal, and Emulation * Track record of 'first-pass success' in Application-Specific Integrated Circuit (ASIC) development cycle Responsibilities * Define and implement verification plans, and build test benches for block, IP, sub-system, and SoC level verification * Develop functional tests based on verification test plan * Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage * Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality * Debug, root-cause and resolve functional failures in the design, partnering with the Design team About Meta Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics. Equal Employment Opportunity Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics. You may view our Equal Employment Opportunity notice here. Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.

Condor Computing is a brand-new member of the RISC-V revolution. Condor is aiming to fly high by building the industry's highest performance licensable RISC-V core. Our team of highly experienced CPU designers will create a new benchmark for power efficiency in high performance open-source computing. Formal Verification Engineer As a Formal Verification Engineer at Condor, you will be responsible for ensuring the correctness and reliability of our world-class processor designs. Your role will involve crafting innovative solutions to verify complex design micro-architectures using cutting-edge technologies. Additionally, you will collaborate closely with design teams to enhance micro-architecture and contribute to the development of reusable and optimized verification models. As a formal verification engineer with Condor, you will Work on verification of Condor's world-class processor designs Craft novel, creative, and best-in-class solutions for verifying complex design micro-architectures with the best technologies available Develop a comprehensive formal verification test plan Develop functional properties for the design, find design bugs, and work closely with design teams to help improve the micro-architecture Develop re-usable and optimized verification models and a verification code base Architect correct-by-construction design methodologies to enhance formal verification efficiency and productivity Here are the minimum requirements: Master' Bachelor, or above degree in electronic/electrical engineering or computer science 4+ years of verification experience, with at least 2 years utilizing formal verification methods Solid understanding of RTL designs and computer architecture Proficiency in scripting languages such as Python, Ruby, or Perl Demonstrated track record of implementing new ideas that positively impact the company These would be nice to have but are not required: Industry experience developing test benches and verification components from scratch using SystemVerilog and UVM Deep understanding of event-driven simulator-based modeling techniques Familiarity with low-power implementation (UPF) Strong written and verbal communication skills Effective cross-site and cross-functional execution skill Condor Computing is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application!

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a Silicon Design Verification Engineer, you will work with graphics designers to verify AMD graphics logics and drive convergence. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Write tests, sequences, and testbench components in SystemVerilog and UVM along with formal to achieve verification of the design * Responsible for verification quality metrics like pass rates, code coverage and functional coverage * Drive formal verification for the block and write formal properties and assertions to verify the design * Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design PREFERRED EXPERIENCE: * Hands on experience with UVM, test-bench, coverage etc * Project level experience with design concepts and verifications * Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics * Good understanding of computer architecture ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering This role is not eligible for visa sponsorship. #LI-HYBRID #LI-SL2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.