Senior verification engineer jobs in Petaluma, CA

Senior / Staff Frontend Engineer | Product-Focused | Series A Startup We're working with a Series A, AI-driven software company building a product that fundamentally changes how federal contractors create and submit proposals. This team is tackling complex, high-stakes workflows and turning weeks of compliance-heavy work into days through thoughtful product design and modern AI. This role is ideal for a Senior or Staff-level Frontend Engineer who cares deeply about user experience, enjoys owning large parts of the product, and wants to help shape both the technical foundation and product direction at an early-stage company. What you'll do • Build and ship core, customer-facing product features used by external users • Own frontend architecture and help define best practices as the product scales • Partner closely with product, design, and backend engineering to deliver polished, intuitive experiences • Translate complex workflows into clean, usable interfaces • Contribute to enterprise-grade software with high standards for performance and reliability • Play a key role in an early-stage company, influencing both product direction and engineering culture What we're looking for • 5+ years of product-focused frontend engineering experience • Proven experience building consumer or business-facing products (not just internal tools) • Background working at a Series A or early-stage startup, or a strong desire to work in that environment • Track record of shipping high-quality software in fast-moving, ambiguous settings • Senior-level ownership mindset, with Staff-level scope or ambition welcomed Technical skills • Strong proficiency in React, JavaScript, and TypeScript • Deep understanding of modern web technologies and frontend architecture • Strong UI/UX instincts and product design sensibility • Experience building complex, data-rich interfaces • Exposure to AI-powered features or large language models is a plus Traits that matter • Product-minded and deeply user-centric • Comfortable taking ownership and making decisions • Excited to build from the ground up at an early-stage startup • Clear communicator who collaborates well across disciplines If you're excited about building meaningful, user-facing products at a Series A company where your work has visible impact, this is worth a conversation.

ABOUT THE ROLE We're seeking a Senior Desktop Systems Engineer to manage Azure and Intune environments. In this role, you'll oversee analysis, design, implementation, and maintenance of OS deployment, updates, security, and group policy enforcement. You'll manage Active Directory, Group Policy, BitLocker, BIOS, and OS security policies. You'll handle level 3 support tickets, resolves vulnerabilities using scripting and PowerShell, and ensures high client services and satisfaction are attained across all responsibilities and areas of position. Establish, engineer, and implement procedures and processes to improve efficiency and the quality of the user experience with applications and systems. Install, maintain, and administer Azure, Intune, Active Directory, GPO, OSD, Bitlocker, Office365 and ensure services and needs are met. Utilize in-depth application knowledge to identify, anticipate, manage, and resolve complex problems relating to Active Directory, Azure, Intune, operating system management and security dev ops and related technology in use at the firm. Engineer and implement operating system deployment, software and patch distribution management such as RIS/WDS, WPE, MECM/SCCM/OSD, Intune, WSUS. Evaluate and recommend workstation hardware, such as desktop, laptop, tablet computers, peripherals and accessories. Ensure all operating systems have the latest security updates, service pack level including device driver maintenance through the use of patch management and/or software distribution as well as operating system builds with WDS, OSD, and WPE. Create, deploy and maintain automated installations and repetitive tasks associated with workstation and server administration using scripting languages such Powershell, Windows Host Script. Lead in application installation package creation with Task Sequencing, Powershell and Windows MSI. Possess in-depth knowledge of Microsoft Azure Intune and Powershell to meet the firm needs to resolve and trouble shoot problems in areas of expertise. Provide technical support to other IT analysts, assisting them with the operating system deployment, cloud and application software installation. Log technical support incidents and requests into the ticket management system from live calls, email, and voice mail systems. Monitor support center incidents assigned to the team to ensure SLAs and OLAs are met for responding to and resolving incidents. Provide succinct and pertinent updates to incidents indicating acted upon resolution and communication to user. Participate in Problems and Knowledge initiatives and other process improvements. Prepare and update technical documentation; ensure non-technical decision makers understand technical matters. Reachable outside of standard working hours as needed. ABOUT YOU Bachelor's Degree in related field or educational and work equivalent. 10+ years' experience leading department goals and administrating and managing Microsoft Azure, Intune and other Microsoft Cloud technologies. A minimum of 5 years of experience in creating and supporting Operating System images for workstation and server hardware and virtual machines in an enterprise environment. Experience in a law firm environment a plus, experience maintaining the core infrastructure of the workstation and server imaging, software, and patch distribution management such as RIS/WDS, WPE, MECM/OSD, WSUS. Strong knowledge of scripting language and automation of repetitive tasks through scripting language in Powershell, also nice to have Windows Host Script. Strong knowledge of application installation package creation using Task Sequencing, Powershell and/or Windows MSI. Ability to perform quality assurance and testing for both client/server and web applications. Ability to partner with both software development and software integration specialists and Firm business process owners. Solid understanding of the application lifecycle process, including requirement analysis, quality assurance, design, scheduling, implementation, issue tracking, version control and deployment.

We are actively searching for a Distributed Systems Engineer to join our team on a permanent basis. In this founding engineer role you will focus on building next-generation data infrastructure for our AI platform. If you have a passion for distributed systems, unified storage, orchestration, and retrieval for AI workloads we would love to speak with you. Our office is located in downtown SF and we collaborate two days a week onsite. Your Rhythm: Design, build, and maintain data infrastructure systems such as distributed compute, data orchestration, distributed storage, streaming infrastructure, machine learning infrastructure while ensuring scalability, reliability, and security Ensure our data platform can scale by orders of magnitude while remaining reliable and efficient Tackle complex challenges in distributed systems, databases, and AI infrastructure Collaborate with technical leadership to define and refine the product roadmap Write high-quality, well-tested, and maintainable code Contribute to the open-source community and engage with developers in the space Your Vibe: 3+ years of professional distributed database systems experience Expertise in building and operating scalable, reliable and secure database infrastructure systems Strong knowledge around distributed compute, data orchestration, distributed storage, streaming infrastructure Strong knowledge of SQL and NoSQL databases, such as MySQL, Postgres, and MongoDB. Programming skills in Python Passion for building developer tools and scalable infrastructure Available to collaborate onsite 2 days a week Our Vibe: Relaxed work environment 100% paid top of the line health care benefits Full ownership, no micro management Strong equity package 401K Unlimited vacation An actual work/life balance, we aren't trying to run you into the ground. We have families and enjoy life too!

690 Texas St, San Francisco, CA 94107 Mechatronics Systems & Motor Control Engineer ABOUT US: Skip is on a mission to make life joyful through powered movement. Movement is a powerful way to build physical, mental and social health. Yet it is elusive for 2 billion people due to age, injury, or disability. We are building products that will restore mobility for millions and enable a new frontier of joyful movement experiences. We want to build a future where a grandparent can easily outrun their grandkids and no one is left behind at the trailhead. Skip is a 20-person early-stage start-up that spun out of Google X in 2023. With deep cross-disciplinary expertise and key partnerships (e.g. with Arc'teryx) we are uniquely positioned to launch the first commercially successful wearable robotic device, the MO/GO, develop a platform to launch future Movewear products and transform millions of lives in the coming years. More information about Skip and MO/GO can be found at ******************* THE ROLE: We are seeking a highly motivated and adaptable individual who will explore the peaks and valleys of all problems that may come up while building a new generation of wearable robots for everyday life. We are looking for a mechatronics systems engineer who would primarily be responsible for the design, development, testing and validation of our powertrain, including motor control for novel actuators, and complex battery management. The team has just finished an “EVT” build, so we have functional prototypes but they need to be tested, improved and optimised with a whole-system approach. We are a team of 20 phenomenal senior engineers and product leaders, where everyone contributes directly to product development. As such this will start as an individual contributor role, with leadership for critical systems, and directing work for people contributing to the system (e.g. working closely with our test engineer and gearbox designer). Some of the specific responsibilities include, but are not limited to: Understand every element of our mechatronics system; being the go-to person for troubleshooting Guide design and development decisions for future iterations of the product, and future systems; including battery and motor specifications, motor control chip selection and firmware requirements Own the testing protocol to validate performance of the mechatronics at volumes and standards relevant to consumer products (and work with our Test Engineer to execute) Help us precisely control a range of actuators including off-the-shelf BLDCs, custom PMSM and axial flux motors, cycloid gearboxes, and series elastic actuators, including writing firmware for our motor control chip (currently c2000; but likely to change over time) Characterize and model our actuators for open-loop and closed-loop torque control. Create thermal models and evaluate the thermal limits of the actuator. Own the process of productising our novel actuation systems as standalone products and components of a broader platform Wear prototypes several hours a week to participate in data collection, on-body testing and provide feedback Bring joy to the team, participate in embarrassing team events, tolerate KZ's terrible music Basic Qualifications 5+ years' experience working in robotics or mechatronics Extensive experience controlling PMSM, including Ti and STM chipsets Experience with design for systems at scale , with a focus on testing and validation Demonstrable expertise in C/C++ for high performance applications Expertise with Linux, command-line tools, Python scripting Strong experience developing real-time firmware for multi-sensor systems Knowledge of low level hardware and OS internals at a kernel level Attention to detail, even in the middle of overly-long lists Experience with troubleshooting tools (JTAG, SWD, oscilloscopes, logic analyzers) Ability to work at the Skip Bay Area office >3 days/week Sense of humour, tolerant of Aussie & Canadian spelling Bonus Points Experience with powered consumer electronics (e.g. drones, robot vacuums) Experience in start-up environments and using AI coding tools to leverage your skills for broader impact Personal motivation to improve human movement Taylor Swift fan. Good taste in background music :) This is a full time position working at the Skip office in the San Francisco Bay Area, starting ASAP. Skip is an equal opportunity employer. Our hiring decisions are based on need and competence to satisfy said need. We do not discriminate on the basis of race, religion, color, gender, sexual orientation, gender identity, age, marital status, veteran status, disability status, or any other legally protected status. Any and all offers of employment extended by Skip are conditional on candidates' ability to provide satisfactory proof of eligibility to maintain full-time employment in the United States. To apply, send via email a CV and cover letter to **************************

We are building a general AI for humanoid robots that learns in the real world with minimal human supervision. Our approach is based on world-model-based reinforcement learning trained on large-scale data that is practical to collect. This makes it possible to learn reliable behaviors and improve beyond human performance limits. As a founding engineer, you will design and build core systems while helping shape the technical direction from the ground up. Responsibilities Build data pipelines that scale to 100k+ hours of multimodal robot data Scale pre- and post-training runs on 1000s of GPUs Improve inference efficiency on low-power embedded systems Lead core architectural decisions, help define the long-term technical roadmap, and set engineering standards from the beginning Qualifications Strong practical experience building software infrastructure Experience implementing and debugging distributed systems Extensive experience in Python and at least one deep learning library such as PyTorch or JAX Ideally experienced in implementing scalable training pipelines for world-model-based RL Experience with systems programming languages (e.g. Rust, C++) is a plus We're a small, focused team where your contributions would have a major impact. As a founding team member, you'd also have significant ownership in what we're building together - we believe in giving our early engineers meaningful equity that reflects their foundational role.

Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code. If making an impact and having a seat at the table is important to you, this is the opportunity for you. Join our small, rapidly-growing team at Quadric to develop supercomputer technology designed for the Edge. In this position you will be a core member of our hardware team, reporting to the CTO and will have an opportunity to grow in the company of expert technologists who also happen to be good people you'll want to spend time with. Architect, and develop from scratch, a novel set of test benches for a new generation of GPNPU processors Collaborate with architects, HW & SW designers to document verification test plans Implement testbenches using commercial VIPs and/or internal SW utilities Develop directed/random drivers, assembly or C++ programs to efficiently test the design Use coverage metrics to track and communicate progress on verification Requirements At least 5 years of experience in design verification for CPU or GPUs. Deep knowledge of leading verification methodologies for CPU or GPU designs. Expertise in either UVM or C/C++ based CPU or GPU verification. Experience in assembly programming and scripting languages like Python. Benefits Provide competitive salaries and meaningful equity Provide catered lunches, commuter benefits & solid choice of healthcare plans Provide a politics-free community for the brilliant minds who want to make an immediate impact Provide an opportunity for you to build long term career relationships Foster an environment that allows for lasting personal relationships alongside professional ones Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21. Quadric is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, religion, sex, national origin, sexual orientation, age, citizenship, marital status, or disability.

Job Description Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high-performance automotive or autonomous vehicle systems. Unlike other NPUs or neural network accelerators in the industry today that can only accelerate a portion of a machine learning graph, the Quadric GPNPU executes both NN graph code and conventional C++ DSP and control code. If making an impact and having a seat at the table is important to you, this is the opportunity for you. Join our small, rapidly-growing team at Quadric to develop supercomputer technology designed for the Edge. In this position you will be a core member of our hardware team, reporting to the CTO and will have an opportunity to grow in the company of expert technologists who also happen to be good people you'll want to spend time with. Architect, and develop from scratch, a novel set of test benches for a new generation of GPNPU processors Collaborate with architects, HW & SW designers to document verification test plans Implement testbenches using commercial VIPs and/or internal SW utilities Develop directed/random drivers, assembly or C++ programs to efficiently test the design Use coverage metrics to track and communicate progress on verification Requirements At least 5 years of experience in design verification for CPU or GPUs. Deep knowledge of leading verification methodologies for CPU or GPU designs. Expertise in either UVM or C/C++ based CPU or GPU verification. Experience in assembly programming and scripting languages like Python. Benefits Provide competitive salaries and meaningful equity Provide catered lunches, commuter benefits & solid choice of healthcare plans Provide a politics-free community for the brilliant minds who want to make an immediate impact Provide an opportunity for you to build long term career relationships Foster an environment that allows for lasting personal relationships alongside professional ones Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21. Quadric is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, religion, sex, national origin, sexual orientation, age, citizenship, marital status, or disability.

Title: Design Verification Engineer - Internal IP About the Company: A fast-growing AI startup designing next-generation compute hardware. The company specializes in building high-performance IP blocks and accelerators, aiming to enable leading‐edge AI workloads with custom silicon and software stacks. Role Overview: You will lead verification efforts on internal IP blocks that power the company's compute architecture. Working closely with design engineers and systems teams, you'll define verification strategies, develop testbenches, write directed and random stimulus, debug failures, and sign off quality IP for integration into larger systems. Key Responsibilities: Review IP specifications and architecture to understand functional, performance, and integration requirements. Develop verification plans, create functional coverage models, define corner cases and failure modes. Build testbenches using SystemVerilog (or similar HDL), UVM or equivalent methodology, and integrate into simulation/acceleration/emulation flows. Automate regressions, monitor coverage metrics, identify gaps, and work with design teams to close them. Debug and triage simulation/emulation failures, analyze waveforms/traces, provide meaningful feedback to design and physical teams. Collaborate with RTL designers, synthesis and physical teams, CAD and systems/firmware teams to ensure smooth handoff and tape-out readiness. Mentor or collaborate with other engineers to drive verification best practices and process improvements. Qualifications: Strong experience (typically 5 + years) in design verification of digital IP in a hardware environment. Proficiency in SystemVerilog (or equivalent HDL), and verification methodologies (UVM/UVM-like frameworks). Deep understanding of digital logic, microarchitecture (e.g., pipelines, memory subsystems, AXI/AMBA interconnects), timing, and clocking domains. Experience with functional coverage, constrained-random verification, assertions, and testbench development. Familiar with simulation tools, emulation/prototyping flows, and regression automation. Excellent debug skills, ability to drive issues to resolution across cross-functional teams. Bachelor's or Master's in Electrical Engineering/Computer Engineering or equivalent; advanced degree preferred. Strong communication and collaboration skills; ability to lead in a fast-paced startup environment. Nice to Have: Experience in AI/hardware accelerator domain (e.g., tensor cores, matrix engines, AI pipelines). Familiarity with low-power design, clock gating, power domains, and verification of power/clock islands. Experience working with mixed‐signal or analog/mixed-signal IP verification, or prototyping on FPGA/emulation platforms. Background in physical verification, synthesis flow, timing closure or floorplanning. What's in It for You: Opportunity to design and verify cutting-edge compute IP for AI workloads. Early‐stage startup with high autonomy, ownership and the ability to shape architecture and process. Competitive compensation, equity participation and benefits aligned with high-growth startup norms. Collaborative, high-velocity culture driven by innovation and ambitious goals.

ASIC Design Verification Engineer Our client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come. Low Latency has become the key enabler for their industry and other real-time application and the current industry' state-of-the art is just not up to the task. Client has been developing its Neural Net Engines accelerators, optimizing it for Latency and achieving the best LPPA (Latency, Performance, Power, Area) in the field. We are now building the corresponding SoC, to deliver unrivaled products to mission-critical and real-time applications. This is a fast-paced, intellectually challenging position, and you will work with a talented team driven by innovation and excellency. You'll have relentlessly high standards for yourself and everyone you work with, and you'll be constantly looking for ways to improve our products' performance, quality and cost. We're changing the meaning of low latency and we want individuals ready to rise up to the challenge and take the industry by storm. Job Responsibilities Architect and build an SoC-level and unit-level UVM verification environment. Collaborate with Architecture and Design teams to verify the SoC features according to the chip use scenario. Construct the chip level test plans, develop either directed or constrained random test vectors for closing the target coverage. Participate evaluating and selecting third-party VIPs and integrate them into the test bench. Debug test failures by collaborating with stakeholders to identify the root cause of the issues. Develop and maintain the daily and weekly regressions. Required Skills A minimum of 10+years (Principal) / 7+ years (Senior Staff) / 5+ years (Staff) of design verification experience with 1+ years of leader role (for Lead position). Must possess prior experience in developing a complete chip-level UVM test bench from scratch (for principal / Lead role). Expert in coverage driven System verilog UVM with DPI-C, including UVM runtime phases (for Lead/Principal role). Proficient in programming in C/C++, python and/or scripting language. Prior experience in ASIC design verification. In-depth knowledge in bus fabrics; NoC, AMBA etc in multi-CPU environment. Nice to have Prior experience in verifying instruction driven designs like CPUs and GPGPUs. Understanding of chip security, cold/warm boot sequences. Experiences using SERDES based high speed interfaces, i.e. MIPI, PCIe and USB. FPGA prototyping experience. Knowledge in ISO-26262 ASIL compliances. Education BSEE/BSCE required Master in Science preferred. Featured benefits Medical insurance Vision insurance Dental insurance 401(k)

Job DescriptionOur client is a world-leading technology company at the forefront of semiconductor innovation, powering some of the most advanced digital systems in the industry. Their work touches billions of users globally, driving next-generation performance and efficiency across highly complex hardware and software ecosystems.They are seeking a Design Verification Engineer with deep expertise in SystemVerilog/UVM and digital ASIC verification. This role is critical for ensuring robust, reusable verification environments, achieving high functional coverage, and supporting rapid innovation in complex hardware designs that operate at massive scale.What You'll Do Develop comprehensive Core Verification Plans based on unit micro-architecture and design specifications. Architect and implement reusable verification environments using SystemVerilog/UVM. Create and execute constrained-random and directed tests to achieve high functional and code coverage for core units. Analyze simulation results, debug complex failures, and collaborate with design teams to root-cause and resolve issues. Develop and maintain scripts (Python/Perl) to automate verification flows and regression management. Support verification of digital systems using standard IP components and interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Act as a technical leader within verification teams, providing feedback to RTL designers and IP architects. Requirements SystemVerilog/UVM expertise is mandatory. At least 7 years of hands-on expertise. Strong grasp of digital logic design and verification methodologies. Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems). Proven ability to work autonomously and demonstrate technical confidence when engaging with, and providing constructive feedback to, FE RTL design teams and CPU/IP micro-architects. Proficiency with industry-standard EDA simulation and debug tools. Solid abilities in debugging and root-cause analysis. Experience with scripting (Python, Perl). Excellent written and verbal communication skills in English are required. Nice-to-Have Qualifications (Not required, but beneficial) Experience in high-performance computing or large-scale SoC verification. Familiarity with emerging verification methodologies and flows. Prior involvement in multi-team or cross-site verification projects. Why This Role MattersThis position is central to delivering high-performance, reliable digital hardware at global scale. You will have the opportunity to shape verification strategies, implement reusable test environments, and contribute to cutting-edge projects that power complex systems used by millions worldwide. This is an environment where technical expertise meets massive real-world impact.Confidentiality Statement: At Quix Recruitment, we prioritise confidentiality throughout the recruitment process. We understand the sensitivity of exploring new career opportunities while currently employed. Rest assured that when you apply through Quix Recruitment, your application is kept completely confidential from both your current employer and the hiring company. If we determine that you might be a good fit for the position, we will arrange a confidential call with you to discuss the opportunity in more depth. Only after obtaining your permission will we share your CV with the hiring company.Disclaimer: Please note that all personal information collected during the application process will be used for recruitment-related purposes only. We are committed to protecting your privacy and will not disclose your information to any third parties without your consent.

About the Team: OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We're looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems-ranging from individual IP blocks to subsystems and full SoC-working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. Key Responsibilities Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. Qualifications BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives. Familiarity with performance modeling, formal verification, or emulation is a plus. Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware. To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations. About OpenAI OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity. We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic. For additional information, please see OpenAI's Affirmative Action and Equal Employment Opportunity Policy Statement. Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US-based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations. To notify OpenAI that you believe this job posting is non-compliant, please submit a report through this form. No response will be provided to inquiries unrelated to job posting compliance. We are committed to providing reasonable accommodations to applicants with disabilities, and requests can be made via this link. OpenAI Global Applicant Privacy Policy At OpenAI, we believe artificial intelligence has the potential to help people solve immense global challenges, and we want the upside of AI to be widely shared. Join us in shaping the future of technology.

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. **Meet the Team** The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. **Your Impact** ** ** Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. **Minimum Qualifications** ** ** + Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degreeprogram.Familiaritywith hardware description languages (HDLs), such as Verilog or VHDL. + Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). + Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. + Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) + Understanding of physical design and DFT (Design for Test) principles + Familiarity with Linux-based development environments + Ability to adapt to new technologies and problem-solve sophisticated engineering challenges + Excellent organizational, teamwork, and communication skills **Why Cisco** ** ** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to work in the U.S. and/or Canada:** Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: + 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees + 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco + Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees + Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) + 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next + Additional paid time away may be requested to deal with critical or emergency issues for family members + Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: + .75% of incentive target for each 1% of revenue attainment up to 50% of quota; + 1.5% of incentive target for each 1% of attainment between 50% and 75%; + 1% of incentive target for each 1% of attainment between 75% and 100%; and + Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.

Let your dog walker into your apartment while you're at the office. Or grant your in-laws access to the building's gym while you're sunning on a beach. It'll be possible at new projects by some of the biggest U.S. builders. Toll Brothers Inc., Brookfield Property Partners LP, RXR Realty and Related Group of Florida are among developers incorporating smart-access technology from this leader in door access in selected upcoming condo and rental projects. Users can grant access to guests and service providers, like dog walkers and cleaners, by providing them temporary entry codes. A wide-angle camera embedded in the hardware at each doorway will create a visual record of every interaction by a non-resident -- all of it viewable through the Latch app on the resident's phone. Job Description Our Client is seeking a Senior Embedded Android Engineer to be based in our San Francisco office . In this role you will be an integral part of a stellar engineering team responsible for building new products. You will work within a highly cross-functional feature team and collaborate closely with mobile, backend and hardware engineers. You will be focussed on firmware development for IoT devices, including board bring up, writing low level device drivers and delivering high quality, robust product firmware. This position is an exciting opportunity to be part of a growing team as we add value to our expanding product family. Qualifications Responsibilities: Participate in design, development, verification, troubleshooting, and delivery of high quality firmware. Deliver resilient and robust designs - Lead and participate in technical discussions across engineering and product teams. Work with the electrical team for hardware bring up and verification of new designs. Work closely with the software and mobile teams for definition and implementation of wireframes used by devices for wireless communications. Write low level peripheral drivers needed for board and application bring up. Perform power consumption analysis and optimize firmware for low power battery operation. Qualifications: BS or above in EE/CS. 5+ years of experience in software development on Embedded Android AOSP /Embedded Linux based systems. Experience in Linux kernel, device tree, Android/Linux device driver and HAL layers as well as Android Framework layers. Knowledgeable in C/C++, Linux, RTOS's and Object Oriented Design/Architecture Knowledge of mobile device emerging technologies including Smartphone LTE architectures, wireless IoT- BLE/Internet connected devices, camera/video, and touch screen displays. Experience working with device drivers for serial communication protocols such as SPI/I2C/RS-232/USB etc. Ability to work well independently and in close collaboration with a remote team. Ability to travel and work in 1-2 week increments periodically in the NYC office as needed. Preferred: Knowledge and experience working with Security, Cryptography a huge plus. Deep knowledge of electrical concepts and comfortable reading hardware schematics and debugging hardware at a board level. Familiarity/Experience working with network stacks and protocols TCP/IP, UDP, MQTT etc Prior experience with AWS, REST API's and Android App development is a plus Familiarity or experience with Agile/Scrum methodology and practices. Additional Information All your information will be kept confidential according to EEO guidelines.

The Senior Embedded Networking Engineer is the technical expert to the Tech Ops team through the lifecycle of a project. This role will design and implement cutting edge networks, using Cisco, ACI, SDN and more. They are accountable to ensure a project is executed with excellence as well as meets all design requirements laid out in the scope of work. This position will be responsible for the design, configuration, and deployment of networks for audio video and telecommunications systems in commercial environments. They will be the subject matter expert in data network support for the technical operations team. Additionally, this position will provide new network designs for office build-outs in new locations. This position is an embedded role, working for AVDG, but being based at another company 5 days a week . THIS IS A 6 MONTH CONTRACT ROLE ONSITE MONDAY - FRIDAY - 40 HOURS PER WEEK Minimum Experience Requirements: BS/BA information technology, computer systems engineering, or related field At least 5+ years of recent experience in Networking and AV integration and support with Cisco, IOS/NX-OS experience Experience with Cisco ACI,SD-WAN and layer 4/7 firewalls. Cisco certifications (CCDA/CCDP, CCNA/CCNP routing and switching, CCNA/CCNP security) preferred Experienced with Cisco firepower, ASA, VPN, BGP, OSPF, MPLS, QOS. Expert knowledge of network technologies including WAN, LAN, Firewalls, Load Balancers, L3 Routing and L2 Switching. Must versed in best practices for installation and termination of layer 1 network devices (per BICSI, AVIXA, etc.) Must be able to interpret and mark up construction and technical drawings Experience working with clients in a professional manner Must be able to effectively explain technical concepts to non-technical users Highly skilled in oral and written communication clear, direct, detailed. Independent work ethic highly motivated to getting a job done right MS Office able to use Excel, Word, PowerPoint, Access proficiently without training Responsibilities & Duties: Monitor, maintain and design networks, configure and implement SDN fabric overlays using Cisco ACI. Cisco background, strictly network support, firewall. Configure layer 4/7 firewalls and application load balancers. Collaborate with audit teams to ensure compliance Troubleshoot and maintain cisco routers, switches (ASR, ISR, 9k,5k,3k,2k) and network security infrastructure Be the technical expert in the quality control process of each project as it relates to data networking. Interface & maintain ongoing dialogue with engineers, project management and clients as to project timelines, challenges, and training. Direct technical teams on installation best practices. Sales support for network related design. Job Types: Full-time, Contract Work Location: In person

Senior Neuro-Symbolic Systems Engineer - San Francisco, CA A company building AI systems that can interact with the physical world at scale - designing experiments, controlling hardware, and accelerating scientific discovery from days to reality are looking for a Senior Neuro-Symbolic Systems Engineer to join their team. What Will I Be Doing: Design and implement structured representations such as hypergraphs, relational models, symbolic planners, or similar abstractions Build update rules, inference mechanisms, and dynamic graph operations that support multi-step reasoning and coordination Work with agent, simulation, and data infrastructure teams to integrate symbolic structures into real workflows Develop tools for evaluating correctness, consistency, and stability of graph-based representations Operate as a cross-functional technical partner to ensure symbolic layers work alongside ML, RL, and systems architecture components What We're Looking For: Strong background in symbolic AI, knowledge representation, graph systems, computational logic, or neuro-symbolic methods Experience designing or implementing structured representations for planning, reasoning, or complex workflows Familiarity with ML toolchains and comfort bridging symbolic and statistical systems Ability to design abstractions and system architectures that support large-scale, real-time updates High-agency engineer who enjoys defining new structures and building them from first principles What's In It For Me: Salary of $200,000 - $300,000 dependent on experience Greenfield work. Build something that doesn't exist, at the frontier of physical AI and automated hardware design Real impact. Control actual physical systems contributing to breakthroughs in cancer detection, materials science, and more Join a company backed by significant venture funding and a $42M government research programme Apply now for immediate consideration!

We are actively searching for a Distributed Systems Engineer to join our team on a permanent basis. In this founding engineer role you will focus on building next-generation data infrastructure for our AI platform. If you have a passion for distributed systems, unified storage, orchestration, and retrieval for AI workloads we would love to speak with you. Our office is located in downtown SF and we collaborate two days a week onsite. Your Rhythm: Design, build, and maintain data infrastructure systems such as distributed compute, data orchestration, distributed storage, streaming infrastructure, machine learning infrastructure while ensuring scalability, reliability, and security Ensure our data platform can scale by orders of magnitude while remaining reliable and efficient Tackle complex challenges in distributed systems, databases, and AI infrastructure Collaborate with technical leadership to define and refine the product roadmap Write high-quality, well-tested, and maintainable code Contribute to the open-source community and engage with developers in the space Your Vibe: 3+ years of professional distributed database systems experience Expertise in building and operating scalable, reliable and secure database infrastructure systems Strong knowledge around distributed compute, data orchestration, distributed storage, streaming infrastructure Strong knowledge of SQL and NoSQL databases, such as MySQL, Postgres, and MongoDB. Programming skills in Python Passion for building developer tools and scalable infrastructure Available to collaborate onsite 2 days a week Our Vibe: Relaxed work environment 100% paid top of the line health care benefits Full ownership, no micro management Strong equity package 401K Unlimited vacation An actual work/life balance, we aren't trying to run you into the ground. We have families and enjoy life too!

690 Texas St, San Francisco, CA 94107 Mechatronics Systems & Motor Control Engineer ABOUT US: Skip is on a mission to make life joyful through powered movement. Movement is a powerful way to build physical, mental and social health. Yet it is elusive for 2 billion people due to age, injury, or disability. We are building products that will restore mobility for millions and enable a new frontier of joyful movement experiences. We want to build a future where a grandparent can easily outrun their grandkids and no one is left behind at the trailhead. Skip is a 20-person early-stage start-up that spun out of Google X in 2023. With deep cross-disciplinary expertise and key partnerships (e.g. with Arc'teryx) we are uniquely positioned to launch the first commercially successful wearable robotic device, the MO/GO, develop a platform to launch future Movewear products and transform millions of lives in the coming years. More information about Skip and MO/GO can be found at ******************* THE ROLE: We are seeking a highly motivated and adaptable individual who will explore the peaks and valleys of all problems that may come up while building a new generation of wearable robots for everyday life. We are looking for a mechatronics systems engineer who would primarily be responsible for the design, development, testing and validation of our powertrain, including motor control for novel actuators, and complex battery management. The team has just finished an “EVT” build, so we have functional prototypes but they need to be tested, improved and optimised with a whole-system approach. We are a team of 20 phenomenal senior engineers and product leaders, where everyone contributes directly to product development. As such this will start as an individual contributor role, with leadership for critical systems, and directing work for people contributing to the system (e.g. working closely with our test engineer and gearbox designer). Some of the specific responsibilities include, but are not limited to: Understand every element of our mechatronics system; being the go-to person for troubleshooting Guide design and development decisions for future iterations of the product, and future systems; including battery and motor specifications, motor control chip selection and firmware requirements Own the testing protocol to validate performance of the mechatronics at volumes and standards relevant to consumer products (and work with our Test Engineer to execute) Help us precisely control a range of actuators including off-the-shelf BLDCs, custom PMSM and axial flux motors, cycloid gearboxes, and series elastic actuators, including writing firmware for our motor control chip (currently c2000; but likely to change over time) Characterize and model our actuators for open-loop and closed-loop torque control. Create thermal models and evaluate the thermal limits of the actuator. Own the process of productising our novel actuation systems as standalone products and components of a broader platform Wear prototypes several hours a week to participate in data collection, on-body testing and provide feedback Bring joy to the team, participate in embarrassing team events, tolerate KZ's terrible music Basic Qualifications 5+ years' experience working in robotics or mechatronics Extensive experience controlling PMSM, including Ti and STM chipsets Experience with design for systems at scale , with a focus on testing and validation Demonstrable expertise in C/C++ for high performance applications Expertise with Linux, command-line tools, Python scripting Strong experience developing real-time firmware for multi-sensor systems Knowledge of low level hardware and OS internals at a kernel level Attention to detail, even in the middle of overly-long lists Experience with troubleshooting tools (JTAG, SWD, oscilloscopes, logic analyzers) Ability to work at the Skip Bay Area office >3 days/week Sense of humour, tolerant of Aussie & Canadian spelling Bonus Points Experience with powered consumer electronics (e.g. drones, robot vacuums) Experience in start-up environments and using AI coding tools to leverage your skills for broader impact Personal motivation to improve human movement Taylor Swift fan. Good taste in background music :) This is a full time position working at the Skip office in the San Francisco Bay Area, starting ASAP. Skip is an equal opportunity employer. Our hiring decisions are based on need and competence to satisfy said need. We do not discriminate on the basis of race, religion, color, gender, sexual orientation, gender identity, age, marital status, veteran status, disability status, or any other legally protected status. Any and all offers of employment extended by Skip are conditional on candidates' ability to provide satisfactory proof of eligibility to maintain full-time employment in the United States. To apply, send via email a CV and cover letter to **************************

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Applications are accepted until further notice. Meet the Team The ASIC Group works closely with other development teams within Cisco, including marketing, system hardware, software, product engineering, and manufacturing. Through this collaboration, members of our group play a major role in defining, developing and bringing new products to market across Cisco's product line. Open-minded, driven, diverse and deeply creative people at Cisco craft the hardware that makes the internet work. Bring your knowledge of computers and networking and take it to a new level in any one of the following product categories including: cloud, social, mobile/wireless, video, VoIP, collaboration, web, Internet of Things, routing, switching, IPv6, data center, HPC, TelePresence and many more. Your work will affect billions globally. Your Impact Join our award-winning ASIC team, where you'll collaborate with top industry talent to design and deliver ground breaking communications and network processing silicon. You'll contribute to system and processor architecture, high-speed logic design and verification, digital signal processing, memory and custom library development, physical design, DFT, signal integrity, and advanced packaging. Work with the latest VLSI techniques and deep submicron technologies, owning projects from concept to in-house physical implementation. Minimum Qualifications * Completion within the past 3 years, or current enrollment with expected completion within 12 months, of a Bachelor's degree program. Familiarity with hardware description languages (HDLs), such as Verilog or VHDL. * Experience with RTL design and simulation tools (e.g., Synopsys, Cadence, Mentor Graphics). * Exposure to scripting languages (e.g., Python, Perl, TCL) for automation. * Familiarity with ASIC/SoC design flow including synthesis, place & route, and timing closure. Preferred Qualifications * Experience with ASIC verification methodologies (e.g., UVM, SystemVerilog) * Understanding of physical design and DFT (Design for Test) principles * Familiarity with Linux-based development environments * Ability to adapt to new technologies and problem-solve sophisticated engineering challenges * Excellent organizational, teamwork, and communication skills Why Cisco At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Simply put - we power the future. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: * 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees * 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco * Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees * Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) * 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next * Additional paid time away may be requested to deal with critical or emergency issues for family members * Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: * .75% of incentive target for each 1% of revenue attainment up to 50% of quota; * 1.5% of incentive target for each 1% of attainment between 50% and 75%; * 1% of incentive target for each 1% of attainment between 75% and 100%; and * Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $94,200.00 - $137,500.00 Non-Metro New York state & Washington state: $84,000.00 - $122,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Let your dog walker into your apartment while you're at the office. Or grant your in-laws access to the building's gym while you're sunning on a beach. It'll be possible at new projects by some of the biggest U.S. builders. Toll Brothers Inc., Brookfield Property Partners LP, RXR Realty and Related Group of Florida are among developers incorporating smart-access technology from this leader in door access in selected upcoming condo and rental projects. Users can grant access to guests and service providers, like dog walkers and cleaners, by providing them temporary entry codes. A wide-angle camera embedded in the hardware at each doorway will create a visual record of every interaction by a non-resident -- all of it viewable through the Latch app on the resident's phone. Job Description Our Client is seeking a Senior Embedded Android Engineer to be based in our San Francisco office. In this role you will be an integral part of a stellar engineering team responsible for building new products. You will work within a highly cross-functional feature team and collaborate closely with mobile, backend and hardware engineers. You will be focussed on firmware development for IoT devices, including board bring up, writing low level device drivers and delivering high quality, robust product firmware. This position is an exciting opportunity to be part of a growing team as we add value to our expanding product family. Qualifications Responsibilities: Participate in design, development, verification, troubleshooting, and delivery of high quality firmware. Deliver resilient and robust designs - Lead and participate in technical discussions across engineering and product teams. Work with the electrical team for hardware bring up and verification of new designs. Work closely with the software and mobile teams for definition and implementation of wireframes used by devices for wireless communications. Write low level peripheral drivers needed for board and application bring up. Perform power consumption analysis and optimize firmware for low power battery operation. Qualifications: BS or above in EE/CS. 5+ years of experience in software development on Embedded Android AOSP /Embedded Linux based systems. Experience in Linux kernel, device tree, Android/Linux device driver and HAL layers as well as Android Framework layers. Knowledgeable in C/C++, Linux, RTOS's and Object Oriented Design/Architecture Knowledge of mobile device emerging technologies including Smartphone LTE architectures, wireless IoT- BLE/Internet connected devices, camera/video, and touch screen displays. Experience working with device drivers for serial communication protocols such as SPI/I2C/RS-232/USB etc. Ability to work well independently and in close collaboration with a remote team. Ability to travel and work in 1-2 week increments periodically in the NYC office as needed. Preferred: Knowledge and experience working with Security, Cryptography a huge plus. Deep knowledge of electrical concepts and comfortable reading hardware schematics and debugging hardware at a board level. Familiarity/Experience working with network stacks and protocols TCP/IP, UDP, MQTT etc Prior experience with AWS, REST API's and Android App development is a plus Familiarity or experience with Agile/Scrum methodology and practices. Additional Information All your information will be kept confidential according to EEO guidelines.