Engineer jobs in Manteca, CA - 1,962 jobs

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology. Description In Physical Design, you will be at the center of design effort collaborating with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs and knowledge of basic chip architecture, back end chip design flow, physical synthesis, floor‑planning, place and route (PnR), power grid, timing (STA), physical design verification (DRC/LVS), EMIR (Redhawk/Totem/Voltus). Responsibilities would include: Working with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Timing, physical and electrical verification and driving the signoff closure for the partitions. Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum Qualifications Basic understanding of logic gates. Preferred Qualifications Previous internship/co‑op, project work or relevant coursework in computer architecture, VLSI, design, logic design, or circuit design. Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields. Experience with Verilog, VHDL, Python, Perl, TCL and/or SPICE. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $126,800 and $190,900, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

Meet The Team Cisco Webex is the world's #1 business collaboration and customer engagement platform. It is used across all industries in the world being used to support governments, business, education, and more, including use by 85% of Fortune 500 business. The workplace of the future will be powered by AI, and we, Collaboration AI, is the team responsible for building AI/ML intelligent experiences within Cisco's Webex portfolio. The team is made up of multiple major AI fronts to enrich the collaboration use cases. This, in the order of processing pipeline, includes audio codec technologies, automatic speech recognition (ASR), text-to-speech (TTS), natural language processing (NLP) using and training LLMs and beyond, and gen‑AI evaluation methodologies, both metric-based and subjective testing. In addition, videos are empowered via computer vision (CV) and additional contextual information by employee graphs, and much more. We aim to build the next-generation AI solutions in collaboration software, devices, and APIs - from digitizing the in‑meeting, enhancing distributed team efficiency and improving all aspects of people connection. Your Impact In this role, you will be responsible for conducting applied NLP research to advance our Language AI features. This includes, but not limited to, hierarchical summarization, internationalization, evaluation of generated texts, human alignment, and more fundamentally, a crucial set of techniques that can utilize the existing pre‑/mid‑/post‑trained LLM model checkpoints to the best extent, by, for instance, fine‑tuning, adaptation, model surgery/editing, and reinforcement learning to customize models for the business need, for cloud, on‑prem, and on‑device deployment. Your duties will include innovating and employing cutting‑edge technologies with the consideration of practical product launch, which concerns optimization of performance, scalability, safety, reliability, and measurable generation quality. Staying up to date with the latest advancements in AI and machine learning (ML) is expected, as is suggesting how new technologies might be implemented. Addressing and resolving any modeling issues that arise from product applications will be an integral part of your responsibilities: Advance Collaboration AI's Language AI capabilities by researching, prototyping, and implementing next‑generation LLM technologies Conduct rigorous applied NLP research following systematic methodology: establish benchmarks, evaluate baselines, perform ablation studies, and deliver actionable recommendations Develop and evaluate NLP models that address specific business requirements Balance technical trade‑offs (performance, latency, cost, quality) to determine optimal production solutions Collaborate with product managers and stakeholders to translate research into production features Write production‑ready code with appropriate testing, documentation, and deployment considerations Pursue publication opportunities at top‑tier NLP and ML conferences Minimum Qualifications Recent graduate or in your final year of studies toward a PhD, or Master's degree with 3+ years of post‑graduation work experience in related fields. Relevant fields include Computer Science, Data Science, Statistics, Mathematics, Engineering, or a related STEM program Strong foundation in machine learning and natural language processing, including familiarity with transformer architectures, common training schemes, and evaluation methodologies Proficiency in Python and experience with at least one deep learning framework Demonstrated NLP or ML research experience through publications, technical reports, thesis work, or significant contributions to related projects Preferred Qualifications At least one NLP or ML research paper published in a top‑tier conference, such as ACL, EMNLP, ICLR, ICML, NeurIPS, etc. Experience in using cloud services such as AWS, Google Cloud Platform, and Azure, for model training and deployment. Experience writing production‑quality Python code including testing, documentation, and code review practices Familiar with LLM benchmarking methods and experience analyzing benchmark datasets Experience collaborating with cross‑functional teams to deliver production ML solutions Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: Individual pay is determined by the candidate's hiring location, market conditions, job‑related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long‑term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: 10 paid holidays per full calendar year, plus 1 floating holiday for non‑exempt employees 1 paid day off for employee's birthday, paid year‑end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco Non‑exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full‑time employees Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next Additional paid time away may be requested to deal with critical or emergency issues for family members Optional 10 paid days per full calendar year to volunteer For non‑sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance‑based incentive pay on top of their base salary, which is split between quota and non‑quota components, subject to the applicable Cisco plan. For quota‑based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non‑quota‑based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $181,000.00 - $270,300.00 Non‑Metro New York state & Washington state: $165,300.00 - $240,600.00 For quota‑based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non‑exempt, will participate in a unique time off program to meet local requirements. Cisco is an affirmative action and equal opportunity employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status or any other legally protected basis. Cisco will consider for employment, on a case‑by‑case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr

A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship. #J-18808-Ljbffr

A leading tech company invites applications for a Machine Learning Engineer to advance AI research in California. The role focuses on Generative AI and requires a PhD or Master's degree, with a minimum of 3 publications in AI. The candidate will collaborate across teams and publish findings, contributing to networking solutions and AI innovations. This full-time position offers a competitive salary and benefits, fostering an inclusive workplace culture. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.Join us in our journey to becoming the world's #1 FPGA company!Altera is seeking a **Senior Design Automation Engineer** to join our Design Methodology Automation and Infrastructure Team.The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next-generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross-functional teams to deliver world-class automation solutions.**Key Responsibilities:*** Architect next-generation unified FPGA/SoC design methodologies spanning Front-End, handoff to Backend, Design Verification, Design-For-Test (DFT), Design Data Management/Release flows, and FPGA-specific flows such as Design Intent and Configuration Management.* Develop and integrate state-of-the-art EDA solutions, including ML/AI-enhanced tools, flows, and methodologies-sourced externally or developed internally-to create sustainable, scalable automation solutions for multiple chip design programs.* Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.* Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn-around time, and enhance design optimization.* Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.* Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.* Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.* Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross-functional initiatives to streamline FPGA design execution.* Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.* Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimizations.* Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next-generation capabilities.* Mentor and provide technical leadership to junior engineers within the Design Automation organization.#LI-MD1**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$142,600 - $206,500 USDWe use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 10 years of experience in IC Design or Design Automation and experience in the following:* Extensive experience with industry-standard EDA tools and hands-on expertise in design methodologies across multiple domains, such as Front-End Logic Design flows, Design Intent and FPGA-specific flows, Design Verification flows, and Design-for-Test (DFT) flows (with Back-End flow knowledge considered a plus).* Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.* Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimizations.* Proven leadership skills for driving collaborative, cross-functional projects, with strong communication and influencing abilities### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

Pre-layout STA to ascertain feasibility, timing constraint validation and feedback to customers and design teams Chip/Block Level Floorplanning and pin assignment Review top-level/block-level clock specifications for completeness and feasibility Handle all the Physical design tasks (Placement, Timing Optimization, Clock Tree Synthesis, Routing) Perform sign-off tasks (RC Extraction, Static Timing Analysis, IR drop analysis and Physical Verification) Presentations and Customer Interaction in customer meetings Necessary Qualifications: BSEE, with 9+ years of experience or equivalent experience. MSEE preferred. Experience in ASIC Physical Design; Experience in an SoC product development organization with tapeouts at 28nm/16nm design nodes. Hands-on Experience with implementation EDA tools like ICC2/Innovus. Scripting (Perl/Tcl/Python) is required. Good understanding of ASIC frontend design. Experience in both Flat and Hierarchical layouts. Strong problem‑solving skills and ability to analyze and resolve physical design issues related to library, timing constraints or CAD tools is required. Experience with power analysis and IR‑drop tools (primepower/Redhawk) and Static Timing Analysis (Primetime). Experience with Physical Verification and fix PV errors in layout. Expert handling of Verilog HDL based Netlists, Physical design libraries. Team player with good interpersonal and communication skills; ability to explain processes and answer customer questions during meetings. Compensation: $190,000.00 - $200,000.00 per year MAKING THE INDUSTRY'S BEST MATCHES DBSI Services is widely recognized as one of the industry's fastest growing staffing agencies. Thanks to our longstanding experience in various industries, we have the capacity to build meaningful, long‑lasting relationships with all our clients. Our success is a result of our commitment to the best people, the best solutions and the best results. Our Story: Founded in 1995 Privately Owned Corporation Managing Partner Business Model Headquartered in New Jersey US Based Engineers Only Methodology and Process Driven Top performing engineers are the foundation of our business. Our priority is building strong relationships with each employment candidate we work with. You can trust our professional recruiters to invest the time required to fully understand your skills, explore your professional goals and help you find the right career opportunities. #J-18808-Ljbffr

Join ERM and be part of a global team delivering innovative air quality and climate solutions for the world's most dynamic industries. Why This Role Matters At ERM, we're shaping the future of environmental consulting by tackling some of the most complex air quality and climate challenges for leading global companies. As a Managing Consultant, Environmental Air Quality, Engineering or Science , you'll play a pivotal role in guiding clients through regulatory landscapes, driving innovative solutions, and influencing strategies that impact industries and communities worldwide. This is your opportunity to lead, innovate, and make a measurable difference in Walnut Creek, CA, Sacramento, CA, Scottsdale, AZ or Denver, CO . What Your Impact Is Lead strategic air permitting and compliance programs for high-profile industrial clients. Serve as a trusted advisor, helping clients maintain operational flexibility while meeting regulatory requirements. Drive business growth by building strong client relationships and expanding ERM's market presence. Mentor and develop project teams across multiple offices, fostering technical excellence and collaboration. Contribute to ERM's national Air Quality & Climate Change technical community, sharing best practices and shaping industry standards. What You'll Bring Required: Bachelor's degree in Environmental Science, Chemical, Environmental, or Mechanical Engineering (or related discipline). 4+ years of experience in air quality compliance, permitting, and regulatory programs. Proven ability to manage multiple projects and build lasting client relationships. Strong communication, analytical, and technical writing skills. Driver's License Required: This position requires a valid driver's license and/or the ability to operate a company vehicle due to the nature of job duties, which include travel to various client locations across a large geographical area. This position is not eligible for immigration sponsorship. Preferred: Master's degree in a related discipline. Experience in refinery, chemical, or technology sectors. Professional certifications (P.E., CSP, CHMM, or similar). Familiarity with AERMOD, GIS, health risk assessments, CEQA, and other compliance programs. Key Responsibilities Manage complex air permitting and compliance assurance programs under NSR, PSD, Title V, and state-level regulations. Conduct regulatory analyses and develop permitting strategies tailored to client operations. Engage with regulators to facilitate permit reviews and approvals. Prepare technical proposals and lead business development initiatives. Build and maintain client relationships that drive repeat business and market growth. Mentor junior staff and manage project teams across multiple ERM offices. For the Managing Consultant, Environmental Air Quality, Engineering or Science position, the anticipated annual base pay is $100,940 - $132,849 USD. Actual pay will depend on factors such as education, experience, skills, location, performance, and business needs. In some cases, pay may fall outside this range. This role may be eligible for bonus pay (casual and fixed term/flex force employees are not bonus eligible). We offer a comprehensive benefits package, including paid time off, parental leave, medical, dental, vision, life, disability, AD&D insurance, 401(k) or RRSP/DPSP, and other applicable benefits to eligible employees. Note:Bonuses, commissions, and other forms of additional compensation are not guaranteed and subject to the sole discretion of ERM and its policies and procedures. Who We Are: As the largest global pure play sustainability consultancy, we partner with the world's leading organizations, creating innovative solutions to sustainability challenges and unlocking commercial opportunities that meet the needs of today while preserving opportunity for future generations. At ERM we know that creating a diverse, equitable and inclusive work environment is an essential part of making our company a great place to build a career. We also see our diversity as a strength that helps us create better solutions for our clients. Our diverse team of world-class experts supports clients across the breadth of their organizations to operationalize sustainability, underpinned by our deep technical expertise in addressing their environmental, health, safety, risk and social issues. We call this capability our “boots to boardroom” approach for its comprehensive service model that allows ERM to develop strategic and technical solutions that advance objectives on the ground or at the executive level. Please submit your resume and brief cover letter. ERM does not accept recruiting agency resumes. Please do not forward resumes to our jobs alias, ERM employees or any other company location. ERM is not responsible for any fees related to unsolicited resumes. ERM is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, gender, sexual orientation, gender identity, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. Thank you for your interest in ERM! #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Senior High-Speed Mixed-Signal Layout/Analog Engineer. In this role, you will collaborate with circuit designers, optimize performance for SERDES analog PHY, and utilize tools like Virtuoso and Calibre. Ideal candidates have a Bachelor's with extensive experience in RF/analog design. The position offers a competitive salary ranging from $180,950 to $289,050 USD and comprehensive benefits including medical, dental, and flexible work options. #J-18808-Ljbffr

A leading network and security company is seeking an Engineering Sr Manager to lead a team building and operating distributed cloud services. The role requires over 10 years of software engineering experience, including significant leadership experience. The successful candidate will drive engineering best practices, ensure secure and scalable solutions, and collaborate across teams. This position is hybrid, allowing flexibility in work location, and offers an attractive salary range between $216,800 and $325,200, complemented by various benefits. #J-18808-Ljbffr

About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is looking for exceptional PD engineers to join our team. The candidate will be responsible for working with 3rd party design services to implement and verify physical designs, and will help Etched as we work to improve iteration speed on physical design. Representative projects Supervise the outsourcing of physical design to a 3rd party service Deeply understand what is involved in physical design Running Physical Design flows to close blocks, support ASIC infrastructure, automate Physical Design flows, improve CAD infrastructure Drive dashboards that show the convergence of projects related to Physical Design Optimize tool flows, working with EDA vendors to incorporate the latest features Accountable for block level closure Requirements 2+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on 3nm-7nm Experience with UPF-based low power design methodology, power verification, synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis Deeply creative and able to think from first principles Desired qualifications: Familiarity with transformer models and machine learning. Familiarity with Cadence or Synopsys automated RTL-to-GDSII flows Ability to program with Python or another scripting language. We encourage you to apply even if you do not believe you meet every single qualification. Benefits: Full medical, dental, and vision packages, with generous premium coverage Housing subsidy of $2,000/month for those living within walking distance of the office Daily lunch and dinner in our office Relocation support for those moving to West San Jose Compensation Range $150,000 - $275,000 How we're different: Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in West San Jose, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. #J-18808-Ljbffr

About us: FLINT focuses on the design-build and design-assist delivery methods, producing the highest quality of projects and yielding the greatest value to our clients. Our employees and industry partners are truly some of the best people you will ever work with. FLINT is built on values, ethics, quality design, and exceptional construction. Our “master builder” approach to design and construction is the hallmark of our firm. FLINT is honored to be selected as the General Contractor of the Year by the Associated Subcontractors Alliance of Sacramento for five consecutive years. One of the key attributes to the success of FLINT is the employment and retention of highly talented individuals. From this, FLINT has established itself as one of the preeminent Design-Builders in the western region. Our relationships and experiences have shaped our purpose: to create an extraordinary building experience through collaboration with passionate professionals. Who we are seeking: » 3+ years of experience, capable of performing project management functions on small projects ($2-$5M) with minor Project Management oversight. Essential job functions: » Manage overall project administration and ensure compliance with all project requirements. » Engage with architects and owners for business development. » Draft and review subcontracts and purchase orders to ensure the scope of work is accurately defined. » Review project documents and familiarize with project participants. » Determine submittal requirements and maintain the submittal log. » Develop and maintain overall project schedules and short-term schedules. » Conduct regular site visits to ensure proper construction and adherence to schedule. » Obtain necessary permits and ensure timely receipt of recorded documents. » Strong grasp of construction terminology and activities. » Basic understanding of all trades including MEP and building permit process. » Ability to estimate CORs, assist in bidding, and assemble project estimates. » Proficiency in cost control types and delivery methods. » Skills in project documentation, scheduling, safety practices, and technology tools (Fieldview, Viewpoint, Team VPT1, Bluebeam, Pype, GCPay, P6, and Vista). » Business development skills with the ability to maintain customer relations. » Understanding of fee enhancement, risk mitigation, and client management. » Ability to mentor team members and promote teamwork and cooperation.

Seeking a top-tier Project Engineer for high-end residential construction. Are you looking for a challenge and opportunity to grow? Are you interested in working on architecturally-driven, high-end residential projects throughout Northern California? FORMA Construction, an award-winning firm, seeks a motivated, detail-oriented Project Engineer to help our clients build their dream homes. The Project Engineer role is a critical hub for FORMA. In coordination with the Project Manager and the Superintendent; the PE works closely with clients, architects, designers, subcontractors, and other vendors. The PE tracks progress and updates budgets while keeping the project well-documented and running smoothly ensuring that our clients are informed and consulted every step of the way. Success in this role is measured by your ability to maintain project documents like RFI's and Submittals among other tasks within Procore while maintaining good relations with our clients, vendors, and other stakeholders. At FORMA, our Mission is the continual development of our people and processes to create lasting relationships built on integrity, partnership, and craft. Our core values are based on Urgency, Ownership, Communication and Craft. FORMA's clients and work sites take us throughout the greater Bay Area, building a range of styles and requirements, but all our projects share the same level of dedication, detail, and communication. Our Project Engineer will ensure that our clients receive the best possible service, while continuing to build their experience in project management. Responsibilities: Assist with document control including RFI's, submittals, subcontractor bids and documentation, change orders, schedule updates, drawings, and meeting minutes. Ensure projects and subcontractors are properly set up in Sage and Procore. Coordinate with Superintendent to ensure daily logs, photo documentation, and required postings are correct and up to date. Interface with City and County government in relation to permits, parking, and inspections. Coordinate on site project set up, ensuring basic office supplies, safety equipment, required postings, toilets and utilities are in place for the project. Schedule, set agendas, produce documentation and logs, and take notes for project meetings. Manage and update punch list for project. Assemble close out package for clients at the end of the project, including Maintenance and Service information and schedule. Participate in weekly Maintenance and Service meeting, schedule all maintenance, and distribute service schedule to the service team. Regularly interface with clients, answering questions, keeping them up to date on their projects, and contacting them about needed maintenance and service on their completed projects. Requirements: Construction project management experience preferred Degree in a related field. Valid driver's license and reliable transportation. Ability to speak, read, and write in English. Ability to multitask and handle multiple high priority tasks. Strong written and verbal communication skills. Excellent customer service. Strong computer skills, experience with Microsoft suite, Smartsheet, and Procore. Team-oriented and willing to work with others to achieve results. Ability to work independently. Compensation This is a full-time, exempt role with a salary range of $65-85k annually. FORMA's current benefits package includes: Health, dental, and vision insurance with employer contribution. FSA and commuter benefits accounts. Employer-provided life insurance. 401k with employer matching. Potential annual bonus based on twice yearly employee review cycle. Unlimited PTO policy. Separate paid sick leave of 72 hours per year. FORMA provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training.

A leading tech company in San Jose is seeking a Physical Design Engineer to drive the implementation of design partitions for a complex SOC. This role requires collaboration with architecture and design teams and entails responsibilities such as verifying timing and physical aspects while resolving design issues. Candidates should have a basic understanding of logic gates and demonstrate strong teamwork skills, with preferred experience in Verilog and VHDL. Join us to innovate and influence the future of technology. #J-18808-Ljbffr

A leading semiconductor company in San Jose seeks a Senior Engineer in Product Engineering to manage new product introductions and production support. Candidates should have a Master's degree in Electrical Engineering and two years of relevant experience. Responsibilities include interfacing with manufacturing, conducting failure analyses, and implementing process improvements. This role offers competitive pay and benefits, including healthcare coverage and a performance-based bonus. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow - from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities:*** Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII.* Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies.* Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met.* Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention.* Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness.* Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.* Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$127,400 - $184,400 USD**We use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience in:* Hands-on digital/SoC physical design (synthesis through P&R and sign-off).* Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation.* Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement.* Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution.* Power/IR analysis, signal/power integrity reporting, and corrective action planning.* Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams.**Preferred Qualifications:*** Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows.* Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration.* Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows.* Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure.* Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations.* Experience mentoring or leading small physical design sub-teams or owning major P&R blocks.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

Seeking a top-tier Project Engineer for high-end residential construction. Are you looking for a challenge and opportunity to grow? Are you interested in working on architecturally-driven, high-end residential projects throughout Northern California? FORMA Construction, an award-winning firm, seeks a motivated, detail-oriented Project Engineer to help our clients build their dream homes. The Project Engineer role is a critical hub for FORMA. In coordination with the Project Manager and the Superintendent; the PE works closely with clients, architects, designers, subcontractors, and other vendors. The PE tracks progress and updates budgets while keeping the project well-documented and running smoothly ensuring that our clients are informed and consulted every step of the way. Success in this role is measured by your ability to maintain project documents like RFI's and Submittals among other tasks within Procore while maintaining good relations with our clients, vendors, and other stakeholders. At FORMA, our Mission is the continual development of our people and processes to create lasting relationships built on integrity, partnership, and craft. Our core values are based on Urgency, Ownership, Communication and Craft. FORMA's clients and work sites take us throughout the greater Bay Area, building a range of styles and requirements, but all our projects share the same level of dedication, detail, and communication. Our Project Engineer will ensure that our clients receive the best possible service, while continuing to build their experience in project management. Responsibilities: Assist with document control including RFI's, submittals, subcontractor bids and documentation, change orders, schedule updates, drawings, and meeting minutes. Ensure projects and subcontractors are properly set up in Sage and Procore. Coordinate with Superintendent to ensure daily logs, photo documentation, and required postings are correct and up to date. Interface with City and County government in relation to permits, parking, and inspections. Coordinate on site project set up, ensuring basic office supplies, safety equipment, required postings, toilets and utilities are in place for the project. Schedule, set agendas, produce documentation and logs, and take notes for project meetings. Manage and update punch list for project. Assemble close out package for clients at the end of the project, including Maintenance and Service information and schedule. Participate in weekly Maintenance and Service meeting, schedule all maintenance, and distribute service schedule to the service team. Regularly interface with clients, answering questions, keeping them up to date on their projects, and contacting them about needed maintenance and service on their completed projects. Requirements: Construction project management experience preferred Degree in a related field. Valid driver's license and reliable transportation. Ability to speak, read, and write in English. Ability to multitask and handle multiple high priority tasks. Strong written and verbal communication skills. Excellent customer service. Strong computer skills, experience with Microsoft suite, Smartsheet, and Procore. Team-oriented and willing to work with others to achieve results. Ability to work independently. Compensation This is a full-time, exempt role with a salary range of $65-85k annually. FORMA's current benefits package includes: Health, dental, and vision insurance with employer contribution. FSA and commuter benefits accounts. Employer-provided life insurance. 401k with employer matching. Potential annual bonus based on twice yearly employee review cycle. Unlimited PTO policy. Separate paid sick leave of 72 hours per year. FORMA provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training.

A leading tech firm is seeking a recent graduate or final-year PhD/Master's student for a role focused on advancing NLP research within their Language AI features. Responsibilities include conducting rigorous research, collaborating with product managers, and innovating in AI solutions. Ideal candidates will have a strong background in machine learning and natural language processing, and experience with Python. This position is located in San Jose, California, and offers a competitive salary package. #J-18808-Ljbffr

Altera .Senior OSAT Engineer page is loaded## Senior OSAT Engineerlocations: San Jose, California, United Statestime type: Full timeposted on: Posted Yesterdayjob requisition id: R01840# **Job Details:**### ## **Job Description:****About Altera**Altera is a global leader in FPGA and programmable logic solutions, enabling innovation in data center, communications, automotive, aerospace, and industrial markets. As we expand manufacturing capabilities for next-generation programmable devices, we are strengthening our OSAT engineering organization to deliver world-class backend manufacturing performance.**Role Summary**We are seeking a highly skilled **Senior OSAT Engineer** to drive outsourced assembly and test engineering activities across Altera's global supplier network. You will lead NPI readiness, yield optimization, cost improvements, and qualification activity for packaging and test flows supporting Altera's FPGA/SoC product lineup. This role requires strong semiconductor backend engineering experience, hands-on problem solving, and the ability to collaborate closely with OSAT partners and cross-functional stakeholders.**Key Responsibilities*** Lead technical engagement with OSAT suppliers on assembly and test process development, yield ramp, quality improvement, and volume manufacturing readiness.* Drive new product introduction (NPI) from engineering builds through production release, ensuring OSAT capability meets electrical/thermal/mechanical requirements for FPGA and SoC products.* Optimize packaging and test architectures for performance, cost, and reliability: flip-chip BGA, high-pin-count packages, substrate technologies, wafer-level solutions, burn-in/FT coverage.* Monitor and improve backend yield performance using data-driven analysis; identify systemic issues and lead root cause / corrective actions.* Partner with Test Engineering, Packaging, Product Engineering, DFM, and Quality teams on process optimization, failure analysis, and manufacturability improvements.* Implement and maintain process control systems, SPC methodologies, automation improvements, and lean manufacturing principles at OSAT.* Support cost reduction initiatives including BOM optimization, process simplification, and cycle time improvements.* Track supplier performance metrics (yield, DPPM, cost, cycle time, OEE) and provide updates with risk assessments and mitigation plans.* Lead or support reliability testing and package qualification activities aligned to industry standards (JEDEC, IPC, AEC-Q).* Maintain strong technical relationship and communication cadence with OSAT partners to ensure transparency, collaboration, and escalation management.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$159,700 - $231,000 USD**We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.### ## **Qualifications:****Minimum Requirements*** Bachelor's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.* 10+ years of semiconductor assembly, packaging, or test engineering experience.* Hands-on experience with OSAT manufacturing environments, including wafer finishing, substrate attach, interconnect packaging, test, and burn-in.* Strong technical understanding of backend manufacturing flows: flip-chip, wire bond, underfill, molding, final test, reliability stress and analysis.* Proven ability to analyze yield, reliability, and cost data to drive engineering decisions and improvements.* Demonstrated success working with international suppliers and cross-functional teams.* Strong written and verbal communication skills, including technical reporting and supplier engagement.******Preferred Qualifications*** FPGA, ASIC, or SoC backend experience, particularly high-pin-count or high-power devices.* Experience in automotive or high-reliability product qualifications (AEC-Q / ISO standards).* Familiarity with advanced packaging: 2.5D/3D, fan-out WLP, heterogeneous integration.* Knowledge of supply chain risk mitigation, dual sourcing, and volume scaling strategies.* Experience with automation, traceability systems, and smart factory/manufacturing analytics.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr