Senior mechanical engineer jobs in Santa Cruz, CA - 3,808 jobs

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

About Commonwealth Fusion Systems: Commonwealth Fusion Systems is on a mission to deliver the urgent transition to fusion energy. Combining decades of research, top talent, and new technologies, we're designing and building commercially viable fusion power plants. And working with policymakers and suppliers to build the energy industry of the future. We're in the best position to make it happen. Since 2018, we've raised nearly $3 billion in capital, making us the largest and leading private fusion company in the world. Now we're looking for more thinkers, doers, builders, and makers to join us. People who'll bring new perspectives, solve tough problems, and thrive as part of a team. If that's you and this role fits, we want to hear from you. Principal Mechanical Engineer We're looking for a Principal Mechanical Engineer to join our R&D and equipment design team to help build the next generation of thin‑film deposition technology. The Principal Mechanical Engineer will be responsible for the design and implementation of advanced R&D equipment and complex machinery. This role requires strong technical expertise, procedural discipline, and the ability to collaborate across engineering and technology functions to ensure safe, reliable, and high‑performance equipment. If you enjoy working on complex design problems, mentoring others, and solving problems in a collaborative, fast‑paced environment, this is your opportunity to make an impact. What you'll do: Lead the design and implementation of advanced R&D equipment for thin‑film processing, including ownership of key mechanical modules and sub‑systems Define system level requirements and drive innovative design concepts to meet these requirements Lead design reviews for overall mechanical system and key mechanical subsystems Generate and maintain interfaces with other engineering subsystems Report on and be accountable for project progress to stakeholders Work effectively within a multi‑disciplinary team of top scientists and engineers Mentor engineering staff for effectiveness and delivery of on‑time & in‑spec outcomes Get things done: drive projects, consistently deliver, act with speed What we're looking for: Master's degree in Mechanical Engineering or related field (or equivalent industrial experience) 15+ years of experience with at least 7 years of experience working as a principal mechanical design engineer or engineering team lead in a relevant context: design and implementation of R&D systems and manufacturing equipment Ability to conceive of novel solutions for complex engineering systems in challenging environments Expertise with 3D modeling; preferred experience with SolidWorks and NX Experience with COMSOL, ANSYS or other FEA tools Ability to select and qualify vendors for components or subsystems Demonstrated ability to lead in either direct or matrix structures Strong verbal and written communication skills and a dedication to high‑quality documentation Bonus points for: Ph.D. in Mechanical Engineering or related field (or equivalent industrial experience) Prior success building first‑of‑kind or experimental tools for material science or semiconductor R&D Familiarity in applying Semi‑S8, ASME, ACI, ASTM, and other mechanical standards to design solutions Experience with the operation of equipment in a manufacturing environment Must‑have Requirements: Ability to occasionally lift up to 50 lbs Perform activities such as stooping, climbing, standing, or sitting for extended periods of time Dedication to safety to mitigate industrial hazards that may include heat, cold, noise, fumes, strong magnets, lead (Pb), high voltage, and cryogenics Willingness to travel or work required nights/weekends/on‑call occasionally $150,000 - $225,000 a year Benefits Competitive compensation with equity 12.5 Company‑wide Holidays Flexible vacation days 10 sick days Generous parental leave policy Health, dental, and vision insurance 401(k) with employer matching Professional growth opportunities Team‑building activities #LI‑Onsite At CFS, we excel in fast‑paced environments, driven by our values of integrity, execution, impact, and self‑critique. As we grow, we're eager to bring on mission‑driven folks who offer diverse perspectives and fresh ways to tackle challenges. We value diversity deeply and are proud to be an equal opportunity employer by choice. We consider all qualified applicants equally, regardless of race, color, national origin, ancestry, citizenship status, protected veteran status, religion, physical or mental disability, marital status, sex, sexual orientation, gender identity or expression, age, or any other basis protected by law. This role requires compliance with U.S. laws concerning the export of controlled or protected technologies or information (collectively, “Export Control Laws #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

Mizuho OSI is the leader in the markets for specialty surgery and patient positioning. The company's portfolio includes specialty surgical tables for procedure‑specific approaches that improve patient outcomes in spine and orthopedic surgeries along with disposable and reusable surgical patient care products. Job Summary The Mechanical Engineer designs operating room equipment including patient support structures, electromechanical, pneumatic, hydraulic actuators, and accessories. Contributes to product innovation via out of box thinking and drive product concepts to production. Maintains current knowledge of competitive technologies including medical, technical, manufacturing, and materials developments as related to company products. Maintains complete, accurate, and timely design history documentation, including testing methods. We are looking for you, if you have the ability to: Design metal, plastic, and carbon composite patient support structures for use in operating rooms meeting requirements for stiffness, strength, stability, reliability and cost. Design user actuated mechanisms and electro‑mechanical drive trains to articulate these structures to optimize patient positioning, surgical access, and applied traction. Work with a diverse group of motivated individuals within the mechanical engineering team as well as peers in other R&D, manufacturing, clinical, marketing, and service teams. Responsibilities Work independently or within cross‑functional development teams to design, develop, and test products that meet system specifications. Participate with New Product Introduction (NPI) to assure product designs are optimized for manufacturing. Evaluate field input from Service and Marketing regarding product performance. Maintain a continuing liaison relationship with Manufacturing and Marketing functions to meet and improve product needs. Continually contribute to product improvement and cost reduction. Participate in vendor selection, sustaining engineering, QC inspection, and material review board activities. Assist other engineers and designers with technical input and lead projects as necessary. Clear verbal and written communication skills. Understand, follow and support Mizuho OSI's internal Quality System policies, procedures and work instructions including but not limited to applicable external regulations (21 Code of Federal Regulations Part 820 Quality System Regulations and applicable International Standards). Qualifications & Requirements Bachelor's Degree in Mechanical Engineering; and 5‑8 years of design experience with emphasis on product design. Fluency with CAD software, preferably Solidworks. Ability to apply engineering principles to define and solve problems, collect data, establish facts, and draw valid conclusions. Ability to create and innovate solutions for design of mechanical parts and assemblies. Excellent written and verbal communication skills. Familiarity with electromechanical design including motor selection, couplings, bearings, gearbox design, drivetrain integration, sensor integration, and electronics packaging. Familiarity with structure design via hand calculations and using software. Familiarity with mechanism design including cams, linkages, actuators, mechanical attachments, and jigs and fixtures. Familiarity with design of mechanical user interfaces such as adjustment devices and touch points. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. Salary range: $124,000- $142,000 DOE + annual potential bonus + comprehensive benefits package EOE STATEMENT Mizuho OSI is an Equal Opportunity Employer and makes business decisions based on job related criteria only. Company policy prohibits unlawful discrimination based on race, color, religious creed, gender, religion, marital status, registered domestic partner status, age, national origin or ancestry, physical or mental disability, medical condition including genetic characteristics, sexual orientation, sexual identity, or any other consideration made unlawful by federal, state or local laws. Mizuho OSI conducts criminal conviction background checks and drug screening through a third‑party screening vendor which includes searches of address history, criminal convictions, court records, education verification, employment verification and reference checks. In addition, depending on the nature of the position for which you are applying, a motor vehicle driving report, a credit report, and/or ID checks in other non‑U.S. countries are also included. Criminal conviction background checks will run after an applicant has received and accepted a conditional offer of employment. After a conditional offer is made and before any background check is performed, applicants will receive background check disclosure and consent forms under state and federal laws, such as the Fair Credit Reporting Act and the Investigative Consumer Reporting Agencies Act. Existence of a criminal record is not an automatic bar to employment. An assessment will be made about whether the conviction has a direct and adverse relationship to the job in question. No job offer will be withdrawn, and no adverse action will be taken against any employee, based on the results of a criminal conviction background check, without an individualized assessment of whether the applicant's conviction history has direct and adverse relationship with the specific duties of the job in question. Top Reasons To Join The Mizuho OSI Team Privately held company with a tradition of market leadership and best‑in‑class innovation Fast‑paced entrepreneurial culture focused on dramatically improving patient outcomes through personal empowerment Emphasis on continuous improvement and celebration of our values of R.E.S.P.E.C.T. and the Mizuho OSI Way. Create innovative solutions designed and manufactured at our HQ in Northern California The Mizuho OSI Way We commit to your satisfaction. If you are dissatisfied, we will strive to make it right. We do things the right way. We commit to hire people with competence, generosity and a caring attitude. We motivate our employees to use their individual strengths to provide creative solutions, changes, and innovations. We anticipate your needs through customer experiences, thus nurturing our relationships. Dare to go further. Care to do more. BENEFITS At Mizuho OSI, we believe better solutions and decisions are born of diversity and are proudly an EEO/AA employer. We offer a comprehensive benefits package that includes: medical, dental, vision, life insurance, 401k with matching, educational assistance and more. FOR OUR SERVICE MEMBERS AND VETERANS Mizuho OSI values the service Veterans and their family members have given to our country and we support the hiring of returning Service Members and military spouses. If you are a Veteran or wounded warrior and would like assistance with the employment process at Mizuho OSI, please contact HR at **************. FOR PERSONS WITH DISABILITIES If you are a person with a disability or a disabled Veteran and are applying for a job with Mizuho OSI, we would like to ensure your application process goes as smoothly as possible. If you need additional assistance, information or answers to your questions, feel free to contact HR at **************. #J-18808-Ljbffr

Physical Design Engineer - New College Grad 2026 page is loaded## Physical Design Engineer - New College Grad 2026locations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR2009983We are now looking for a Physical Design Engineer!NVIDIA has continuously pioneered and reinvented itself over two decades through various avenues of computing: Graphics, High Performance Computing, Artificial Intelligence, Research, and more. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can solve, and that matter to the world. This is our life's work, to amplify human creativity, intelligence, and technology. Today, visual computing is becoming increasingly central to how people interact with technology, and there has never been a more exciting time to join our team. We are looking for a Physical Design Engineer who will be responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets, and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets.**What you will be doing:*** As a member of the team, you will participate in the efforts in establishing CAD and physical design methodologies (flow and tools development) as well as implementation.* Your day to day will include developing chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects.* This position requires you to work with EDA vendor (Synopsys, Cadence, Mentor, etc.) tool suites such as: ICC2,PrimeTime, dc\_shell, Innovus, SeaHawk.* You will interact with a diverse team engineers.**What we need to see:*** Completing an BSEE, MSEE or PhD (or equivalent experience).* Deep understanding of VLSI and Physical Design related basics & concepts.* Possess a deep understanding of static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis.* Experience in scripting and programming using several of the following languages/tools: Perl, C, C++, TCL, Scheme, Skill, or Make.* Previous internship or project experience in physical design implementation With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a passion for technology, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 96,000 USD - 161,000 USD for Level 1, and 108,000 USD - 184,000 USD for Level 2.You will also be eligible for equity and .Applications for this job will be accepted at least until December 19, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**For decades, Altera has been at the forefront of programmable logic technology. Our commitment to innovation has empowered countless customers to create groundbreaking solutions that have transformed industries.Join us in our journey to becoming the world's #1 FPGA company!Altera is seeking a **Senior Design Automation Engineer** to join our Design Methodology Automation and Infrastructure Team.The Design Methodology Automation and Infrastructure Team is responsible for building and maintaining the core automation infrastructure that supports Altera's FPGA design flows-from RTL to GDSII. In this senior role, you will drive the architecture, development, and optimization of highly automated, reliable, and scalable flow systems that enhance design productivity and accelerate development cycles for next-generation FPGA products. You will influence technical direction, mentor junior engineers, and collaborate closely with cross-functional teams to deliver world-class automation solutions.**Key Responsibilities:*** Architect next-generation unified FPGA/SoC design methodologies spanning Front-End, handoff to Backend, Design Verification, Design-For-Test (DFT), Design Data Management/Release flows, and FPGA-specific flows such as Design Intent and Configuration Management.* Develop and integrate state-of-the-art EDA solutions, including ML/AI-enhanced tools, flows, and methodologies-sourced externally or developed internally-to create sustainable, scalable automation solutions for multiple chip design programs.* Collaborate with design automation technical leads, design domain leads, and domain managers to define and drive new design automation architectures from concept through full production deployment across upcoming product programs.* Partner with EDA vendors to evaluate, explore, and extend tool capabilities that improve design quality, shorten turn-around time, and enhance design optimization.* Architect, develop, deploy, and maintain advanced design automation flows and methodologies for digital and/or analog design at scale.* Lead evaluation, integration, and enhancement of EDA tools, driving improvements in design productivity, efficiency, and quality across multiple design teams.* Design and implement robust automation frameworks that reduce manual effort, increase reproducibility, and improve overall design throughput.* Identify workflow bottlenecks across design, verification, CAD, and methodology teams and lead cross-functional initiatives to streamline FPGA design execution.* Provide deep technical expertise in scripting, tool customization, and flow development for advanced semiconductor design needs.* Drive continuous innovation in design automation infrastructure through adoption of new methodologies, technologies, and optimizations.* Collaborate with internal and external EDA vendors, owning issue resolution, feature requests, and deployment of next-generation capabilities.* Mentor and provide technical leadership to junior engineers within the Design Automation organization.#LI-MD1**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.$142,600 - $206,500 USDWe use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's or Master's in Computer Science, Electrical Engineering, or equivalent, with a minimum of 10 years of experience in IC Design or Design Automation and experience in the following:* Extensive experience with industry-standard EDA tools and hands-on expertise in design methodologies across multiple domains, such as Front-End Logic Design flows, Design Intent and FPGA-specific flows, Design Verification flows, and Design-for-Test (DFT) flows (with Back-End flow knowledge considered a plus).* Strong programming skills in Python, Tcl, C-shell, C, C++, or similar languages.* Familiarity with ML/AI applications and algorithms and their use in EDA or design methodology optimizations.* Proven leadership skills for driving collaborative, cross-functional projects, with strong communication and influencing abilities### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

An automotive giant is seeking a Staff ML Engineer for their ML Compute Platform to scale backend services and contribute to AI infrastructure. Responsibilities include designing software components, improving system efficiency, and leading initiatives. Candidates should have 7+ years of experience and expertise in languages like Go, C++, or Python, as well as a solid background in distributed systems. Join a team that's transforming mobility and tackling complex engineering challenges with AI applications. #J-18808-Ljbffr

A leading technology firm in California is looking for an experienced Staff Machine Learning Engineer. In this role, you will drive the technical direction of machine learning technology, design and build impactful solutions, and lead cross-team initiatives. The ideal candidate has extensive experience in machine learning and is skilled in collaboration and mentorship. This position offers competitive compensation with equity options and emphasizes a diverse and inclusive workplace. #J-18808-Ljbffr

A leading technology company is seeking a Staff Machine Learning Engineer based in Mountain View, CA. In this pivotal role, you will develop and deploy advanced machine learning models to address challenges in today's complex electric grid. You will lead model building efforts, mentor junior engineers, and collaborate on cross-functional projects. Ideal candidates have over 10 years of experience in machine learning, strong Python skills, and familiarity with ML frameworks like PyTorch and TensorFlow. Join us and make a significant impact on the energy future. #J-18808-Ljbffr

About us: FLINT focuses on the design-build and design-assist delivery methods, producing the highest quality of projects and yielding the greatest value to our clients. Our employees and industry partners are truly some of the best people you will ever work with. FLINT is built on values, ethics, quality design, and exceptional construction. Our “master builder” approach to design and construction is the hallmark of our firm. FLINT is honored to be selected as the General Contractor of the Year by the Associated Subcontractors Alliance of Sacramento for five consecutive years. One of the key attributes to the success of FLINT is the employment and retention of highly talented individuals. From this, FLINT has established itself as one of the preeminent Design-Builders in the western region. Our relationships and experiences have shaped our purpose: to create an extraordinary building experience through collaboration with passionate professionals. Who we are seeking: » 3+ years of experience, capable of performing project management functions on small projects ($2-$5M) with minor Project Management oversight. Essential job functions: » Manage overall project administration and ensure compliance with all project requirements. » Engage with architects and owners for business development. » Draft and review subcontracts and purchase orders to ensure the scope of work is accurately defined. » Review project documents and familiarize with project participants. » Determine submittal requirements and maintain the submittal log. » Develop and maintain overall project schedules and short-term schedules. » Conduct regular site visits to ensure proper construction and adherence to schedule. » Obtain necessary permits and ensure timely receipt of recorded documents. » Strong grasp of construction terminology and activities. » Basic understanding of all trades including MEP and building permit process. » Ability to estimate CORs, assist in bidding, and assemble project estimates. » Proficiency in cost control types and delivery methods. » Skills in project documentation, scheduling, safety practices, and technology tools (Fieldview, Viewpoint, Team VPT1, Bluebeam, Pype, GCPay, P6, and Vista). » Business development skills with the ability to maintain customer relations. » Understanding of fee enhancement, risk mitigation, and client management. » Ability to mentor team members and promote teamwork and cooperation.

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

At Apple, we believe our products begin with our people. By hiring a diverse team, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our collaborative process, we build memorable experiences for our customers! These elements come together to make Apple an amazing environment for motivated people to do the greatest work of their lives. You will become part of a hands-on development team that sets the standard in cultivating excellence, creativity and innovation. Come help us design the next generation of revolutionary Apple products. We are looking for a forward-thinking and talented engineer. As a member of our team, you will have the opportunity to craft and implement methodologies with high impact on upcoming products that will delight millions of Apple's customers. In this role, you will be involved in our physical design machine learning efforts, collaborating with internal teams, and using your expertise to ensure that our SOCs achieve optimal Power, Performance, and Area (PPA). Description As part of the physical design machine learning architecture team, you will work on building efficient application processors for Apple products. Your experience in physical design and machine learning will help solve complex problems across RTL design, logic synthesis, floor planning, power/clock distribution, place and route, timing/noise analysis, power/thermal analysis, voltage drop analysis, and manufacturing/yield considerations. You will collaborate with design, power, post silicon, CAD, software, and machine learning teams in a dynamic environment. Minimum Qualifications Bachelor's degree and 3+ years of relevant industry experience. Understanding of optimization algorithms, data structures, and linear algebra. Knowledge of VLSI fundamentals, including physical design. Preferred Qualifications Experience with advanced machine learning algorithms like GNNs, VAEs, transformers, diffusion models, LLMs. Programming skills in Python and C/C++. Master's or PhD with relevant publications in Machine Learning or EDA algorithms. Strong communication and organizational skills. At Apple, compensation includes base pay within a range depending on skills and experience, along with stock programs, benefits, and educational reimbursement. The role may also be eligible for bonuses, commissions, or relocation support. Apple is an equal opportunity employer committed to diversity and inclusion. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. #J-18808-Ljbffr

A leading fusion energy company in Milpitas is seeking a Principal Mechanical Engineer to join their R&D team focused on advanced thin-film deposition technology. Responsibilities include designing R&D equipment, leading complex projects, and mentoring engineering staff. The ideal candidate will have a Master's in Mechanical Engineering, over 15 years of experience in mechanical design, and familiarity with tools such as SolidWorks and ANSYS. Competitive salary and benefits are offered, including 12.5 holidays and flexible vacation days. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. Drive PPA optimization and ensure scalability across roadmap and custom devices. Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. Analyze trade-offs for performance, power, reliability, and manufacturability. Influence strategies for security, safety, and reliability across CPF domains. Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. Experience with low-power design techniques, boot/reset flows, and power management. Knowledge of design methodologies, advanced process technologies, and associated challenges. Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS BS or MS or PhD in Electrical/Computer Engineering or related field. Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

Altera .# **Job Details:**### ## **Job Description:****About the Role:**As a Physical Design Engineer at Altera, you will play a critical role in the backend implementation flow - from RTL/netlist through GDSII/tape-out for FPGA/SoC devices. You will collaborate with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve performance, power, and area (PPA) goals, with a particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).**Key Responsibilities:*** Execute physical design implementation tasks (floorplanning, power planning, placement, clock tree synthesis (CTS), routing, engineering change orders (ECO), extraction, sign-off preparation) from netlist to GDSII.* Apply PPA optimization techniques (performance/timing closure, power reduction, area efficiency) across block-level and full-chip hierarchies.* Collaborate with front-end design, architecture, and CAD/EDA tool teams to ensure physical design constraints, timing budgets, power budgets, and DFT insertions are met.* Develop and enhance physical design flows, methodologies, scripts, and automation frameworks (TCL, Python, Perl) to accelerate turnaround, improve QoR, and reduce manual intervention.* Participate in timing, power, EM/IR integrity, signal/power noise, and DRC/LVS/ERC verification for sign-off readiness.* Integrate FPGA-specific physical design aspects: configurable logic block placement, fabric routing, I/O ring optimization, power domains for programmable regulation, and yield optimization.* Debug physical design issues and interact with CAD tool vendors and internal tool teams to drive tool enhancements or workarounds.**Salary Range**The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.**$127,400 - $184,400 USD**We use artificial intelligence to screen, assess, or select applicants for the position.### ## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 6+ years of experience in:* Hands-on digital/SoC physical design (synthesis through P&R and sign-off).* Industry-standard EDA tools (e.g., Synopsys IC Compiler/Fusion, Cadence Innovus/Encounter, PrimeTime, STAR-RCX, Calibre) for high-speed digital ASIC/SoC implementation.* Scripting/programming (TCL, Python, Perl, shell) for flow automation and productivity enhancement.* Physical design flow: floorplanning, CTS, placement, routing, power domain gating, clock domain crossing, multi-power domain design, timing closure, ECOs, and DRC/LVS/DFM resolution.* Power/IR analysis, signal/power integrity reporting, and corrective action planning.* Interfacing with front-end teams (RTL, architecture), CAD/EDA tool teams, and manufacturing/packaging teams.**Preferred Qualifications:*** Experience with advanced process nodes (7nm, 5nm or smaller) or FPGA/programmable logic device flows.* Familiarity with FPGA architecture: routing fabrics, programmable logic blocks (PLBs), on-chip networks, I/O rings, static/dynamic reconfiguration.* Expertise in low-power design methodologies, power grid design, power gating, multi-voltage domain implementation, and power sign-off flows.* Prior exposure to full-chip integration flows (block-to-chip convergence) and high-frequency (1 GHz+) timing closure.* Experience in high-volume manufacturing environments, including yield and DFM/DFY considerations.* Experience mentoring or leading small physical design sub-teams or owning major P&R blocks.### ## **Job Type:**Regular### ## **Shift:**Shift 1 (United States of America)### ## **Primary Location:**San Jose, California, United States### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr

A leading technology company in San Jose is seeking a skilled engineer to develop applications based on generative AI models such as GPT-4. This role involves collaborating with cross-functional teams to optimize performance and ensure reliability, as well as engaging in cutting-edge AI developments. The ideal candidate will have a Bachelor's or Master's degree in a relevant field and deep knowledge of machine learning methodologies. Competitive compensation, benefits, and opportunities for growth will be offered. #J-18808-Ljbffr

A leading technology company in San Jose, California is seeking a Physical Design Engineer to play a critical role in backend implementation for FPGA/SoC devices. You will be responsible for tasks such as floorplanning, PPA optimization, and collaboration with diverse teams. The ideal candidate will have a Bachelor's degree in Electrical Engineering and over 6 years of hands-on experience. Join us to help develop innovative technology solutions. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a recent graduate or PhD candidate for an AI/ML development role. The position requires backend development skills in Go or Python and understanding of LLM infrastructure. Candidates should be ready to collaborate with cross-functional teams, optimizing models for real-world deployment. This role offers competitive salary ranges based on location, benefiting from Cisco's extensive employee perks and growth opportunities. #J-18808-Ljbffr