Principal Design Engineer jobs at BAE Systems - 9411 jobs

Principal, Design Engineering - Signal Integrity Celestica Engineering is seeking a highly motivated and self-driven candidate qualified for the position of Signal Integrity Engineer to help design and build market leading Hardware Platform Solutions. The Signal Integrity Engineer will play a critical role as the subject matter expert in the planning of digital PCB designs, simulation, lab verification, and troubleshooting signal integrity issues on completed designs. They will also be expected to help with design review of critical PCBs for signal integrity concerns. Good communications skills and ability to work with physically dispersed teams is a strong requirement. Responsibilities Define and Develop next generation technologies for Networking, server and storage products. Provide innovative solutions to unusually complex and sensitive problems requiring ingenuity and creativity. Serve as technical consultant and technical leader for their team. Engage with customers and suppliers on product roadmaps and support. Communicate progress toward projects and program goals. Strong ability to lead, motivate and direct a workgroup. Proficiency in hardware systems environments and detail oriented. Strong organizational skills. Cross-Functional capabilities. PCB design fundamentals (single ended and differential signals). Signal loss • Impedance control • Crosstalk (near end and far end). Experienced with single-ended and differential signaling up to 50Gbps. Experienced working with component models (touchstone files) and cascading models to generate complete system models for simulation. Simulation of digital interfaces (FPGA to DRAM, SERDES interfaces). Simulation of analog paths through a combination of PCB, connector, and cable (signal driver to DUT). Proficient with 2D and 3D simulation tools (examples include ADS, ANSYS HFSS, Sigrity). Electrical length calculations for signal matching. Familiar with looking at signals in both frequency (S-parameter) and time domain and understand how to interpret results when it comes to suitability for a particular application. Very familiar with generating and interpreting data-eye diagrams up to 50Gbps: NRZ and PAM4. Proficient with Allegro or similar layout tool and schematics. PCB Stack up design and familiar with fabrication limitations and cost trade-offs. High Frequency board material experience. Significant experience with measuring signal performance in the lab: TDR measurements and VNA measurements. Able to develop test fixtures for making measurements (both custom design test boards as well as making “ad hoc” probing solutions to troubleshoot existing PCBs). Expert in cost vs performance tradeoffs when designing signal paths as cost is a key design constraint. Experience with flex circuit design for high speed signaling. QualificationsTypical Experience 12+ years experience with High Speed Signal Delivery Design and Evaluation. This includes both signal integrity within a PCB and off the board (board to board connectors, ribbon cables, coaxial cable, etc.). Typical Education Bachelor's degree in Electrical Engineering, Master's is preferred $200,000- $351,000 The salary range described in this posting is an estimate by the Company, and may change based on several factors, including but not limited to a change in the duties covered by the job posting, or the credentials, experience or geographic jurisdiction of the successful candidate. Notes This job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time. Celestica is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, pregnancy, genetic information, disability, status as a protected veteran, or any other protected category under applicable federal, state, and local laws. This policy applies to hiring, promotion, discharge, pay, fringe benefits, job training, classification, referral and other aspects of employment and also states that retaliation against a person who files a charge of discrimination, participates in a discrimination proceeding, or otherwise opposes an unlawful employment practice will not be tolerated. All information will be kept confidential according to EEO guidelines. Celestica is an E-Verify employer. COMPANY OVERVIEW: Celestica (NYSE, TSX: CLS) enables the world's best brands. Through our recognized customer-centric approach, we partner with leading companies in Aerospace and Defense, Communications, Enterprise, HealthTech, Industrial, Capital Equipment and Energy to deliver solutions for their most complex challenges. As a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development - from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud.Headquartered in Toronto, with talented teams spanning 40+ locations in 13 countries across the Americas, Europe and Asia, we imagine, develop and deliver a better future with our customers. Celestica would like to thank all applicants, however, only qualified applicants will be contacted. Celestica does not accept unsolicited resumes from recruitment agencies or fee based recruitment services. Nearest Major Market: San Jose Nearest Secondary Market: Palo Alto #J-18808-Ljbffr

Press Tab to Move to Skip to Content Link Select how often (in days) to receive an alert: Principal, Design Engineering Job Title: Principal, Design Engineering Functional Area: Engineering (ENG) Career Stream: Engineering (ENG) Role: Principal (PRI) Job Code: PRI-ENG-DSGN Job Band: 12 Direct/Indirect Indicator: Indirect Summary The Principal Engineer, Software works in cross functional teams with other designers, customers, manufacturing engineering and project leadership to ensure robust and high quality product development. Enhance designs with feedback from reviews in areas such as manufacturing, test, supply chain, reliability, industrial design and simulations. Detailed Description Performs tasks such as, but not limited to, the following: Lead the design, development and implementation of technical solutions for complex projects, involving multiple domains. Participate in project planning and scheduling. Global SME with comprehensive knowledge and industry recognition. Provides technical leadership and direction to a global team of engineers. Take responsibility for non-technical elements of an engineering project (people, financials etc.) Review and interpret customer specifications and may act as primary customer contact. Analyze trade-offs in complex systems and recommend solutions. Develops deployment strategies and plans. Lead the deployment of strategic complex programs and coordinate site-wide deployment efforts. May manage relationships with key vendors/partners Software Development: You'll be responsible for designing, developing, and testing software that runs on Compute, Networking and Storage appliances, enabling high-performance networking and computing appplications at hyperscalers. Optimize code for performance, efficiency, and low latency Innovate new ideas in conjunction with networking and compute engineers to optimize overall data center efficiency Architect solutions for customer's data center management needs working with multiple lower-level drivers, OS, libraries Hardware Integration: You'll be responsible for designing, developing, and testing software that runs on Compute, Networking and Storage appliances, enabling high-performance networking and compute applications Troubleshoot and resolve hardware-software interaction issues Performance Optimization: Analyze and optimize network performance, identifying bottlenecks and implementing solutions. Develop and implement performance testing methodologies and tools. Security: Design and implement security features for Compute, Networking and Storage appliances software, ensuring data integrity and confidentiality Stay up-to-date on security best practices and vulnerability remediation Work effectively in a team environment, collaborating with engineers and peer functional leads from different disciplines to innovate solutions, triage issues and speed execution Work with product line management, customers and sales teams to understand requirements Explain the value addition software brings to technical and non-technical audiences. Leadership: Mentor and coach team members on the technical skills and approaches to solve problems. Review and maintain quality of code going into production. Architect software applications that will work across multiple technology generations with minimal changes. Present innovation and value addition from our software in technical forums and customer interactions Project Management - Ability to manage/lead complex, multiple line engineering projects that may also involve other functions. Demonstrate solid understanding of the technical, financial and people aspects of the project. Able to create a project/change management plan and ensure that the project is delivered within the assigned time and budget. Ability to recognize project barriers and develop mitigation plans Financial Acumen / Business Planning - Ability to create financial plans for your projects, align them internally with your line of management and other functions and externally if needed. Create project plans, profitability calculations, risk and sensitivity analysis, able to recognize barriers and mitigate profitability risks. Fully knowledgeable about internal and external financial reporting, accounting and tax requirements relevant to your area of expertise. The following competencies may also be required: Coaching/Mentoring; Communication/Negotiation/Presentation; Creative Problem Solving; Customer Interaction/Stakeholder Management; Quality & Lean; Working Effectively with Others; D/PFMEA; 8D/Corrective Action; Equipment Safety; Design of Experiments (DOE). Strong programming skills: Proficiency in C, C++and other low-level programming languages. Networking knowledge:Deep understanding of networking protocols (TCP/IP, Ethernet, etc.) and concepts Operating system knowledge:Experience with Linux driver kernel development is a plus Hardware experience: Familiarity with main elements of CPU, XPU, memory, NICs, board monitoring elements is a must Debugging and testing skills:Ability to identify and resolve software and hardware issues. Problem-solving skills:Strong analytical and problem-solving abilities Experience with GPU programming: Prior experience GPU is a plus Experience with Cloud Orcherstation: Prior experience of Ansible/Terraform and understanding of cloud computing architectures and services is the plus Clear Communication: Proven ability to articulate requirements and vision to large and diverse audience through written documents like architecture specifications and verbal presentations in technical forums is required. Physical Demands Duties of this position are performed in a normal office environment. Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data. Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required. Occasional travel may be required. Typical Experience 15 to 20 years Typical Education Masters degree or consideration of an equivalent combination of education and experience. Educational Requirements may vary by Geography Salary Range The salary range described in this posting is an estimate by the Company, and may change based on several factors, including by not limited to a change in the duties covered by the job posting, or the credentials, experience or geographic jurisdiction of the successful candidate. Salary Range: $171,956 - $268,734k Annually Notes This job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran. Celestica's policy on equal employment opportunity prohibits discrimination based on race, color, creed, religion, national origin, gender, sexual orientation, gender identity, age, marital status, veteran or disability status, or other characteristics protected by law. This policy applies to hiring, promotion, discharge, pay, fringe benefits, job training, classification, referral and other aspects of employment and also states that retaliation against a person who files a charge of discrimination, participates in a discrimination proceeding, or otherwise opposes an unlawful employment practice will not be tolerated. All information will be kept confidential according to EEO guidelines. COMPANY OVERVIEW: Celestica (NYSE, TSX: CLS) enables the world's best brands. Through our recognized customer-centric approach, we partner with leading companies in Aerospace and Defense, Communications, Enterprise, HealthTech, Industrial, Capital Equipment and Energy to deliver solutions for their most complex challenges. As a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development - from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud. Headquartered in Toronto, with talented teams spanning 40+ locations in 13 countries across the Americas, Europe and Asia, we imagine, develop and deliver a better future with our customers. Celestica would like to thank all applicants, however, only qualified applicants will be contacted. Celestica does not accept unsolicited resumes from recruitment agencies or fee based recruitment services. This location is a US ITAR facility and these positions will involve the release of export controlled goods either directly to employees or through the employee's movement within the facility. As such, Celestica will require necessary information from all applicants upon an applicant's acceptance of employment to determine if any export control exemptions or licenses must be filed. Nearest Major Market: San Jose Nearest Secondary Market: Palo Alto #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an “out of the box” thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle “how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power”. Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. Consult DV engineers in describing features, outlining test plans, and closing on coverage Assist DV engineers to debug functional, performance or power test failures Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology company in Santa Clara seeks an experienced ASIC Design Engineer specializing in GPU/ML Shader Core. In this role, you will define micro-architecture, implement RTL, and collaborate with various engineering teams. Ideal candidates will have experience in micro-architecture and an undergraduate degree in Computer Engineering or Electrical Engineering. Enjoy a vibrant culture that fosters innovation and teamwork, while pushing the boundaries of next-generation computing. This role does not offer visa sponsorship. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara, CA, seeks a skilled digital design engineer. The role involves RTL design, power management features, and collaboration across teams. Candidates should have strong Verilog skills and experience in IP design. A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required. This position offers an opportunity to be part of a company that values innovation and teamwork, but it is not eligible for visa sponsorship. #J-18808-Ljbffr

A technology company in San Jose is seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs. The role requires expertise in RTL ownership, complex timing constraints, and EDA tools, alongside strong communication skills. Candidates should have a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. This is a non-remote role requiring in-person presence, and does not offer visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry‑leading technologies to market. As a key contributor, you will focus on RTL design and validation of high‑speed interfaces such as chip‑to‑chip interconnect, both on system and on package, and highly configurable multi‑protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role. THE PERSON: You have a passion for digital design. You are a team player. You have strong analytical and problem‑solving skills. You are willing to learn and ready to take ownership of problems. KEY RESPONSIBILITIES: Perform RTL design of the digital components. Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP. Help lead and mentor other engineers to achieve project goals and organizational growth. Work with a functional (design) verification team to meet coverage and quality standards. Analyze/fix lint and CDC/RDC errors of the components. Guarantee quality/timely deliverables meeting project's schedule. Help to improve and automate design process. Support post‑silicon product bring‑up/debug. PREFERRED EXPERIENCE: Strong experience in designing digital components for high performance, low power SOC/FPGA. Design of digital circuits and components using Verilog/System Verilog. Creating and maintaining of timing constraints for complex multi‑clock designs. Debugging in digital and mixed‑signal simulation environment. Power optimization of digital designs. Multi‑clock domain designs. Experience/knowledge of high‑speed SerDes/Physical layer is a plus. Logic synthesis, timing closure, logical equivalence checking and ECOs. Scripting languages such as Perl, Tcl, or Python. Collaboration with verification team. Excellent verbal and interpersonal communication skills. Excellent technical communications. Ability to produce technical documentation. Exhibit strong ownership of tasks and responsibilities. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering with relevant industry experience. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Together, we advance your career. SMTS SoC Architect THE ROLE We are seeking a SoC Architect to join our adaptive SoC Architecture team. This role is pivotal in defining and driving architecture for next‑generation Adaptive SoCs, with Processor subsystems, Interconnect, AI, GPU, video processing pipelines, and memory systems. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems. You thrive in collaborative environments and bring a system‑level mindset to solving architectural challenges. You are passionate about performance, power, and scalability, and have a strong grasp of silicon design trade‑offs. You communicate effectively across engineering disciplines and influence architectural decisions with clarity and technical rigor. KEY RESPONSIBILITIES Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC Define and optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. Drive early‑stage architectural analysis, modeling, and specification development. Contribute to architectural innovation for Adaptive SoC Use‑cases in AI, GPU, video, and IO domains. Collaborate with planning, software and hardware cross‑functional teams to develop architecture solution. Collaborate with subsystem architects to ensure cohesive integration and system‑level performance. PREFERRED EXPERIENCE Proven experience in SoC architecture with Processor, Interconnects, and Memory subsystem. Expertise in AI accelerators, GPU integration, video processing pipelines, and IO subsystems. Expertise in SoC control bus design, reset architecture, clocking, and power management techniques. Experience with modeling and automation using Python, SystemC, or equivalent. Knowledge of advanced process technologies and associated design challenges. ACADEMIC & EXPERIENCE REQUIREMENTS BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. Demonstrated success in delivering high‑performance, low‑power SoC solutions. Benefits offered are described: AMD benefits at a glance. Equal Opportunity Employment AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

Senior Principal Emulation Design Engineer page is loaded## Senior Principal Emulation Design Engineerlocations: SAN JOSEtime type: Full timeposted on: Posted Todaytime left to apply: End Date: December 31, 2026 (30+ days left to apply)job requisition id: R51946## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**We are seeking a highly skilled**Design Engineer** to join our Palladium Solutions Development team, to drive the development of full-system design verification environments. This role focuses on developing and integrating and validating high speed interface [Serdes, Chip 2 chip link] based subsystems in Emulation Platforms. Development includes Parallel and Serial models for highspeed interface circuits in analog Mixed Signal Designs and components (PHYs). Integration includes the PHY, Controller / Mac and the **Accelerable Verification IP (AVIP)** environments on **Palladium** and **Protium**. End-to-end verification flow development across a wide range of system components including custom test case developments, validating the bare-metal-driver components in emulation platforms.**Key Responsibilities:*** Lead the design and deployment of **PHY logic models** for emulation platforms including **Palladium** and **Protium**.* Develop and maintain **end-to-end verification environments**, encompassing: + **System-level models** including microcontrollers, memories, NoC (Network-on-Chip), and high-speed communication interfaces + **Test case generation** + **Interface Circuit Performance Analysis.*** Contribute to **system prototyping** for early bring-up and validation of full-system designs.* Collaborate with cross-functional teams to ensure seamless integration from **simulation to emulation**.* Optimize designs for **multi-clock domain synchronization**, **area**, and **performance**, with a focus on **accuracy vs. runtime trade-offs**.* Drive innovation in emulatable IP solutions and contribute to the evolution of verification methodologies.**Required Qualifications:*** Bachelor's or Masters degree in Electrical Engineering, Computer Engineering, or related field with 7-15 years of experience* Strong experience with system-level design and communication standards such as **PCIe, UCIe, Ethernet, UALink, DDR, USB, SPI, JTAG, AMBA protocols*** Proficiency in: + **Converting Analog Mixed Signal Designs [Parallel and Serial models] to emulation models maintaining functional and bit accuracy, enabling software stack development for configuration, control and status monitoring.** + **SystemVerilog** for synthesizable RTL design + **C and Python** for modeling, scripting, and automation + **Lab debug and test case development*** Hands-on experience with emulation platforms:* **Palladium, Protium, Zebu, HAPS, Veloci, FPGA*** Deep understanding of verification flows and emulation acceleration techniques.**Preferred Skills:*** Experience building **emulatable AVIP solutions*** Familiarity with **end-to-end verification environments**from simulation through emulation* Experience in **system prototyping and bring-up*** Strong analytical and problem-solving skills* Excellent communication and leadership abilities We're doing work that matters. Help us solve what others can't.*The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*## **We're doing work that matters. Help us solve what others can't.****Equal Employment Opportunity Policy:**Cadence is committed to equal employment opportunity throughout all levels of the organization.We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************.**Privacy Policy:**Job Applicant If you are a job seeker creating a profile using our careers website, please see the .E-Verify Cadence participates in theE-Verify program in certain U.S. locations as required by law.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr

Sr Principal Design Engineer page is loaded## Sr Principal Design Engineerlocations: SAN JOSEtime type: Full timeposted on: Posted Todayjob requisition id: R52250## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.****Specific duties include:*** Be responsible for high-performance memory IP architecture design, owning the IC micro-architecture, timing budget, power analysis platform development.* Proficiency in logic design, simulation, synthesis, STA and testing* Proficiency in Verilog/SystemVerilog and its simulation environment* Good knowledge of IC design for high-speed and low power* At least five years' experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.**Position Requirements:*** Essential Qualifications: Must have BS degree with 8+ years of applicable experience, MS degree with 6+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.* Essential that the individual demonstrates strong communication, verbal and written.* Experience on the memory IP is desired* Requires good communication skills in English.*The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*## **We're doing work that matters. Help us solve what others can't.****Equal Employment Opportunity Policy:**Cadence is committed to equal employment opportunity throughout all levels of the organization.We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************.**Privacy Policy:**Job Applicant If you are a job seeker creating a profile using our careers website, please see the .E-Verify Cadence participates in theE-Verify program in certain U.S. locations as required by law.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.Requirements;US citizenship preferred.* Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)* Should possess intimate knowledge of DFT insertion flows* Basic scan chain insertion using synthesis or other software tools* Experience in compression scan insertion, LBIST and other scan technologies* Intimate knowledge of memory build-in self-test (MBIST)* Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals* Debug and Analysis of failures to improve fault coverage* Verification of ATPG testbenches and debugging root cause of simulation mis-compares* Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687* Knowledge of timing analysis and equivalency checks would be added bonus* Ability to work in collaborative team environment* Prior experience with Cadence tools and flows is highly desirable* Should be able to finish DFT tasks independently* Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems* Ability to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External Customers* Self-driven and committed individual who can work in a fast-paced project environment## **We're doing work that matters. Help us solve what others can't.****Equal Employment Opportunity Policy:**Cadence is committed to equal employment opportunity throughout all levels of the organization.We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************.**Privacy Policy:**Job Applicant If you are a job seeker creating a profile using our careers website, please see the .E-Verify Cadence participates in theE-Verify program in certain U.S. locations as required by law.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr

A leading technology company is seeking a skilled Design Verification Engineer to focus on functional and performance verification of GPU designs in San Jose, California. This role involves developing verification plans, maintaining UVM-based environments, and collaborating with multiple teams to ensure adherence to specifications. The ideal candidate should have a Bachelor's degree and significant experience in ASIC/SoC/GPU/CPU development, particularly in verification processes. It is a 6-month onsite contract position. #J-18808-Ljbffr

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. Prodapt is seeking a highly skilled and adaptable engineer to join our dynamic team, focusing on System-on-Chip (SoC) verification. In this role, you will work on complex SoC designs and collaborate with various teams to ensure the successful development and validation of our products. Sunnyvale, CA or Austin, TX 2 year Project Responsibilities Collaborate with cross-functional teams to ensure the effective verification of complex SoC designs. UVM Expertise Develop and maintain scripts using languages like Perl, Python, Unix shells, and Makefiles to automate testing and verification processes. Gain an in-depth understanding of high-speed interfaces, including PCIe, USB, NOC, NVMe, Ethernet, LPDDR5, and HBM2, to ensure seamless integration into complex SoC designs. Collaborate with lab managers to set up and manage the necessary infrastructure for emulation and verification activities. Contribute to the development of comprehensive verification plans, testbenches, and methodologies. Identify and propose improvements to streamline the emulation and verification process. Requirements Bachelor's or higher degree in Electrical Engineering, Computer Science, or a related field. ✔8+yearsof SystemVerilog/UVMexperience (IP,sub-system,or SoClevelverification) ✔Strongscriptingskills (Python,TCL,Perl,Shell)forautomationandtooldevelopment ✔EDAtoolexpertise (VCS,Xcelium,Questa,Verdi,Spyglass,etc.) ✔Experienceindebugging,root-causeanalysis,anddrivingverificationclosure ✔FamiliaritywithCPU/GPUverification,AI/ML,Networking,ormicro-architecturalperformanceverificationisaplus ✔High-speedinterfaceverification (PCIe,DDR,HBM,Ethernet,RoCE)preferred #J-18808-Ljbffr

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services. We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our embedded services include firmware, device drivers, RTOS porting, and board bring-up. A “Great Place To Work Certified™” company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of The Jhaver Group, which employs over 32,000 people across 80+ locations globally. Prodapt is seeking a highly skilled Design Verification Engineer to focus on functional and performance verification of cutting-edge GPU designs, ensuring they meet stringent quality and specification requirements. In this role, you will develop and execute verification plans, build and maintain UVM-based environments, and collaborate closely with design and architecture teams to drive verification closure on complex GPU blocks and subsystems. 6 month contract Onsite in Austin, TX Responsibilities Develop and execute comprehensive verification plans for GPU designs, including defining verification goals, test strategies, and coverage metrics. Design, develop, and maintain verification testbenches and environments using SystemVerilog, UVM, and C++ to verify GPU functionality, performance, and power-related features. Create complex test scenarios and test cases to achieve comprehensive functional and performance coverage of GPU features and micro-architecture. Analyze simulation and regression results, debug complex GPU designs, identify root causes, and drive bug resolution in collaboration with design and architecture engineers. Work closely with cross-functional teams, including design, architecture, and software, to align verification efforts with project milestones and product requirements. Maintain accurate and up-to-date documentation for verification plans, testbenches, test cases, and results to support traceability and reviews. Requirements Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field; or equivalent practical experience. 10+ years of industry experience with a Bachelor's, 8+ years with a Master's, or 6+ years with a PhD in relevant domains of ASIC/SoC/GPU/CPU development. 5+ years of hands-on experience in GPU/CPU design verification or closely related IP/subsystem verification. Strong proficiency in SystemVerilog and UVM for block-level and/or subsystem-level verification. Experience with industry-standard verification tools and simulators (e.g., VCS, Xcelium, Questa, Verdi or similar) and coverage-driven verification flows. Proficiency with scripting languages such as Python and Perl for automation, regression management, and data analysis. Demonstrated strength in debugging, root-cause analysis, and driving verification closure in complex designs. Excellent communication and interpersonal skills, with the ability to work effectively in a collaborative, cross-functional environment. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high‑speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. Preferred Experience Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Strong understanding of state of the art of verification techniques, including assertion and metric‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. Academic Credentials BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the front-end verification team you will be part of a multi-site team to help drive successful verification execution and prove the functional correctness of the next generation of AMD/Xilinx programmable devices. THE PERSON: You have a passion for digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware and firmware engineers to understand the new features to be verified Take ownership of block level verification tasks Define test plans, test benches, and tests using System Verilog and UVM Debug RTL and Gate simulations and work with HW and SW development teams to verify fixes Review functional and code coverage metrics to meet the coverage requirements Develop and improve existing verification flows and environments PREFERRED EXPERIENCE: Strong understanding of computer architecture and logic design Knowledge of Verilog, system Verilog and UVM is a must Strong understanding of state of the art verification techniques, including assertion and constraint-random metric-driven verification Working knowledge of C/C++ and Assembly programming languages Exposure to scripting (python preferred) for post-processing and automation Experience with gate level simulation, power and reset verification ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering or a related field LOCATION: San Jose, CA #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analysed and verified system‑level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

A leading aerospace and defense company is looking for a Senior Principal Electronics Engineer - Hardware and Software Integration Lead in San Diego. This role involves leading the development of next-generation ground system solutions, managing software supplier interactions, and coordinating various engineering efforts. Candidates should have a strong background in STEM, relevant work experience, and active security clearance. The position requires on-site work but could offer hybrid options in the future. #J-18808-Ljbffr

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same. About the job you're considering Position: IC CAD Engineer - Analog Mixed-Signal Flow Automation About the Role We are seeking a skilled IC CAD Engineer to support our Analog Mixed-Signal (AMS) design teams. In this role, you will be responsible for maintaining and enhancing the CAD infrastructure, automating design flows, and supporting physical verification processes. You will collaborate closely with both analog and digital design teams, ensuring efficient and reliable design environments. Key Responsibilities Administer and maintain the CAD/EDA environment for analog and digital IC design teams. Support and enhance design flows using tools from Cadence, Synopsys, Mentor, Keysight, Ansys, and others. Develop and maintain automation scripts using Python and other scripting languages. Manage and customize physical verification tools and decks (DRC, LVS, PEX, EM/IR, ESD, etc.). Support PDK administration, including installation, regression testing, and custom PDK development (pcells, models, rule decks). Collaborate with infrastructure teams to ensure optimal performance and availability of compute resources. Provide layout and verification support to design teams across global locations. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in CAD engineering for IC design. Proficiency in Cadence Virtuoso, Calibre DRC/LVS, and other industry-standard tools. Strong scripting skills in Python, SKILL, and Perl. Solid understanding of analog and digital design flows. Experience with EMIR analysis, physical verification (DRC/LVS/PEX/ERC), and waiver handling. Strong fundamentals in software development and automation. Excellent communication skills and ability to work effectively with remote teams. Preferred Experience Hands‑on experience with tools from Keysight and Ansys. Familiarity with custom PDK development and automated regression testing. Job Description - Grade Specific Focus on Electrical, Electronics and Semiconductor. Fully competent in own area. Acts as a key contributor in a more complexor critical environment. Proactively acts to understand and anticipates client needs. Manages costs and profitability for a work area. Manages own agenda to meet agreed targets. Develop plans for projects in own area. Looks beyond the immediate problem to the wider implications. Acts as a facilitator, coach and moves teams forward. The base compensation range for this role in the posted location is: [$65,200 - $158,550 /yr] Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law. The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction. These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity. It is not typical for candidates to be hired at or near the top of the posted compensation range. In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws. Capgemini offers a comprehensive, non‑negotiable benefits package to all regular, full‑time employees. In the U.S. and Canada, available benefits are determined by local policy and eligibility and may include: Paid time off based on employee grade (A‑F), defined by policy: Vacation: 12‑25 days, depending on grade, Company paid holidays, Personal Days, Sick Leave Medical, dental, and vision coverage (or provincial healthcare coordination in Canada) Retirement savings plans (e.g., 401(k) in the U.S., RRSP in Canada) Life and disability insurance Employee assistance programs Other benefits as provided by local policy and eligibility Important Notice: Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini's discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation. Disclaimers Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law. This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact. Please be aware that Capgemini may capture your image (video or screenshot) during the interview process and that image may be used for verification, including during the hiring and onboarding process. Capgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end‑to‑end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market‑leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem. When you join Capgemini, you don't just start a new job. You become part of something bigger. We bring together passionate, skilled people, a tech‑driven approach to innovation, and a deep commitment to our clients to help organizations unlock the true value of technology. As a graduate or an experienced professional, you will be working with the world's leading brands to enhance and transform the way they do business. #J-18808-Ljbffr