Senior IC Design Verification Application Engineer
Design verification engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology. We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces year after year!
As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence's market leading verification platforms including cutting edge technologies using AI assistants, Agentic AI and machine learning. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with the account team to come up with innovative solutions to address our customers' most challenging problems in verification. You will own customer success!
In this role, you will develop customer specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence's verification tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Xcelium simulation platform and Verisium platform of AI and ML tools for enhanced verification. You will create and conduct technical presentations and product demonstrations for customers.
At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools, unlock unique expertise in verification methodologies, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement.
Key Responsibilities:
- Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support
- In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design wins
- Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions
- Understand the competitive landscape and continuously work on differentiating Cadence's solutions
- Write technical product literature such as application notes and technical articles
- Review new product proposals and device specifications
- Assume technical leadership roles in small teams as needed
Requirements:
Minimum:
BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field
5+ years experience with SystemVerilog, VHDL, Verilog
Verification skills such as UVM testbench architecture, development and debug
Strong RTL and Testbench debug skills
Experience in writing scripts (Perl, Python or Tcl)
Strong software, HDL design and verification skills
Ability to quickly analyze verification environments and design complexity
Strong verbal and written communication skills
Strong teamwork skills
Ability to interact effectively with both external customers and R&D teams
Preferred:
Experience with C/C++/SystemC
Experience in deploying VIP in testbenches
Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR
Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing
Digital design experience
The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.
Additional Jobs (*************************************************
Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization.
+ Read the policy(opens in a new tab) (********************************************************************************************************************************
We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************.
Privacy Policy:
Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (**************************************************************** .
E-Verify Cadence participates in the
E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (**************************************************************************************************************************
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Senior IC Design Verification Application Engineer
Design verification engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology. We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces year after year!
As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence's market leading verification platforms including cutting edge technologies using AI assistants, Agentic AI and machine learning. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with the account team to come up with innovative solutions to address our customers' most challenging problems in verification. You will own customer success!
In this role, you will develop customer specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence's verification tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Xcelium simulation platform and Verisium platform of AI and ML tools for enhanced verification. You will create and conduct technical presentations and product demonstrations for customers.
At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools, unlock unique expertise in verification methodologies, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement.
Key Responsibilities:
* Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support
* In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design wins
* Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions
* Understand the competitive landscape and continuously work on differentiating Cadence's solutions
* Write technical product literature such as application notes and technical articles
* Review new product proposals and device specifications
* Assume technical leadership roles in small teams as needed
Requirements:
Minimum:
BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field
5+ years experience with SystemVerilog, VHDL, Verilog
Verification skills such as UVM testbench architecture, development and debug
Strong RTL and Testbench debug skills
Experience in writing scripts (Perl, Python or Tcl)
Strong software, HDL design and verification skills
Ability to quickly analyze verification environments and design complexity
Strong verbal and written communication skills
Strong teamwork skills
Ability to interact effectively with both external customers and R&D teams
Preferred:
Experience with C/C++/SystemC
Experience in deploying VIP in testbenches
Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR
Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing
Digital design experience
The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.
Auto-ApplyLead Design Verification Engineer
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are seeking a seasoned Lead Design Verification Engineer with expertise in verifying networking chip. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead verification teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives.
THE PERSON:
We are seeking an experienced and hands-on Lead Design Verification Engineer to drive the verification strategy, methodology, and execution for our next-generation high-performance networking chip. The ideal candidate will have deep expertise in SoC/ASIC verification, strong knowledge of networking protocols and architectures, and a proven ability to lead verification teams in a fast-paced environment. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
* Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC.
* Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality.
* Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features.
* Lead and mentor a team of DV engineers - drive reviews, define milestones, and ensure high-quality deliverables.
* Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip.
* Develop and maintain automation and regression infrastructure, including CI/CD integration.
* Drive coverage closure and signoff for IP and SoC-level verification.
* Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization.
* Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
* Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
* Proven line management experience, including hiring, mentoring, and performance management of DV engineers.
* Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects.
* Experience with chip-level verification for networking ASICs, switches, or routers.
* Familiarity with traffic generators, packet-level verification, and network protocol stacks.
* Knowledge of SystemC, C testbenches, or hardware/software co-verification.
* Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce).
* Prior experience leading cross-site or multi-IP verification efforts.
* Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines.
ACADEMIC CREDENTIALS:
* Bachelor's or Master's degree in related discipline preferred
LOCATION:
Santa Clara, CA
This role is not eligible for VISA sponsorship
#LI-BW1
#LI-hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
DDR Design Verification Engineer
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are looking for an experienced Verification Engineer to join our team as a Technical Lead for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess expert-level knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl, and will have a proven track record of multiple tape-out experiences and successful verification sign-offs in a high-performance server memory environment..
THE PERSON:
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
* Technical Leadership & Project Oversight: Lead and guide a team of verification engineers in the development and execution of verification strategies for DDR5, LPDDR5, and DFI memory systems in server products.
* Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface.
* Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
* Knowledge sharing and other contributions to verification methodology
* As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests
* Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
* Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
* Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems.
* Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase.
* Provided technical leadership across multiple teams, driving cross-functional collaboration to solve complex issues in memory systems, from firmware to hardware.
* Built VIPs and BFMs for memory interfaces from scratch (preferrable)
* GLS, NLP, XPROP simulation experience is required
* Strong proficiency in system verilog assertions, constraints and coverage.
* Worked in formal verification methods, with proven record of tool usage beyond the standard apps.
* Working knowledge of DFT flows (preferrable)
* Excellent communication, management, and presentation skills.
* Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
* Bachelor's or Master's degree in related discipline preferred
LOCATION: Santa Clara, CA
#LI-SC3
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
Design Verification Engineer
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available.
We are seeking a highly skilled Formal Verification Expert to join our talented team as a Staff Engineer and technical lead. This role is crucial to ensuring IP quality through rigorous formal verification processes.
THE PERSON:
The successful candidate will play a key role in developing verification strategies, leading formal verification team, and collaborating across departments to ensure the highest quality standards.
KEY RESPONSIBILITIES:
* Lead formal verification team to ensure IP quality and project execution.
* Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc..
* Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies.
* Mentor and guide junior engineers in formal verification techniques and best practices.
* Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations.
* Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities.
PREFERRED EXPERIENCE:
* Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems.
* Proficiency in formal verification tools such as VC-Formal or JasperGoal
* Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python).
ACADEMIC CREDENTIALS:
* Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION: Santa Clara, CA
This role is not eligible for visa sponsorship
#LI-SL3
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
Design Verification Engineer
San Jose, CA jobs
Please Note:
1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
2. If you already have a Candidate Account, please Sign-In before you apply.
:
The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements.
The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification.
Job Requirements:
A Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
12+ year's relevant industry work experience.
Experience in verifying designs at system level and block level.
Fluent knowledge of RTL verification methodologies including System Verilog.
Strong experience in ASIC design verification flows and DV methodologies
Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.
Strong and independent design debugging capability.
Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members.
Demonstrated ability to analyze and resolve complex verification trade-off scenarios.
Must have legal authorization to work in the US
The candidate should have expertise in some (or preferably all) of the following areas:
Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus.
Experience working with Emulators and FPGA based prototyping is a plus.
Familiarity with overall chip design methodologies and tools
Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $141,300 - $226,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Auto-ApplySenior IC Design Verification Application Engineer
Design verification engineer job at Cadence Design Systems
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.At Cadence, we hire and develop innovators and leaders who want to make an impact on the world of technology.We offer amazing opportunities to grow, no matter where you are in your career. The ideal candidate will be energetic, innovative and enthusiastic about how to help customers solve their toughest verification problems using Cadence technology. Join our elite application engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ year after year!As an integral member of the North America Verification Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence's market leading verification platforms including cutting edge technologies using AI assistants, Agentic AI and machine learning. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with the account team to come up with innovative solutions to address our customers' most challenging problems in verification. You will own customer success!In this role, you will develop customer specific verification requirements, including advanced verification component development, methodology support, and operation and maintenance of Cadence's verification tools and services. You will support technical evaluations and benchmark development for Cadence's market leading tools such as Xcelium simulation platform and Verisium platform of AI and ML tools for enhanced verification. You will create and conduct technical presentations and product demonstrations for customers.At Cadence, customers are at the heart of everything we do. Talented engineers like you are what enable us to materialize this passion into results. By working directly with Cadence R&D and driving customer engagements, you will enhance your in-depth knowledge in verification tools, unlock unique expertise in verification methodologies, and level up your communication, customer, and sales skills. No matter where you are in your career, whether your next career step is to stay on the technical track, move up in management, or explore sales/marketing career opportunities, the skills and expertise you gain as an Application Engineer here at Cadence will put you miles ahead in your career advancement.Key Responsibilities:- Establish technical credibility and rapport with the customer and become the go-to expert for all of their technical inquiries and support- In collaboration with R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design wins- Champion the customer needs and work closely with R&D and marketing to develop competitive and creative technical solutions- Understand the competitive landscape and continuously work on differentiating Cadence's solutions- Write technical product literature such as application notes and technical articles- Review new product proposals and device specifications- Assume technical leadership roles in small teams as needed Requirements:Minimum:BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field5+ years experience with SystemVerilog, VHDL, VerilogVerification skills such as UVM testbench architecture, development and debug Strong RTL and Testbench debug skills Experience in writing scripts (Perl, Python or Tcl) Strong software, HDL design and verification skills Ability to quickly analyze verification environments and design complexity Strong verbal and written communication skills Strong teamwork skills Ability to interact effectively with both external customers and R&D teams Preferred:Experience with C/C++/SystemCExperience in deploying VIP in testbenches Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDRKnowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing Digital design experience
The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.
Auto-ApplyASIC Design Engineer, GPU/ML Shader Core
Santa Clara, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are looking for a ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you!
You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better.
THE PERSON:
You are an "out of the box" thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle "how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power". Strong interpersonal skills and an excellent teammate.
KEY RESPONSIBILITIES:
* Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations
* Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design.
* Consult DV engineers in describing features, outlining test plans, and closing on coverage
* Assist DV engineers to debug functional, performance or power test failures
* Work with Physical Design team to close on timing, area and power requirements
PREFERRED EXPERIENCE:
* Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches.
* Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
* Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required.
ACADEMIC CREDENTIALS:
* Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred.
LOCATION:
* Santa Clara CA - San Diego CA - Folsom CA
This role is not eligible for Visa sponsorship.
#LI-BM1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
ASIC Physical Design Engineer-GPU
Santa Clara, CA jobs
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
The Role:
This is a great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as Sr. Staff Engineer / Principal Member of Technical Staff.
KEY RESPONSIBILITIES:
Senior level lead engineer driving PPA improvements in both pre-silicon and post-silicon design phase
Drive cross-functional teams (technology, CAD tools, platform characterization , binning practices and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt
Improve low voltage margining methodology and design practices to improve Vmin and performance/watt for low power GFXIP
Drive design practices to improve boost frequency for GFXIP
Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high performance Graphics IP
PREFERRED EXPERIENCE:
Over 18 years' experience with BSEE/BSCS or 15+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII
Excellent analytical and problem-solving skills along with attention to details
Strong RTL analysis skills including Verilog, Timing Analysis and library understanding
Strong knowledge in design margining methodology, low voltage design, silicon - STA correlation
Hands on experience in taping out 5nm, 7nm, 14nm and/or 16nm SOC
Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
Strong communication, Time Management, and Presentation Skills
Must be a self-starter, and be able to independently and efficiently drive tasks to completion
Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player
ACADEMIC CREDENTIALS:
Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or equivalent is preferred.
#LI-PH1
Requisition Number: 181183
Country: United States State: California City: Santa Clara
Job Function: Design
Benefits offered are described here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
ASIC Physical Design Engineer
Santa Clara, CA jobs
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
ASIC Physical Design Engineer
THE ROLE:
The position will involve working with a very experienced physical design team of AMD graphics core and is responsible for delivering the physical design of blocks to meet challenging goals for frequency, power and other design requirements for AMD next generation graphics processors in a fast-paced environment on cutting edge technology.
THE PERSON:
Physical design Engineer with strong analytical thinking and problem-solving skills with excellent attention to detail. The candidates should have excellent communication skills, very good team player and ability to drive, lead and mentor team of engineers for project execution.
KEY RESPONSIBILITIES:
Physical design of complex GPU multi-millions gate design and achieve required performance, area and power targets
Work with RTL design to analyze potential bottlenecks for frequency, resolve LOL and timing issue upfront in the project cycle to achieve frequency targets
Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
Handling different PNR tools - Synopsys ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Innovus, genus
PREFERRED EXPERIENCE:
10+ years of professional experience in physical design, preferably with high performance designs.
Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
Experience in leading team of Engineers for design closure
Versatility with scripts to automate design flow.
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm
Excellent physical design and timing background.
Experience in RTL design and LOL reduction is preferred
Good understanding of computer organization/architecture is preferred.
Strong analytical/problem solving skills and pronounced attention to details.
Proficient in perl, python, tcl etc
ACADEMIC CREDENTIALS:
Bachelors or Masters in Electronics/Electrical Engineering
LOCATION:
Orlando FL, Santa Clara CA, Folsom CA, Austin TX, Boston,
#LI-PH1
Requisition Number: 176681
Country: United States State: California City: Santa Clara
Job Function: Design
Benefits offered are described here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
Staff ASIC Design Engineer - AI Engine
San Jose, CA jobs
What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team.
AMD together we advance_
Staff ASIC Design Engineer - AI Engineer- 152880
THE ROLE:
AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front-end design team of next generation AI Engine/ML processors.
THE PERSON:
You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications.
KEY RESPONISIBILITES:
In this role you will:
Define and specify micro-architecture of processor building blocks based on architecture requirements
RTL design and debug of complex blocks in Verilog / System Verilog
Analyze performance and make implementation choices to optimize timing
Analyze and optimize design for power efficiency and power integrity
Work with verification and physical design teams to achieve high quality design and successful tape out
Solve customer problems through innovative enhancements to product architecture/ micro-architecture
Design and implement underlying clocking infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory
Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms
PREFERRED EXPERIECE:
Strong experience in the following
ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
Digital design and experience with RTL design in Verilog/System Verilog
Circuit timing/STA, and practical experience with Prime Time or equivalent tools
Low power digital design and analysis
Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
Experience in following is highly desired
Understanding of FPGA architecture and implementation flow
TCL, Perl, Python scripting
Version control systems such as Perforce, ICManage or Git
Strong verbal and written communication skills
Ability to organize and present complex technical information
Fluent in working with Linux environment
Needs to be manually updated.
ACADEMIC CREDENTIALS
BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience
LOCATION:San Jose, CA
#LI-DA1
Requisition Number: 152880
Country: United States State: California City: San Jose
Job Function: Design
Benefits offered are described here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.
Staff Power Module Design Engineer
San Jose, CA jobs
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X).
Staff Power Module Design Engineer in ADI µModule Group:
(San Jose, CA, USA)
Analog Devices is committed to investing in our people and their growth. Our hiring program features high impact professional development, opportunities to drive meaningful projects that are directly tied to business goals, and unique executive exposure. Our duty is to develop the next generation of talent in our communities and provide them with a pathway to apply their academic skills in the real-world. At ADI, our hires will learn from the brightest minds who are dedicated to their growth, development, and success. From an industry perspective, incoming new career hires are surrounded by employees that represent the best of the best minds in their respective fields.
Apply now for the opportunity to grow your career and help innovate ahead of what's possible!
The ADI power module team is seeking a motivated, experienced power module staff design engineer to in our Broad Market and Industrial BU located at ADI's San Jose offices. The candidate will be working with the industry best power engineering team and working on the industry leading power module product research and development.
Responsibilities include, but not limited to:
Lead new power module product development, including product definition, feasibility, design, simulation, test, lab evaluation, qualification and release.
Collaborate with product marketing, applications teams and customers to understand applications and contribute to architectural decisions of new products.
Develop innovative techniques for advanced products and technology applications.
Identify project technical risks, define mitigating strategies, and establish milestones to ensure project success.
Enhance product development flows and qualities through advanced tools and methodologies.
Prepare and present design review documentation at peer review meetings.
Work cross-functionally to drive project schedules and achieve performance targets.
Perform lab evaluation or debug.
Mentor and develop junior engineers for technical growth.
Deliver technical writing, presentations and training sessions.
Required Education, experiences, and skills:
MSEE or Ph.D. degree in Power Electronics.
Minimum 3-year industry experience of switching power converter design and development.
Strong foundation of analog circuit, power electronics and power management systems.
Strong DC/DC power converter (Buck, Boost, etc.) design and optimization experiences and skills.
Solid knowledge and experience of transformer-based power converters (Flyback, forward, half-bridge, full bridge, etc.)
Strong analytic skills. Good knowledge and skills of power converter modeling, control architecture and loop design, static and dynamic performance optimizations.
Familiar with circuit design/simulation/optimization tools (SPICE/LTspice, Simplis, MathCAD/Matlab, Ansys/Maxwell, etc) and lab equipment for power applications.
Strong hardware and circuit debugging skills.
Firmware, DPS or FPGA programming and I2C/PMbus experience (preferred).
Analog IC design knowledge (preferred).
Magnetic design and simulation, thermal analysis knowledge and experiences.
Good technical writing and presentation skills
Strong communication skills and ability to work effectively in a multidisciplinary team.
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $144,038 to $216,056.
Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
Auto-ApplyPCIe / CXL IP Verification Engineer
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As an IP verification engineer in the AECG Group, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.
THE PERSON:
You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBLITIES:
* Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
* Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
* Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
* Build the directed and random verification tests
* Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality
PREFERRED EXPERIENCE:
* Experience with PCIe or CXL or NVMe or ethernet protocols is a must
* Proficient in IP level ASIC verification
* Expert in Verilog, System Verilog, Object Oriented programming
* Expertise in developing UVM based verification frameworks and testbenches
* Scripting and automation of verification processes and flows
* Exposure to leadership or mentorship is an asset
* Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
* Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
* Good Computer Architecture, systems knowledge
* Comfortable in python / perl and editing / maintaining scripts
* Strong communication skills and the ability to work independently as well as in a cross-site team environment
* Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus
ACADEMIC CREDENTIALS:
* Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION: San Jose, CA
#LI-DW1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
Physical Verification Engineer
San Jose, CA jobs
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: This is a unique opportunity to be at the forefront of AMD's next-generation product development. In this role, you will drive design verification flows that enable robust product design and successful tapeout, including advanced silicon technologies and 3DIC packaging solutions. THE PERSON: We are seeking a highly skilled Physical Verification Engineer to join our team. The candidate will be responsible for developing and maintaining Design Rule Check (DRC) decks, supporting product-level physical verification sign-off, and ensuring compliance with manufacturing requirements through Design for Manufacturability (DFM) flows. JOB RESPONSIBLITIES: * Develop, validate, and maintain DRC decks for advanced technology nodes * Support product & IP physical verification sign-off, including: *
Performing QA on physical verification flows * Reviewing and approving waiver requests * Collaborating with design teams to resolve violations * Work closely with foundry and internal teams to ensure rule compliance and process alignment * Implement and optimize DFM flows to improve yield and manufacturability KEY QUALIFICATIONS: * Strong experience in physical verification tools (e.g., Mentor Calibre, Synopsys IC Validator). * Proficiency in SVRF, TVF, or similar rule deck languages * Familiarity with advanced process nodes (TSMC 2nm & 3nm) and foundry design rules * Knowledge of DFM methodologies and best practices * Working experience of LVS, RC Extraction, EMIR and PERC ESD flow is preferred * Prior experience in supporting semiconductor product sign-off is preferred * Excellent problem-solving and communication skills ACADEMIC CREDENTIALS: * Bachelor degree in engineering or physical science, preferably with advanced degree (MS or PhD) LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
Embedded Adaptive Hardware Engineer
San Jose, CA jobs
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at ************** and on LinkedIn and Twitter (X).
Embedded Adaptive Hardware Design Engineer
For more than five decades, Analog Devices (ADI) has transformed how the world senses, measures, and interprets data-from precision analog circuits to advanced mixed-signal SoCs. Today, ADI is increasingly recognized as “the Intelligent Edge company,” leading digital transformation and reimagining the engineer's journey with AI-driven tools and customer-first design experiences. Looking ahead, ADI is making bold bets to double its presence in industrial automation by 2030, while accelerating breakthroughs in healthcare, robotics, automotive, and sustainability.
ADI's Embedded FPGA (eFPGA) team within the Digital Business Unit (DBU) plays a pivotal role in this transformation. The team is driving innovation in heterogeneous processing platforms, delivering industry-leading solutions that enable high-speed, real-time hardware adaptability and product differentiation across diverse markets and applications. Through multi-project execution and architectural innovation, the eFPGA team continues to advance this technology as a cornerstone of ADI's Intelligent Edge strategy.
To fuel this growth, we are seeking talented designers who are passionate about soft-logic design and optimization, software-hardware co-design, and building scalable, future-proof architectures for next-generation systems.
If you are excited about pushing the boundaries of real-time processing and shaping the future of adaptive hardware, we invite you to join us at the forefront of technological innovation.
What you'll be doing:
The group is seeking an experienced Embedded Adaptive Hardware Designer to contribute to the development of the eFPGA architecture and softlogic IDE. You do NOT need to be an eFPGA expert yet need to be experienced in digital hardware/architecture design. The job responsibility includes
Documenting eFPGA architecture, specifications, user guides, and design process
Upgrading eFPGA architecture and RTL for the advanced features, such as functional safety and ASIL-D automotive qualification.
Performing hardware-software co-design, such as the PPA analysis/optimization and the debug environment.
Developing the softlogic library (a library of RTLs that will be programmed into the eFPGA) as a part of the developer-friendly IDE that will be integrated into ADI's CodeFusion Studio.
Porting the eFPGA hardware IP to the advanced technology nodes, such as TSMC 16FFC, TSMC N4/N5.
Integrating the eFPGA IP in the chip with the SoC design team.
Interacting with the eFPGA verification and PnR team for design iteration.
What we need to see:
Master's degree (or equivalent experience) in Electrical Engineering or related fields.
Knowledge of system-level protocols and operations (e.g. AHB, AXI).
Basic understanding of design verification.
Deeply inquisitive and able to use core technical competencies to provide direction on system architecture.
Excellent communication skills required to work well with multi-functional teams (SoC integration, physical-design, software, marketing, etc.)
Strong EE fundamentals, knowledgeable in computer architecture, timing analysis, process variations, statistical error rates and power analysis.
Ways to stand out from the crowd:
5+ years of proven experience in SoC/microarchitecture design and RTL coding.
Tapeout experience in advanced nodes (N4/N5 or similar).
Understanding of functional-safety (FuSA) hardware requirements.
Understanding of chiplet protocols (e.g. UCIe) and characterization/validation methods in post-silicon environment.
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the time Shift Type: 1st Shift/DaysThe expected wage range for a new hire into this position is $144,038 to $216,056.
Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.
Auto-ApplyHardware Engineer
Irvine, CA jobs
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. :
Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes.
The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms.
Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California.
Responsibilities:
Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation.
The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness.
Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner
Qualifications:
Advanced degree in EE, Material Science, Physics or related field with 10+ years of industry experience after MS or 7+ years after PhD with recent work in advanced FINFET (or GAA) nodes.
1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions
2. Proficient in interacting with design teams and foundry partner
3. Familiarity with analog and digital design flows and CAD tools
4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis
5. Extremely detail oriented with strong analytical, communication, and multitasking skills
6. Mix of hands-on and project management skills
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $127,100 - $203,400
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Auto-ApplyHardware Engineer
Irvine, CA jobs
**Please Note:** **1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)** **2. If you already have a Candidate Account, please Sign-In before you apply.** **:**
****
Broadcom's Central Engineering Design Correlation team is looking for an energetic and self-driven professional to join our team to help with silicon technology evaluation in advanced process nodes for IP and product designs. Our mission is to assess foundry technology offerings, help define new technology platforms for IP and product designs, risk assessment, and provide Broadcom's design communities with insights into design and process-technology interactions especially during co-development in advanced process nodes.
The candidate will have the opportunity to participate in new technology platform definition, PPAC (power performance area cost) assessment and benchmarking, test structure design, silicon characterization and model to silicon correlation in most advanced foundry technology nodes. The candidate will work closely with other experts in the fields of CMOS process technology, device & modeling, process and device reliability, digital & analog IP design, design sign-off flow for timing and power, CAD & EDA tools, as well as chip designers from various product lines. Primary duties will include assessment of technology offerings and capabilities to meet design needs and drive alignment with IP/product requirements. This role will involve active participation with foundry and internal teams on new technology enablement including help ensuring robustness of technology platforms.
Candidate must have the ability to prioritize well, communicate clearly, deliver solutions on time, and possess excellent data analysis & foundry interaction skills. The candidate expected to work across multiple facets of projects and juggle multiple responsibilities at the same time. The position is in Broadcom's Irvine facility in California.
**Responsibilities** :
Candidate will support IP and Chip teams with technology evaluation including reliability and design enablement. Responsibilities as part of technology evaluation will involve test structure layout, verification, extraction, simulation, and silicon evaluation.
The job scope will include a) cross-functional quality assurance of designs and tape-outs, b) EDA & RCX tool quality and predictability, and c) custom device infrastructure readiness & robustness.
Candidate will engage in collaborative team projects involving design, platform technology, and operations teams and foundry partner
**Qualifications** **:**
Advanced degree in EE, Material Science, Physics or related field with 10+ years of industry experience after MS or 7+ years after PhD with recent work in advanced FINFET (or GAA) nodes.
1. Strong background in advanced CMOS technology (FEOL, MEOL, BEOL) including understanding of design-technology interactions
2. Proficient in interacting with design teams and foundry partner
3. Familiarity with analog and digital design flows and CAD tools
4. Hands-on experience with device/circuit level test structure designs, verification (DRC, LVS), extraction, spice simulation, silicon characterization (DC/AC/RF) and data analysis
5. Extremely detail oriented with strong analytical, communication, and multitasking skills
6. Mix of hands-on and project management skills
**Additional Job Description:**
**Compensation and Benefits**
The annual base salary range for this position is $127,100 - $203,400
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.**
**If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**
Welcome! Thank you for your interest in Broadcom!
We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.
For more information please visit our video library (******************************* and check out our Connected by Broadcom (************************************************************************************************************************************************* series.
Follow us on Linked In Broadcom Inc (****************************************** .
Hardware Engineer
San Jose, CA jobs
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : You will be part of the NPI team within the Wireless Semiconductor Division (WSD) of Broadcom. Cross-functional with R&D Project teams, Product engineering, Quality and Reliability Engineering teams, Packaging team and suppliers. Support products from development stage to product release.
Job scope and responsibilities
* Lead NPI engineering build plan and documentation/instruction to Contract Manufacturer release. Analyze demand and generate build plan as well as material supporting plan for engineering samples.
* Active interaction with suppliers to manage build process and material flow.
* PCB tape out logistic management and DRC process.
* Managing Wafer Backend(bumping dicing & TnR) processing vendor. Oversee overall engineering material supply from forecasting, tape out, order logistic and WIP monitoring.
* Communicate logistic status & lead activities to meet overall program objectives/supportability.
* Material planning and tracking for fast-paced projects inclusive of wafers, passive components and PCB.
* Develop and establish integrated system to drive work efficiency.
Education & Experience
* Bachelor's degree in engineering field.
* At least 5+ years of working in manufacturing environment, semiconductor industry is a plus.
Key qualification
* Experienced in manufacturing environment
* Able to collaborate with cross-functional teams to achieve project goal.
* Proactive communication skills & attention to details.
* Able to work in fast pace environment
* Demonstrate multi-tasking across different projects.
* Creative and strategic thinking in problem solving
Additional requirements
* Master in Microsoft excel
Additional Job Description:
Compensation and Benefits
The annual base salary range for this position is $101,000 - $162,000
This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.
Auto-ApplyHardware Engineer
Santa Clara, CA jobs
We're in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.
This type of work-work that changes the world-is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.
THE ROLE
We are seeking a Hardware Engineer to join our Hardware Development team and help shape the future of enterprise data storage. In this role, you'll be instrumental in designing, validating, and qualifying our cutting-edge storage subsystems, collaborating closely with engineering, operations, and partners to bring innovative solutions to market. You will own key projects from concept to production, ensuring quality, reliability, and performance.
WHAT YOU'LL DO
Participation of the entire hardware product development lifecycle, from initial design and documentation to validation, failure analysis, and sustaining engineering.
Define, implement, and automate hardware validation and qualification tests for new storage subsystems.
Partner with cross-functional teams, including engineering, operations, and support, to perform failure and root cause analysis and ensure seamless production launches and customer success.
Develop and implement processes and best practices that promote a culture of quality-by-design, enhancing the reliability and performance of our products.
Design and execute server stress tests and qualify complex CPU subsystems and peripherals, including DDR memory, LOM devices, and various bus technologies (SAS/SATA, PCIe, UPI, I2c, SPI, etc.).
WHAT YOU BRING
A strong background in hardware design, including knowledge of x86 architectures and interfaces.
Proven ability to qualify x86 hardware at the electrical, signal integrity, protocol, and functional levels.
Experience with Linux operating systems and proficiency in scripting languages like Python and BASH.
Experience with high-speed oscilloscopes, bus analyzers, and other lab equipment to capture and analyze data.
Demonstrated ability to work autonomously in a fast-paced environment while collaborating effectively with cross-functional teams to achieve project goals.
We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure's policies, unless you are on PTO, or work travel, or other approved leave.
#LI-ONSITE
Salary ranges are determined based on role, level and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations.
This role may be eligible for incentive pay and/or equity.
There is no application deadline and we accept applications on an ongoing basis until the job is filled.
The annual base salary range is:
$175,000 - $263,000 USD
WHAT YOU CAN EXPECT FROM US:
Pure Innovation: We celebrate those who think critically, like a challenge and aspire to be trailblazers.
Pure Growth: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work !
Pure Team: We build each other up and set aside ego for the greater good.
And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out purebenefits.com for more information.
ACCOMMODATIONS AND ACCESSIBILITY:
Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at ********************** if you're invited to an interview.
OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:
We're forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn't just accepted but embraced. That's why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership.
Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.
JOIN US AND BRING YOUR BEST.
BRING YOUR BOLD.
BRING YOUR FLASH.
Auto-ApplyHardware Engineer
Santa Clara, CA jobs
We're in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry. This type of work-work that changes the world-is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.
THE ROLE
We are seeking a Hardware Engineer to join our Hardware Development team and help shape the future of enterprise data storage. In this role, you'll be instrumental in designing, validating, and qualifying our cutting-edge storage subsystems, collaborating closely with engineering, operations, and partners to bring innovative solutions to market. You will own key projects from concept to production, ensuring quality, reliability, and performance.
WHAT YOU'LL DO
* Participation of the entire hardware product development lifecycle, from initial design and documentation to validation, failure analysis, and sustaining engineering.
* Define, implement, and automate hardware validation and qualification tests for new storage subsystems.
* Partner with cross-functional teams, including engineering, operations, and support, to perform failure and root cause analysis and ensure seamless production launches and customer success.
* Develop and implement processes and best practices that promote a culture of quality-by-design, enhancing the reliability and performance of our products.
* Design and execute server stress tests and qualify complex CPU subsystems and peripherals, including DDR memory, LOM devices, and various bus technologies (SAS/SATA, PCIe, UPI, I2c, SPI, etc.).
WHAT YOU BRING
* A strong background in hardware design, including knowledge of x86 architectures and interfaces.
* Proven ability to qualify x86 hardware at the electrical, signal integrity, protocol, and functional levels.
* Experience with Linux operating systems and proficiency in scripting languages like Python and BASH.
* Experience with high-speed oscilloscopes, bus analyzers, and other lab equipment to capture and analyze data.
* Demonstrated ability to work autonomously in a fast-paced environment while collaborating effectively with cross-functional teams to achieve project goals.
* We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Pure's policies, unless you are on PTO, or work travel, or other approved leave.
#LI-ONSITE
Salary ranges are determined based on role, level and location. For positions open to candidates in multiple geographical locations, the base salary range is reflective of the labor market across the applicable locations.
This role may be eligible for incentive pay and/or equity.
There is no application deadline and we accept applications on an ongoing basis until the job is filled.
The annual base salary range is:
$175,000-$263,000 USD
WHAT YOU CAN EXPECT FROM US:
* Pure Innovation: We celebrate those who think critically, like a challenge and aspire to be trailblazers.
* Pure Growth: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area, Fortune's Best Workplaces for Millennials and certified as a Great Place to Work!
* Pure Team: We build each other up and set aside ego for the greater good.
And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out purebenefits.com for more information.
ACCOMMODATIONS AND ACCESSIBILITY:
Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at ********************** if you're invited to an interview.
OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:
We're forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn't just accepted but embraced. That's why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership.
Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.
JOIN US AND BRING YOUR BEST.
BRING YOUR BOLD.
BRING YOUR FLASH.
Auto-Apply