Lead Design Engineer jobs at Cadence Design Systems - 307 jobs

## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST) and automatic test pattern generation (ATPG) is required for this position. Should follow systematic quality metrics driven ATPG pattern generation. It is highly desirable for candidate to possess hands-on knowledge of synthesis, verification and debugging Verilog testbenches.Requirements;US citizenship preferred.* Prior 5-15 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)* Should possess intimate knowledge of DFT insertion flows* Basic scan chain insertion using synthesis or other software tools* Experience in compression scan insertion, LBIST and other scan technologies* Intimate knowledge of memory build-in self-test (MBIST)* Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals* Debug and Analysis of failures to improve fault coverage* Verification of ATPG testbenches and debugging root cause of simulation mis-compares* Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687* Knowledge of timing analysis and equivalency checks would be added bonus* Ability to work in collaborative team environment* Prior experience with Cadence tools and flows is highly desirable* Should be able to finish DFT tasks independently* Strong problem-solving skills. Exhibit discipline, thoroughness, and methodical approach in solving problems* Ability to work with stakeholders across cross-functional teams - Architecture, Design, Internal and External Customers* Self-driven and committed individual who can work in a fast-paced project environment## **We're doing work that matters. Help us solve what others can't.****Equal Employment Opportunity Policy:**Cadence is committed to equal employment opportunity throughout all levels of the organization.We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact ********************.**Privacy Policy:**Job Applicant If you are a job seeker creating a profile using our careers website, please see the .E-Verify Cadence participates in theE-Verify program in certain U.S. locations as required by law.Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class. #J-18808-Ljbffr

Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > CPU Engineering As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm CPU Engineer, you will lead innovative Central Processing Unit (CPU) design efforts that have a critical impact on industries across the world. Qualcomm Engineers collaborate with cross-functional teams to design, verify, and implement multi-core CPU operations for all Qualcomm Business Units. Minimum Qualifications: • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field. Preferred Qualifications: • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. • 2+ years of work experience with high-performance microprocessor design. • 2+ years of work experience with high level programming (e.g., C, C++), scripting language programming (e.g., Perl, Python, etc.). • 2+ years of work experience with simulators and/or waveform debugging tools (e.g., Verilog, VHDL, etc.). • 2+ years of work experience with industry standard tools for synthesis place and/or route and design verification. • 2+ years of work experience with simulation, emulation, formal verification, or silicon validation. • 2+ years of experience in creating functional models, checkers, test plans, and/or test generation. • 1+ year experience working in a large matrixed organization. Principal Duties and Responsibilities: • Applies knowledge of computer architecture, micro-architecture, logic design, circuits, and/or physical design to develop and verify high performance and low power CPU designs. • Anticipates, identifies, and solves problems to ensure design completeness, functionality, power, and performance. • Collaborates across teams to define requirements, specifications, and trade-offs (e.g., performance, power, cost, functionalities, etc.) in order to accomplish product goals. • Evaluates the design process from conceptualization to productization (i.e., architecture definition, feasibility, pre-silicon design and verification, and post-silicon validation) that meet customer and industry standards. • Writes detailed technical documentation (e.g., feature descriptions, architectural descriptions, verification test plans, and implementation details, etc.) for CPU designs. Level of Responsibility: • Works independently with minimal supervision. • Decision-making may affect work beyond immediate work group. • Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. • Has a moderate amount of influence over key organizational decisions. • Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively. Note: We have multiple positions open at different job levels. Based on experience and background, the job level will be decided. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-maildisability-accomodations@qualcomm.comor call Qualcomm's toll-free number foundhere. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies:Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $122,500.00 - $183,700.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at thislink. If you would like more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

A leading technology firm is seeking a Physical Design Engineer to join their team in San Diego, CA. The ideal candidate will have extensive experience in ASIC design, focusing on clock tree synthesis and verification. This role requires strong scripting skills and the ability to collaborate across functional teams to meet performance goals. A competitive salary range of $140,000 to $210,000 is offered, along with comprehensive benefits. #J-18808-Ljbffr

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

Physical IC Design Engineer page is loaded## Physical IC Design Engineerlocations: USA-California-San Jose-1320 Ridder Park Drivetime type: Full timeposted on: Posted Todayjob requisition id: R024621**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **:**Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group. This position involves working with the latest technology to continue driving next generation AI/ML ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tape-out.**Responsibilities include, but are not limited to the following:*** Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure* Setup and Synthesizing RTL* Timing closure through various methods and strategies; preferable in-depth experience in top-level STA* EM/IR Analysis,* Place and Route* Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques* Floor-planning and Layout; preferable in-depth experience in top-level floorplanning* Flow and Methodology Development* Collaborating with IC Design RTL Engineers* Must work in person at our San Jose site: no remote work allowed.**Required attributes:*** TCL/PERL Scripting* Proficiency in related EDA Tools* Full physical design cycle experience: RTL to Tape-out* Excellent verbal and written communication skills**Education and Experience Requirements:*** Minimum: Bachelor's degree required in Electrical Engineering or Electronics Engineering* 12+ Years of relevant experience**Additional Job Description:****Compensation and Benefits**The annual base salary range for this position is $141,300 - $226,000. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.****If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.** #J-18808-Ljbffr

A leading technology company is seeking a Physical IC Design Engineer in San Jose, California. The role involves executing various physical design tasks and requires a bachelor's degree in Electrical or Electronics Engineering with over 12 years of relevant experience. Strong scripting skills and expertise in EDA tools are essential. The position offers a competitive salary range of $141,300 - $226,000 along with comprehensive benefits including health insurance, 401(K) matching and more. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a Physical IC Design Engineer to drive next-gen AI and ML ecosystems. The role requires 8+ years of experience and a Bachelor's degree in Electrical or Electronics Engineering. Responsibilities include execution of Physical Design, Synthesis, and collaborating with IC Design engineers. This position has a salary range of $120,000 - $192,000 and offers a comprehensive benefits package including health plans, 401(K) matching, and paid leave. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Physical IC Design Engineer to drive next-generation AI and ML ecosystems through PCIe Switch Products. This role requires a strong background in Physical Design, including execution of design, verification, and timing closure. The ideal candidate must have a Bachelor's degree in Electrical or Electronics Engineering and at least 8 years of experience. The position offers a competitive salary range of $120,000 to $192,000, along with comprehensive benefits. #J-18808-Ljbffr

A leading technology firm located in San Jose is seeking a Physical IC Design Engineer to drive innovation in Artificial Intelligence and Machine Learning through their products. This position focuses on executing the physical design and verification of chip architectures. Candidates should possess a Bachelor's degree in Electrical Engineering or Electronics Engineering and have over 8 years of relevant experience. The role offers a competitive salary ranging from $120,000 to $192,000, plus various benefits including medical and retirement plans. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking an experienced Physical IC Design Engineer to join their Data Center Solutions Group. You will drive advancements in AI/ML ecosystems and manage data centers. The ideal candidate will have over 12 years of experience in physical design and proficiency in TCL/PERL scripting. A Bachelor's degree in Electrical or Electronics Engineering is required. This position offers a competitive salary and comprehensive benefits package, including health insurance and 401(k) matching. #J-18808-Ljbffr

A leading technology firm in San Jose is seeking a Physical Design Engineer to focus on the implementation and optimization of IC layouts for advanced technologies. The ideal candidate has extensive experience in physical layout, strong scripting skills in TCL and Python, and a solid background in electrical engineering. This role offers a competitive salary, bonus potential, and comprehensive benefits. #J-18808-Ljbffr

A leading semiconductor company in San Jose seeks a Senior Engineer in Product Engineering to manage new product introductions and production support. Candidates should have a Master's degree in Electrical Engineering and two years of relevant experience. Responsibilities include interfacing with manufacturing, conducting failure analyses, and implementing process improvements. This role offers competitive pay and benefits, including healthcare coverage and a performance-based bonus. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. The Role This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The Person Strong analytical and problem solving skills with a pronounced attention to detail Strong communication, mentoring and leadership skills Self-driven, Methodical and attention to detail in troubleshooting and problem-solving Can work well with cross functional teams Excellent verbal and written communication skills Responsibility Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.) Create RTL designs using Verilog/SystemVerilog for high-performance applications Perform FPGA prototype design, implementation, and bring‑up activities Create comprehensive design documentation, specifications, and technical reports Perform timing analysis, closure, and optimization using Vivado tools Conduct board-level bring‑up and system integration testing Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements Independently troubleshoot and resolve challenging technical issues Work closely with hardware, software, and systems engineering teams Participate in design reviews and technical discussions Communicate project status, risks, and technical challenges to stakeholders Preferred Skill Set & Experience Extensive experience in field of FPGA hardware prototyping Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc Experience with Xilinx Versal ACAP or UltraScale+ devices Knowledge of FPGA synthesis tools and methodologies Familiarity with Python/TCL scripting for design automation Knowledge of FPGA-based system architecture and hardware/software co‑design Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers) Fluent in System Verilog and a familiarity with simulation and debug Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus EDUCATION BS (or higher) degree in Electrical or Computer Engineering desired LOCATION Santa Clara, CA This role is not eligible for visa sponsorship. #LI‑SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. Drive PPA optimization and ensure scalability across roadmap and custom devices. Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. Analyze trade-offs for performance, power, reliability, and manufacturability. Influence strategies for security, safety, and reliability across CPF domains. Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. Experience with low-power design techniques, boot/reset flows, and power management. Knowledge of design methodologies, advanced process technologies, and associated challenges. Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS BS or MS or PhD in Electrical/Computer Engineering or related field. Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry‑leading technologies to market. As a key contributor, you will focus on RTL design and validation of high‑speed interfaces such as chip‑to‑chip interconnect, both on system and on package, and highly configurable multi‑protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role. THE PERSON: You have a passion for digital design. You are a team player. You have strong analytical and problem‑solving skills. You are willing to learn and ready to take ownership of problems. KEY RESPONSIBILITIES: Perform RTL design of the digital components. Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP. Help lead and mentor other engineers to achieve project goals and organizational growth. Work with a functional (design) verification team to meet coverage and quality standards. Analyze/fix lint and CDC/RDC errors of the components. Guarantee quality/timely deliverables meeting project's schedule. Help to improve and automate design process. Support post‑silicon product bring‑up/debug. PREFERRED EXPERIENCE: Strong experience in designing digital components for high performance, low power SOC/FPGA. Design of digital circuits and components using Verilog/System Verilog. Creating and maintaining of timing constraints for complex multi‑clock designs. Debugging in digital and mixed‑signal simulation environment. Power optimization of digital designs. Multi‑clock domain designs. Experience/knowledge of high‑speed SerDes/Physical layer is a plus. Logic synthesis, timing closure, logical equivalence checking and ECOs. Scripting languages such as Perl, Tcl, or Python. Collaboration with verification team. Excellent verbal and interpersonal communication skills. Excellent technical communications. Ability to produce technical documentation. Exhibit strong ownership of tasks and responsibilities. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering with relevant industry experience. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Together, we advance your career. SMTS SoC Architect THE ROLE We are seeking a SoC Architect to join our adaptive SoC Architecture team. This role is pivotal in defining and driving architecture for next‑generation Adaptive SoCs, with Processor subsystems, Interconnect, AI, GPU, video processing pipelines, and memory systems. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems. You thrive in collaborative environments and bring a system‑level mindset to solving architectural challenges. You are passionate about performance, power, and scalability, and have a strong grasp of silicon design trade‑offs. You communicate effectively across engineering disciplines and influence architectural decisions with clarity and technical rigor. KEY RESPONSIBILITIES Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC Define and optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. Drive early‑stage architectural analysis, modeling, and specification development. Contribute to architectural innovation for Adaptive SoC Use‑cases in AI, GPU, video, and IO domains. Collaborate with planning, software and hardware cross‑functional teams to develop architecture solution. Collaborate with subsystem architects to ensure cohesive integration and system‑level performance. PREFERRED EXPERIENCE Proven experience in SoC architecture with Processor, Interconnects, and Memory subsystem. Expertise in AI accelerators, GPU integration, video processing pipelines, and IO subsystems. Expertise in SoC control bus design, reset architecture, clocking, and power management techniques. Experience with modeling and automation using Python, SystemC, or equivalent. Knowledge of advanced process technologies and associated design challenges. ACADEMIC & EXPERIENCE REQUIREMENTS BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. Demonstrated success in delivering high‑performance, low‑power SoC solutions. Benefits offered are described: AMD benefits at a glance. Equal Opportunity Employment AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr