Requirements Engineer jobs at Insight Enterprises - 7362 jobs

San Francisco Bay Area, California, United States Hardware Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than something - you'll add something.Do you love taking on big challenges that require exceptionally creative solutions? The Thermal team is responsible for all thermal aspects of highly collaborative, cross-functional design efforts. We are searching for an extraordinary engineer to help lead the definition and design of Apple products. You'll ensure all thermal objectives are met or surpassed from initial concept to design fruition and the user experience is optimized to surprise and delight our customers. Description You will be tasked with impacting product design decisions by providing reliable analysis and thermal insight. You'll define, guide thermal flow experiments to characterize materials, components, and systems. You'll drive architecture of next-generation cooling strategies for high-powered devices using analytical tools, CFD, and prototype testing. A strong sense of design ownership along with the ability to build consensus will help you drive technical challenges to conclusion. Additionally, you will lead technology investigations, design, implementation of thermal solutions and communicate status results to leadership. Minimum Qualifications 5+ years thermal design experience. M.S. in Mechanical Engineering or equivalent. Strong understanding of heat and fluid flow with the ability to apply this understanding to multi-disciplinary design problems. Excellent verbal and written communications skills. Deep technical and functional expertise in conduction, convection (natural and forced) and radiation, as well as numeric modeling techniques and concepts. Experience with both CFD and experimental techniques for design validation. Ability to clearly communicate complex technical material. Occasional domestic and international travel required. Preferred Qualifications Ph.D. in Mechanical Engineering with emphasis on Heat Transfer or Fluid Dynamics. 7+ years of thermal design experience. Deep knowledge of TIMs, heat sinks, heat pipes, vapor chambers, cold plates, pumps, and air movers for thermal mitigation, especially within a datacenter environment. Proven ability to lead high visibility programs. Ability to thrive in a fast-paced work environment. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

San Francisco Bay Area, California, United States Hardware The Wireless SoC Radio Team designs state‑of‑art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed‑signal blocks from RF front‑end amplifiers to data converters, including baseband filters, baseband and RF phase‑locked loops, crystal oscillators, and bandgap references. Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next‑generation of wireless technologies into high‑volume production in advanced CMOS technology nodes. Responsibilities Detailed transistor‑level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. Co‑work with designers on block level floorplanning. Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling. Minimum Qualifications BS and 3+ years of relevant industry experience. Preferred Qualifications Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub‑micron CMOS. Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. Solid understanding of RC delay, electromigration, and coupling. Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. Knowledge of CADENCE layout tools. Scripting skills in PERL or SKILL. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $141,800 and $258,600, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

A leading AI technology firm based in San Francisco is seeking GenAI Engineers at various levels to drive the development of innovative GenAI-powered products. This role involves shaping AI features, developing LLM technologies, and collaborating with cross-functional teams. Ideal candidates should have 2-8 years of ML engineering experience and proficiency in Python and TensorFlow/PyTorch. A competitive pay range of $166,000 to $210,250 USD is offered, along with comprehensive benefits. #J-18808-Ljbffr

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis. Strong fundamentals in the area of Digital design Familiarity with ASIC design timing concepts Proficient in scripting languages (TCL, Python and Perl) Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks Self-starter and highly motivated Ability to communicate optimally across all internal groups Bachelors Degree + 0 Years of Experience.

**Role Number:** 200*********** Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide. **Description** You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies. **Minimum Qualifications** + BS with 3+ years of industry experience. + Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond) and proficiency with FinFET structures, guard-rings, deep N-wells, and PN junctions are required. + Familiarity with sophisticated process effects such as LOD, WPE, and DFM is critical. + Understanding trade-offs involving matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up is vital. **Preferred Qualifications** + Experience in sophisticated DRC, ERC, LVS verification, and debugging. + Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus. + RF experience is helpful. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200628172-0240 At Apple, we work every single day to craft products that enrich people's lives. In this highly visible role, you will take ownership of the ESD and Latch-Up requirements of all ICs developed by and for Apple. Your mission is to ensure the silicon is designed to meet Apple's ESD specifications and manufacturing requirements. The role involves working closely with our diverse teams within Apple as well as external vendors. Occasional travel might be required. Do you love working on challenges that no one has solved yet? Are you excited to build Apple's products that strive for the highest expectations of quality, innovation and efficiency? We have an opportunity for an especially innovative ESD Designer with strong fundamentals! We are looking forward to having you join our fast growing team and help us deliver on these challenges while enjoying an amazing culture where you lead your career! **Description** Work in a cross-functional team that delivers high quality on-chip IPs immune to ESD/EOS and latchup events. Ensure ESD robust designs with minimum cost to mission-mode functions. **Minimum Qualifications** + BS and 10+ years of relevant industry experience **Preferred Qualifications** + MS and 8+ years relevant industry experience. + Deep understanding of transistor device characteristics. + Solid understanding of models used for testing ESD, including HBM, CDM, MM and IEC-61000-4-2. + Knowledge of state-of-the-art ESD circuit design techniques and topologies. + Hands-on experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc. + Knowledge of ESD checking tools like PERC and Pathfinder. + Experience with Si processes used for high voltage, RF, or advanced ASICs. + Experience with ESD/LUP test and characterization equipment. + Strong initiative, collaboration, and ownership of responsibilities, productive, able to meet challenging deadlines. + Excellent written and verbal communication skills. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide.You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies.Experience in sophisticated DRC, ERC, LVS verification, and debugging. Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus. RF experience is helpful.Array

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. **Description** As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. **Minimum Qualifications** + BS and 3+ years of relevant industry experience. + FinFet experience. **Preferred Qualifications** + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of CADENCE layout tools. + Excellent communication skills. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. **Description** As an RFIC Layout Designer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Apple's state-of-the-art radios and getting them into hundreds of millions of products. **Minimum Qualifications** + 5+ year minimum related experience required. + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of Cadence layout tools. **Preferred Qualifications** + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. + Excellent communication skills and able to work with cross-functional teams. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references. **Description** As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. **Minimum Qualifications** + BS and 10+ years of relevant industry experience. + FinFet experience. **Preferred Qualifications** + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of CADENCE layout tools. + Excellent communication skills. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. **Description** As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs. **Minimum Qualifications** + Bachelors Degree + 10 Years of Experience **Preferred Qualifications** + Strong fundamentals in the area of Digital design + Self-starter and highly motivated + Proficient in scripting languages (TCL and Perl) + Familiarity with ASIC design timing concepts + Exposure in STA tools (Primetime) is a plus + Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks + Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required + Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus + Ability to commnicate optimally across all internal groups Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

Ascentt is building cutting-edge data analytics & AI/ML solutions for global automotive and manufacturing leaders. We turn enterprise data into real-time decisions using advanced machine learning and GenAI. Our team solves hard engineering problems at scale, with real-world industry impact. We're hiring passionate builders to shape the future of industrial intelligence. Job Summary: We are seeking a motivated Junior BI Engineer to join our analytics team. The ideal candidate will be responsible for developing and maintaining business intelligence solutions, working closely with stakeholders to deliver actionable insights. This role involves building dashboards, writing SQL queries, supporting data models, and ensuring the accuracy and reliability of reporting solutions. Key Responsibilities: Develop and maintain BI dashboards and reports using tools such as Power BI or Tableau. Write, optimize, and maintain SQL queries to extract, clean, and analyze data from relational databases. Collaborate with business stakeholders to gather requirements and translate them into effective technical solutions. Support the design and implementation of data models, metrics, and KPIs. Assist in ETL processes and integrate data from multiple systems. Ensure accuracy, consistency, and quality of data and reporting deliverables. Participate in code reviews, QA testing, and documentation to maintain best practices and standards. Qualifications & Skills: Bachelor's degree in Computer Science, Information Systems, Data Analytics, or a related field. Hands-on experience with BI tools (Power BI, Tableau, or similar). Strong knowledge of SQL and relational databases. Basic understanding of ETL processes and data integration concepts. Good analytical and problem-solving skills with strong attention to detail. Ability to work collaboratively in a team environment and communicate effectively with stakeholders. Nice to Have: Exposure to cloud platforms (AWS, Azure, or GCP). Familiarity with version control (Git) and Agile methodologies. Knowledge of Python or R for data analysis.

A leading tech company is seeking a Business Intel Engineer III located in San Francisco, CA. The role involves managing metrics reporting, performing statistical modeling, and developing forecasting technologies. Candidates must have a Master's degree in a related field or equivalent experience, along with skills in SQL, ETL, and statistical analysis. This position offers a salary range of $159,099 to $176,300 annually, along with a comprehensive compensation package including benefits and equity incentives. #J-18808-Ljbffr

Role: Senior Azure DevSecOps Engineer Duration: 6+ months In-person interview is Mandatory at Santa Clara, CA Overview: We are seeking a Senior Azure DevSecOps Engineer to build, maintain, and operate our Azure cloud platform from the ground up. This role follows approved architecture designs and is responsible for turning them into a secure, scalable, and production-ready platform. This individual must be exceptionally strong in Terraform and Infrastructure as Code, have deep hands-on Azure experience, and bring a security-first mindset to everything they build. Manager's Note: Experience in working with ArgoCD and GitOps Model Kustomize and Defender for DevOps Knowledge of Terraform Handling of Azure managed Kubernetes clusters IaaC (experience in writing Yaml files, configuring pipelines in Azure) Troubleshoot production issues by monitoring service Error logs from platform/infra side They should understand Azure thoroughly- how to scale up/down services, Applying IAM policies, Setting up Managed API Gateway, Managed Database services in Azure etc. These are very important Grafana and Prometheus ( Nice to have ) Finally having " security first " mindset. Key Responsibilities: Build, deploy, and maintain Azure cloud infrastructure in alignment with defined architecture Design and manage Infrastructure as Code (IaC) using Terraform Use Terraform Cloud for remote state management, workspaces, and deployment workflows Own and operate CI/CD pipelines for infrastructure and application deployments Deploy and manage observability solutions, including Grafana, metrics, logging, alerting, and dashboards Build and support microservices-based architectures Deploy and manage containerized workloads using Kubernetes (Azure Kubernetes Service - AKS) Monitor platform health and troubleshoot production issues using logs, metrics, and alerts Scale Azure services up and down to meet performance and availability requirements Implement and manage Azure IAM/RBAC policies following least-privilege principles Configure and operate Azure managed services, including: Managed API Gateway Managed database services Networking and security components Partner closely with Software Engineering, Architecture, and Security teams Participate in incident response and root cause analysis from a platform perspective Ensure platforms are secure by design, not secured after deployment Required Skills & Experience (Must Have): Very strong hands-on experience with Terraform Hands-on experience with Terraform Cloud, including: Remote state management Workspaces Workflow-driven deployments Deep expertise in Infrastructure as Code (IaC) concepts and best practices Strong experience building and operating Azure cloud platforms Hands-on experience with Azure Kubernetes Service (AKS) Strong understanding of microservices architecture Experience with containers and Kubernetes Proven experience building cloud platforms from the ground up Strong experience designing and managing CI/CD pipelines Experience implementing observability platforms, including Grafana Strong troubleshooting skills using logs, metrics, dashboards, and alerts Ability to support and stabilize production environments Security Expectations (Critical): Strong security-first mindset Experience implementing least-privilege access, secure configurations, and guardrails Understanding of cloud security fundamentals and secure architecture patterns Comfortable working with security reviews, audits, and compliance requirements Ability to embed security into infrastructure, pipelines, and runtime environments Nice to Have: DevSecOps tooling experience Experience integrating Terraform Cloud with CI/CD systems Knowledge of Azure Monitor, Log Analytics, Prometheus, or similar tools Experience with incident response and on-call rotations Experience operating in regulated or audited environments Cloud cost optimization experience What Success Looks Like: A stable, scalable, and secure Azure platform Infrastructure fully managed through Terraform and Terraform Cloud Reliable CI/CD pipelines with strong observability Faster, safer deployments with reduced production issues Strong collaboration across Engineering, Architecture, and Security teams

A leading AI research company is seeking a privacy engineer in San Francisco. You will protect user data while ensuring AI system efficiency, employing techniques like differential privacy and federated learning. Responsibilities include designing privacy-preserving algorithms, investigating privacy-performance trade-offs, and developing documentation. Ideal candidates have experience with privacy technologies and deep learning. OpenAI promotes a diverse environment and offers relocation assistance. #J-18808-Ljbffr

A global technology company is looking for a seasoned software engineer to enhance AI capabilities within their observability platform. Candidates should have a strong background in AI/ML systems, cloud computing, and robust technical leadership. This role is pivotal in driving innovation in data analysis and delivering scalable solutions. The ideal candidate will thrive in an agile environment and provide mentorship to junior engineers. Enjoy competitive salaries and benefits while contributing to impactful technology solutions. #J-18808-Ljbffr

About Poshmark Poshmark is a leading fashion resale marketplace powered by a vibrant, highly engaged community of buyers and sellers and real-time social experiences. Designed to make online selling fun, more social and easier than ever, Poshmark empowers its sellers to turn their closet into a thriving business and share their style with the world. Since its founding in 2011, Poshmark has grown its community to over 130 million users and generated over $10 billion in GMV, helping sellers realize billions in earnings, delighting buyers with deals and one‑of‑a‑kind items, and building a more sustainable future for fashion. For more information, please visit ***************** and for company news, visit newsroom.poshmark.com. Big Data team is a central player in the Poshmark organization. Our mission is to build a world‑class big data platform to bring value out of data for us and for our customers. Our goal is to democratize data, support exploding business, build data and ML pipelines to fuel existing and new business critical initiatives. We are looking for exceptional, creative and passionate Machine Learning engineers to join our ML and Big Data Team. You will be responsible for building and owning the next‑generation of algorithms and systems that would have critical business impact for Poshmark and improve the user experience for our millions of users. Responsibilities: Explore large datasets, research and develop algorithms/models to solve interesting business problems. Design and code highly scalable, machine learning applications processing large volumes of data. Collaborate with multiple teams - data science, business, engineering and help deliver Machine learning based Data products across the company. Develop best practices and tools to enable robust delivery of features. Design and improve architecture in order to ensure horizontal scalability at all layers. Ideal Candidate: Strong background in Machine Learning with deep understanding of algorithms and modeling techniques. 6+ years of overall software development experience with at least 4+ years of industry experience applying Machine Learning to concrete problems. Great coding skills and strong software development experience with Big Data technologies & Machine Learning frameworks like SparkML, TensorFlow, PyTorch, Keras. Understanding of distributed systems, and large scale engineering challenges is plus. Technologies we use: Scala, Python MongoDB, Redshift, Druid Airflow, Jenkins Spark, SparkML, Kinesis #J-18808-Ljbffr

A data consulting firm based in San Francisco is seeking a Palantir Foundry Consultant for a contract position. The ideal candidate should have strong experience in Palantir Foundry, SQL, and PySpark, with proven skills in data pipeline development and ETL automation. Responsibilities include building data pipelines, implementing interactive dashboards, and leveraging data analysis for actionable insights. This on-site role offers an excellent opportunity for those experienced in the field. #J-18808-Ljbffr

Key Responsibilities Lead the end-to-end architecture and implementation of Snowflake(Bronze/Silver/Gold layers). Partner with business and data stakeholders to translate requirements into canonical models, ontologies, and data products. Define and enforce data modeling standards, naming conventions, and domain-driven design principles. Guide teams on data ingestion patterns, transformation frameworks (e.g., dbt), and performance optimization in Snowflake. Integrate data management capabilities including Data Quality using SODA, Data Governance, Metadata Management, and Data Observability. Ensure platform scalability, security, cost optimization, and compliance with enterprise standards. Provide technical leadership and mentorship to data engineers and modelers. Act as a key contributor in roadmap planning, technical decision-making, and stakeholder communication. Required Skills & Experience 10+ years of experience in data engineering and platform architecture, with at least 3+ years in a lead role. Strong hands-on experience with Snowflake (performance tuning, clustering, security, cost optimization). Hands-on experience with cloud platforms (AWS, Azure, or GCP) Understanding with Data Domains (Client, Finance etc.) Deep understanding of data modeling (dimensional, canonical, domain-driven). Experience designing or working with ontology / semantic layers (business vocabularies, relationships, metrics). Strong knowledge of modern data stack tools (dbt, orchestration, CI/CD for data). Experience implementing Data Quality, Data Governance, Metadata, and Data Observability solutions. Experience with orchestration tools such as: Apache Airflow, Prefect, or Luigi. Solid SQL skills and strong understanding of ELT patterns. Ability to lead cross-functional teams and communicate complex concepts to both technical and non-technical stakeholders. Nice to Have Experience with knowledge graphs, semantic models, or graph technologies. Exposure to enterprise data platforms supporting multiple domains and global users. Background in cloud-native architectures and large-scale data modernization programs.