Electrical Systems Engineer jobs at KBR - 12074 jobs

A leading engineering firm in Boston seeks a Senior Project Engineer to manage design aspects of electrical systems for various projects. The role involves leading design efforts, coordinating with other trades, and ensuring projects adhere to deadlines and quality standards. With a minimum of 5 years of experience and a Bachelor's in Electrical Engineering, the ideal candidate will be proficient in software such as Revit and AutoCAD. Offering a hybrid workplace and comprehensive benefits, this role provides opportunities to work on iconic projects. #J-18808-Ljbffr

MANTECH seeks a motivated, customer-oriented Systems Integration Engineer to help support our current Marine Corps ISR Contract in Stafford, VA. The ideal candidate will be responsible for understanding the integration and interoperability of complex systems across the USMC ISR enterprise. This role requires a strong technical background, excellent communication skills, and the ability to work effectively with a diverse team of technical and non-technical personnel, of all ranks and grades. Experience with Model-Based Systems Engineering (MBSE) is highly desired. Responsibilities include but are not limited to: Stakeholder Collaboration: Act as the primary point of contact for systems integration activities, liaising between technical engineering teams, requirement sponsors, program managers, operational SMEs, and other stakeholders to ensure alignment of operational requirements and capabilities with mission needs. Data Flow and Mission Thread Analysis: Define, analyze, and document data flows and end-to-end performance-based mission threads. This involves defining and mapping operational activities to performance parameters and identifying capabilities and limitations to achieving the execution of specific mission threads / scenarios. Technical Leadership: Provide technical guidance to Capability Integration Officers (CIOs) and CE-Intel Leadership with respect to data integration and interoperability. Participate in technical reviews, trade studies, and performance assessments to inform capability gap assessments, requirement definitions, and resource decisions. Model-Based Systems Engineering (MBSE): Apply MBSE principles and tools (such as Cameo (SysML, UAF)) to develop and maintain mission and scenario-based architectures, define "as-is" and "to-be" architectures, and review requirements traceability within available tools (such as JAMA). Guide the transition from document-based approaches to a model-based digital engineering environment. Communication and Reporting: Clearly articulate complex technical concepts to both technical and non-technical audiences of all ranks/grades. Prepare and present technical briefings and status reports to leadership and customer representatives. Minimum Qualifications: Bachelor's degree in Systems Engineering, Electrical Engineering, Computer Science, or a related technical field and at least 8 years of systems engineering, integration, or a related role. Proven experience with C4ISR systems Strong understanding of systems engineering lifecycle, requirements analysis, and interface design. Excellent interpersonal and communication skills, with a demonstrated ability to work effectively in a team-oriented, collaborative environment Preferred Qualifications: Knowledge of DoD / USMC garrison and tactical environments. Master's degree in a relevant technical field. Proficiency with MBSE tools and methodologies such as SysML, UAF, UML using Cameo. Experience with Department of Defense Architecture Framework (DoDAF). Familiarity with DoD acquisition and Agile development processes. Experience in developing and analyzing mission threads for complex systems-of-systems. Prior military experience or experience working directly with operational users and SMEs. Clearance Required: Must have an active DoD TS/SCI Clearance Physical Requirements: Sedentary Work.

A leading technology company located in Sunnyvale, CA is looking for an ASIC Physical Design Engineer to drive the development of cutting-edge TPU technology, crucial for AI/ML applications. The role requires 7 years of physical design experience, proficiency in Python, and collaboration with various teams to optimize design outcomes. The position offers a competitive salary range of $156,000-$229,000, plus bonus and benefits. #J-18808-Ljbffr

Employment Type: Full-Time | On-Site Industry: Electrical Construction About the Opportunity A highly respected and long-established electrical contracting and engineering firm in the Tri-State area is seeking an Electrical Project Engineer to support large-scale, high-profile projects throughout New York City and New York State. This organization has grown into one of the largest specialty electrical contractors in the United States by consistently delivering projects with integrity, reliability, efficiency, and a strong commitment to safety. Work spans a diverse range of market sectors including aviation, bridges and tunnels, commercial, education, environmental, healthcare, hospitality, industrial, mixed-use, public works, retail, residential, sports and entertainment, and utilities. The portfolio includes some of the most complex and recognizable infrastructure and landmark projects in the region, with continued demand driven by major public and private developments across New York. Position Overview The Electrical Project Engineer will play a critical role in supporting the execution of complex electrical construction projects from preconstruction through closeout. This position focuses on technical coordination, drawing management, and collaboration between design teams, project management, and field operations. This role is well suited for a detail-oriented professional with strong drawing and coordination experience who is looking to grow within large-scale electrical construction environments. Key Responsibilities Support project management and field teams throughout all phases of construction Produce, review, and coordinate electrical drawings and design documentation Manage drawing revisions, RFIs, and submittals to ensure accuracy and constructability Coordinate closely with engineers, designers, superintendents, and trade partners Assist with material takeoffs, procurement tracking, and delivery schedules Support schedule updates, cost tracking, and change management efforts Participate in coordination meetings and field walks as required Ensure drawings and installations align with project specifications, codes, and safety standards Qualifications Experience supporting electrical construction projects in commercial, infrastructure, or institutional environments Strong electrical drawing experience Current and prior proficiency in Revit is essential Excellent organizational, communication, and coordination skills Ability to work effectively on fast-paced, technically complex projects Compensation & Benefits Competitive salary based on experience ($120,000 - $160,000) Performance-based bonus opportunities 401(k) with company match Comprehensive medical, dental, and vision coverage Paid time off and paid holidays Long-term career growth on landmark New York projects This is an opportunity to gain hands-on exposure to some of the most complex electrical construction projects in New York while building a long-term career within a top-tier specialty contractor.

corporate_fare Google Sunnyvale, CA, USA Apply Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 7 years of experience with physical design (e.g. from RTL to GDSII, including key stages like floorplanning, place and route, and timing closure). Experience in Python, Tcl, or Perl scripting. Preferred qualifications: Experience working with external partners on Physical Design (PD) closure. Experience in Static Timing Analysis (STA), with an understanding of how to define timing corners, margins and derates. Experience with Synopsys/Cadence PnR tools. Experience with backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.). Understanding of DFT including Scan, MBIST and LBIST. Understanding of performance, power and area (PPA) trade-offs. About the job In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As an ASIC Physical Design Engineer, you will collaborate with RTL, Design for Testing (DFT), Floorplan, and full‑chip Signoff teams. Additionally, you'll solve technical problems with innovative micro‑architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary range for this full‑time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Participate in the Physical Design of complex blocks. Contribute to the design and closure of the full chip and individual blocks from RTL‑to‑GDS. Collaborate with internal logic and internal and external teams to achieve the best Power/Performance Analysis (PPA). This includes conducting feasibility studies for new microarchitectures as well as optimizing runs for finished RTL. Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire . Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE As a member of the AMD, you will help bring to life cutting‑edge designs and deliver IPs to SOC. As a member of the front‑end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first‑pass silicon success. THE PERSON You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem‑solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi‑site environment are keys to being successful in this role. KEY RESPONSIBLITIES RTL design of high speed design, clock/reset/power features, IP Integration, sub‑system level design Architect and design of power management features. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter‑IP integration issues resolution Own the Clock‑Domain crossing, Linting aspects of the overall design of the IP and the subsystem Work closely with FEINT, DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro‑architecting and documentation of the design features Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. REFERRED EXPERIENCE Extensive experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front‑end EDA tools sign‑off and its flows Familiarity with low power design and low power flow is an added plus Ability to program with scripting languages such as Python or Perl is a plus Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements Proven interpersonal skills, leadership and teamwork Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi‑tasking Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts Knowledge of, or experience in, functional design verification or design is highly desired ACADEMIC CREDENTIALS Bachelors or Masters degree in computer engineering / Electrical Engineering This role is not eligible for visa sponsorship. LOCATION: Santa Clara, CA Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara, CA, seeks a skilled digital design engineer. The role involves RTL design, power management features, and collaboration across teams. Candidates should have strong Verilog skills and experience in IP design. A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required. This position offers an opportunity to be part of a company that values innovation and teamwork, but it is not eligible for visa sponsorship. #J-18808-Ljbffr

A leading technology company in Santa Clara seeks an experienced ASIC Design Engineer specializing in GPU/ML Shader Core. In this role, you will define micro-architecture, implement RTL, and collaborate with various engineering teams. Ideal candidates will have experience in micro-architecture and an undergraduate degree in Computer Engineering or Electrical Engineering. Enjoy a vibrant culture that fosters innovation and teamwork, while pushing the boundaries of next-generation computing. This role does not offer visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an “out of the box” thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle “how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power”. Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. Consult DV engineers in describing features, outlining test plans, and closing on coverage Assist DV engineers to debug functional, performance or power test failures Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading tech company is seeking an RTL Design Engineer in Sunnyvale, CA to shape the future of AI/ML hardware acceleration. The ideal candidate will work on cutting-edge TPU technology, taking part in ASIC development to enhance computational efficiency in data centers. Responsibilities include defining project scope, design, and documentation of next-generation data center accelerators, alongside collaborative efforts with cross-functional teams to drive innovations that empower billions of users globally. Comprehensive education and experience in relevant engineering fields are essential. #J-18808-Ljbffr

A leading tech company in Sunnyvale seeks a Physical Design Engineer to contribute to the development of cutting-edge TPU technology. You will collaborate with various teams to enhance design processes, focusing on innovative solutions for AI/ML applications. Candidates should have relevant experience in physical design, strong qualifications in Electrical Engineering, and skills in scripting languages like Python. The role offers a competitive salary range and numerous benefits, with a strong emphasis on diversity and inclusion. #J-18808-Ljbffr

A technology company in San Jose is seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs. The role requires expertise in RTL ownership, complex timing constraints, and EDA tools, alongside strong communication skills. Candidates should have a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. This is a non-remote role requiring in-person presence, and does not offer visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE AMD is looking for a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs, featuring multiple physical blocks and complex timing constraints. The candidate's responsibilities will include RTL ownership and integration, building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON The ideal candidate demonstrates high energy, excellent written and verbal communication skills, and a structured, organized approach to work. They are collaborative and strongly focused on achieving team and organizational goals. KEY RESPONSIBILITIES Responsible for RTL design and integration. Contribute to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural specification, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis and timing closure. Develop complex multi-mode/multi-corner timing constraints that are compatible for RTL and signoff. Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA (static timing analysis) checks. Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts). Continuously review and identify areas for process improvements and early issue detection during the design phase. PREFERRED EXPERIENCE Experience with SoC designs that includes RTL design and integration. Worked with EDA tools that enable RTL quality checks. Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Ability to multitask, grasp new flows/tools/ideas. Experience in improving the methodologies. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT). Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters. Strong analytical and problem-solving skills. ACADEMIC CREDENTIALS Bachelor's or Master's degree in Electrical Engineering or Computer Engineering LOCATION San Jose This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, CA to contribute to the development of large SoCs. You will be responsible for building and verifying timing constraints and collaborating on complex design projects. Ideal candidates should have strong SDC and EDA tool expertise, along with experience in Tcl scripting. This role offers a collaborative work environment and is hybrid. #J-18808-Ljbffr

A leading technology company located in Sunnyvale, CA, is looking for a Physical Design Engineer. In this role, you will shape the future of AI/ML hardware acceleration by working on cutting-edge TPU technology. The ideal candidate will have a Bachelor's degree in a relevant field and at least 1 year of physical design experience. Responsibilities include collaborating with various teams to ensure optimal design and performance. A competitive salary range of $113,000-$161,000 is offered, along with bonuses and benefits. #J-18808-Ljbffr

MEP Project Engineer - High-Rise Construction (Miami, FL) G&E Partners is partnered with a leading high-rise General Contractor in Miami that is actively expanding its project teams due to a strong pipeline of luxury residential and mixed-use tower projects. This is a fully on-site role supporting complex, multi-story builds and offers long-term career progression within a growing Florida operation. Responsibilities Support MEP scopes across all phases of high-rise construction Coordinate with mechanical, electrical, plumbing, and fire protection subcontractors Review submittals, RFIs, shop drawings, and MEP schedules Track procurement and long-lead equipment (switchgear, generators, chillers, etc.) Assist with inspections, testing, and commissioning activities Work closely with Project Managers, Superintendents, and BIM/VDC teams Maintain documentation and ensure compliance with contract requirements Requirements 1-5+ years of experience in construction, ideally with a GC or large MEP subcontractor Exposure to high-rise, multifamily, hospitality, or large commercial projects preferred Strong understanding of mechanical, electrical, and plumbing systems Degree in Construction Management, Engineering, or related field preferred Comfortable working fully on-site in Miami Why Join Career-defining high-rise projects (30+ to 100+ stories) Strong project backlog and long-term stability Clear path into MEP Project Management Competitive salary, bonus, and full benefits package

A leading global hedge fund in Seattle is seeking a Quantitative Developer to build critical trading infrastructure. You will collaborate with quantitative researchers and senior portfolio managers to optimize systems for trading strategies across global futures and equities. Candidates should have strong skills in React/Typescript and Python, paired with a Master's or PhD in a relevant field. This position offers significant career growth and impact in a dynamic environment. #J-18808-Ljbffr

Mini-Circuits designs, manufactures and distributes integrated circuits, modules, and sub-systems for high-performance radio frequency (RF) and microwave applications. With design, sales, and manufacturing locations in over 30 countries, Mini-Circuits' products are used in a range of wired and wireless communications applications. Our products are also used in detection, measurement, and imaging applications, including military communication, guidance, and electronic countermeasure systems, commercial, scientific, military land, sea, and aircraft; automotive systems, medical systems, and industrial test equipment. Mini-Circuits sells its products to over 20,000 customers globally through our direct sales force, applications engineering staff, and sales representatives, as well as through our extensive website. Position Summary Design, validate, and scale automated production test systems and robotic device handlers for RF and Microwave components. This role is responsible for enabling standardized architectures, throughput improvement, global alignment, and long-term scalability of automated test processes. Salary Range $100,000 - $125,000 per year Job Function Define, design, and validate standardized robotic test handlers, adaptable across multiple RF product lines. Drive new handler integrations and improvements, document FPY, OEE, and operator experience metrics. Collaborate with global teams (Brooklyn, Florida, India, Malaysia) to ensure alignment, backup-site readiness, and standardized deployment. System Design & Development Analyze test and assembly processes to identify candidates for automation based on capacity, efficiency, and process control needs. Develop scalable, modular designs for automated handlers, including mechanical, electrical, vision, and control systems. Specify and integrate sensors (vision, position, presence), robotic arms, conveyors, and fixturing for precision RF component handling. Incorporate RF test-specific requirements (grounding, thermal, high-frequency probing, shielding). Prepare proposals, resource/budget estimates, and project plans for new automation initiatives. Lead cross-functional reviews and maintain stakeholder communication from concept to qualification. Manage vendor engagement, procurement, build, and qualification of handler systems. Documentation & Training Create system specifications, qualification/buy-off plans, operation and maintenance procedures. Train users and support personnel on deployed automation platforms. Drive continuous improvement in throughput, FPY, reliability, and maintainability. Track and implement engineering changes and upgrades into future designs. Stay current with emerging automation technologies (vision, robotics, motion systems, AI-driven inspection) and evaluate for Mini-Circuits applications. Qualifications BS/MS degree in Mechanical, Electrical, Mechatronics, or Control Systems Engineering. Minimum 5 years of relevant experience. Experience with robotic systems, automated handlers, or precision motion/vision-based automation. Familiarity with high-mix/low-to-medium volume manufacturing environments. Controls programming experience (PLC, microcontrollers in C/C++, or equivalent). Data collection and analysis skills (Excel, JMP, Python). Preferred Knowledge Experience with automated inspection systems (AOI, Keyence, Cognex vision). Knowledge of RF test process requirements and challenges. Conveyor/robot integration, pneumatic actuators, precision fixturing. Understanding of Lean Manufacturing, OEE analysis, and ROI calculations. Exposure to manufacturing ERP and PLM systems (SAP, Arena PLM, etc.). Skills Strong communication and documentation skills. Ability to lead cross-functional teams and vendor collaborations. Capable of balancing hands‑on design/build/debug with strategic project leadership. Physical Demands The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. While performing the duties of this job, the employee is regularly required to talk and hear. The employee frequently is required to stand, walk, sit and use hands to operate a computer keyboard. The employee is occasionally required to reach with hands and arms. The employee must occasionally lift and/or move up to 10 pounds. Specific vision abilities required by this job include close vision, and ability to adjust focus. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. Additional Requirements/Skills Must be a US citizen or US permanent resident Ability and willingness to abide by Company's Code of Conduct Occasional travel, some overnight, as required Benefits Comprehensive Medical, Dental, and Vision plans 401(K) and Profit‑Sharing Programs Disability Insurance Life Insurance Employer‑Sponsored Wellness Plans Hospital & Accident Indemnity Insurance Employee Benefit Advocate & Employee Assistance Program ul> Disclaimer: The listed qualifications and requirements for each position are intended as guidelines. Mini-Circuits reserves the right to hire outside of these guidelines at Management's discretion. Mini-Circuits is an Equal Opportunity Employer and does not discriminate on the basis of actual or perceived age, race, creed, color, national origin, sexual orientation, military status, sex, disability, predisposing genetic characteristics, marital status, familial status, gender identity, gender dysphoria, pregnancy‑related condition, and domestic violence victim status or protected class characteristic, or any other protected characteristic as established by federal or state law. #J-18808-Ljbffr

Title: Systems Engineer Belong. Connect. Grow. with KBR! KBR's National Security Solutions team provides high-end engineering and advanced technology solutions to our customers in the intelligence and national security communities. In this position, your work will have a profound impact on the country's most critical role - protecting our national security. Why Join KBR? Innovative Projects: KBR's work is at the forefront of engineering, logistics, operations, science, program management, mission IT and cybersecurity solutions. Collaborative Environment: Be part of a dynamic team that thrives on collaboration and innovation, fostering a supportive and intellectually stimulating workplace. Impactful Work: Your contributions will be pivotal in designing and optimizing defense systems that ensure national security and shape the future of space defense. Position Summary: KBR is seeking a Systems Engineer to support the horizontal integration of multiple USAF open architecture programs and autonomy projects. You will help drive the development, simulation, maturation, and coordination of USAF open architecture capabilities; ensuring alignment across systems and enhancing mission effectiveness. Key Responsibilities: Assessments: Prototype and assess feasibility of horizontal integration efforts across open reference architectures and multiple projects Coordination: Coordinate experiments, assure complimentary lines of effort, and produce final leadership-level out briefs of experimentation results to inform horizontal integration decision making Risk Reduction: Break up scope of broad cross-cutting activities into prototype-based work to reduce risk and identify opportunities across open architectures and standards Client Engagement: Work with Government clients to understand the requirements and needs for integration Optimization: Analyze business and management challenges, recommend modifications to existing system designs, or develop new designs to maximize efficient use of data Analysis: Conduct analysis related to hardware, software, man-machine interfaces, and system-level requirements to deliver integrated IT solutions Work Environment: Location: On-site Travel: Minimal to Moderate Working Hours: Standard (8am-4pm-core hours) Qualifications: Required: Bachelor's degree in systems engineering, computer engineering, aerospace engineering, or related STEM degree program. 1 to 3 years' experience in Systems Engineering Experience with software architecture and development Experience with data modeling, test driven development, and mission planning Experience with collaborative software development in either open source or professional team environments. Active Secret DoW clearance with Top Secret eligibility Desired: Active Top Secret clearance Familiarity with modern software development tools, languages, and methodologies Knowledge of DoD open architectures such as OMS (Open Mission Systems) Ready to Make a Difference? If you're excited about making a significant impact in the field of space defense and working on projects that matter, we encourage you to apply and join our team at KBR. Let's shape the future together. KBR Benefits KBR offers a selection of competitive lifestyle benefits which could include 401K plan with company match, medical, dental, vision, life insurance, AD&D, flexible spending account, disability, paid time off, or flexible work schedule. We support career advancement through professional training and development. Belong, Connect and Grow at KBR At KBR, we are passionate about our people and our Zero Harm culture. These inform all that we do and are at the heart of our commitment to, and ongoing journey toward being a People First company. That commitment is central to our team of team's philosophy and fosters an environment where everyone can Belong, Connect and Grow. We Deliver - Together. KBR is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, disability, sex, sexual orientation, gender identity or expression, age, national origin, veteran status, genetic information, union status and/or beliefs, or any other characteristic protected by federal, state, or local law.