Requirements Engineer jobs at KBR - 11883 jobs

Plumbing Engineer (EIT or PE) Onsite in Memorial City Direct Hire with Benefits, PTO We're seeking a motivated Plumbing Engineer (EIT or PE) to join a collaborative MEP (Mechanical, Electrical, and Plumbing) engineering team. Revit and MEP experience are both required. Resumes without Revit and MEP will not be considered. ***If you're interested in this opportunity, please apply here or send your resume directly to *************************** --No Corp to Corp at this time, please. --All candidates must be able to work for any employer in the United States without current or future sponsorships needs. In this role, you'll contribute to designing innovative and sustainable plumbing systems for educational, commercial, and institutional projects. You'll gain hands-on experience working with senior engineers, learning the full design process-from concept to construction-while building a strong foundation for your professional growth. Key Responsibilities Assist in the design and documentation of plumbing systems, including domestic water, sanitary waste, storm drainage, and fire protection. Perform engineering calculations and support the production of AutoCAD and Revit drawings. Review shop drawings, RFIs, and submittals related to plumbing system design. Conduct field observations to verify installations and ensure alignment with design intent. Collaborate with cross-discipline teams to deliver high-quality, coordinated construction documents. Requirements Bachelor's degree in Mechanical Engineering or a related field. Successful completion of the Fundamentals of Engineering (F.E.) exam. Certified or eligible for certification as an Engineer-in-Training (EIT) or PE (Professional Engineer). Experience with Revit. Excellent attention to detail, organization, and problem-solving skills. Ability to manage multiple projects while collaborating effectively in a team environment. Familiarity with AutoCAD, Bluebeam, and Microsoft Office Suite. Working knowledge of plumbing and mechanical codes (Uniform Plumbing Code, NFPA standards). Prior internship or experience in an MEP consulting environment. Understanding of water distribution, drainage, gas, and fire protection systems. What We Offer: Competitive salary commensurate with experience. Comprehensive health insurance, 401(k), and paid holidays/PTO. Mentorship and professional development opportunities. Exposure to diverse and meaningful building projects. A collaborative, supportive team environment that values innovation and growth.

San Francisco Bay Area, California, United States Hardware Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than something - you'll add something.Do you love taking on big challenges that require exceptionally creative solutions? The Thermal team is responsible for all thermal aspects of highly collaborative, cross-functional design efforts. We are searching for an extraordinary engineer to help lead the definition and design of Apple products. You'll ensure all thermal objectives are met or surpassed from initial concept to design fruition and the user experience is optimized to surprise and delight our customers. Description You will be tasked with impacting product design decisions by providing reliable analysis and thermal insight. You'll define, guide thermal flow experiments to characterize materials, components, and systems. You'll drive architecture of next-generation cooling strategies for high-powered devices using analytical tools, CFD, and prototype testing. A strong sense of design ownership along with the ability to build consensus will help you drive technical challenges to conclusion. Additionally, you will lead technology investigations, design, implementation of thermal solutions and communicate status results to leadership. Minimum Qualifications 5+ years thermal design experience. M.S. in Mechanical Engineering or equivalent. Strong understanding of heat and fluid flow with the ability to apply this understanding to multi-disciplinary design problems. Excellent verbal and written communications skills. Deep technical and functional expertise in conduction, convection (natural and forced) and radiation, as well as numeric modeling techniques and concepts. Experience with both CFD and experimental techniques for design validation. Ability to clearly communicate complex technical material. Occasional domestic and international travel required. Preferred Qualifications Ph.D. in Mechanical Engineering with emphasis on Heat Transfer or Fluid Dynamics. 7+ years of thermal design experience. Deep knowledge of TIMs, heat sinks, heat pipes, vapor chambers, cold plates, pumps, and air movers for thermal mitigation, especially within a datacenter environment. Proven ability to lead high visibility programs. Ability to thrive in a fast-paced work environment. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $181,100 and $318,400, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant . Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

San Francisco Bay Area, California, United States Hardware The Wireless SoC Radio Team designs state‑of‑art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed‑signal blocks from RF front‑end amplifiers to data converters, including baseband filters, baseband and RF phase‑locked loops, crystal oscillators, and bandgap references. Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next‑generation of wireless technologies into high‑volume production in advanced CMOS technology nodes. Responsibilities Detailed transistor‑level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. Co‑work with designers on block level floorplanning. Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling. Minimum Qualifications BS and 3+ years of relevant industry experience. Preferred Qualifications Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub‑micron CMOS. Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. Solid understanding of RC delay, electromigration, and coupling. Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. Knowledge of CADENCE layout tools. Scripting skills in PERL or SKILL. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $141,800 and $258,600, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. Apple accepts applications to this posting on an ongoing basis. #J-18808-Ljbffr

A leading AI technology firm based in San Francisco is seeking GenAI Engineers at various levels to drive the development of innovative GenAI-powered products. This role involves shaping AI features, developing LLM technologies, and collaborating with cross-functional teams. Ideal candidates should have 2-8 years of ML engineering experience and proficiency in Python and TensorFlow/PyTorch. A competitive pay range of $166,000 to $210,250 USD is offered, along with comprehensive benefits. #J-18808-Ljbffr

A leading technology company is seeking a Machine Learning Engineer to specialize in Recommendations & Personalization. The role involves designing and deploying innovative recommendation systems and machine learning pipelines. Candidates should have a strong background in software engineering and significant experience with ML systems, particularly in personalization and ranking. This position offers a competitive salary range and comprehensive benefits, alongside opportunities for professional growth and stock options. #J-18808-Ljbffr

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. **Description** As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. **Minimum Qualifications** + BS and 3+ years of relevant industry experience. + FinFet experience. **Preferred Qualifications** + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of CADENCE layout tools. + Excellent communication skills. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200628172-0240 At Apple, we work every single day to craft products that enrich people's lives. In this highly visible role, you will take ownership of the ESD and Latch-Up requirements of all ICs developed by and for Apple. Your mission is to ensure the silicon is designed to meet Apple's ESD specifications and manufacturing requirements. The role involves working closely with our diverse teams within Apple as well as external vendors. Occasional travel might be required. Do you love working on challenges that no one has solved yet? Are you excited to build Apple's products that strive for the highest expectations of quality, innovation and efficiency? We have an opportunity for an especially innovative ESD Designer with strong fundamentals! We are looking forward to having you join our fast growing team and help us deliver on these challenges while enjoying an amazing culture where you lead your career! **Description** Work in a cross-functional team that delivers high quality on-chip IPs immune to ESD/EOS and latchup events. Ensure ESD robust designs with minimum cost to mission-mode functions. **Minimum Qualifications** + BS and 10+ years of relevant industry experience **Preferred Qualifications** + MS and 8+ years relevant industry experience. + Deep understanding of transistor device characteristics. + Solid understanding of models used for testing ESD, including HBM, CDM, MM and IEC-61000-4-2. + Knowledge of state-of-the-art ESD circuit design techniques and topologies. + Hands-on experience with design/layout EDA tools, including Virtuoso, Calibre, Allegro, etc. + Knowledge of ESD checking tools like PERC and Pathfinder. + Experience with Si processes used for high voltage, RF, or advanced ASICs. + Experience with ESD/LUP test and characterization equipment. + Strong initiative, collaboration, and ownership of responsibilities, productive, able to meet challenging deadlines. + Excellent written and verbal communication skills. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references. **Description** As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. **Minimum Qualifications** + BS and 10+ years of relevant industry experience. + FinFet experience. **Preferred Qualifications** + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of CADENCE layout tools. + Excellent communication skills. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide. **Description** You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies. **Minimum Qualifications** + BS with 3+ years of industry experience. + Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond) and proficiency with FinFET structures, guard-rings, deep N-wells, and PN junctions are required. + Familiarity with sophisticated process effects such as LOD, WPE, and DFM is critical. + Understanding trade-offs involving matching, parasitic effects, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up is vital. **Preferred Qualifications** + Experience in sophisticated DRC, ERC, LVS verification, and debugging. + Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus. + RF experience is helpful. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. **Description** As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs. **Minimum Qualifications** + Bachelors Degree + 3 Years of Experience. **Preferred Qualifications** + Strong fundamentals in the area of Digital design + Self-starter and highly motivated + Proficient in scripting languages (TCL and Perl) + Familiarity with ASIC design timing concepts + Exposure in STA tools (Primetime) is a plus + Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks + Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required + Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus + Ability to commnicate optimally across all internal groups Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

**Role Number:** 200*********** The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. **Description** As an RFIC Layout Designer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Apple's state-of-the-art radios and getting them into hundreds of millions of products. **Minimum Qualifications** + 5+ year minimum related experience required. + Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS. + High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology. + Knowledge of Cadence layout tools. **Preferred Qualifications** + Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing. + Solid understanding of RC delay, electromigration, and coupling. + Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE. + Excellent communication skills and able to work with cross-functional teams. + Scripting skills in PERL or SKILL. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (*********************************************************************************************** .

Are you passionate about advancing the boundaries of RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous iterations and enrich user experiences worldwide.You will lay out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits, verifying and refining layouts through simulation to meet design requirements. You will diagnose sophisticated verification (DRC/LVS) and PDK issues using Cadence and Calibre. Collaboration with engineering design and layout teams will be meaningful to understand design concepts, constraints, and opportunities for improvement. Upon identifying challenges, you will propose solutions to streamline layout tasks, collaborating with teams to specify and finalize methodologies.Experience in sophisticated DRC, ERC, LVS verification, and debugging. Prior experience in crafting custom layouts at the chip, block, and device levels, particularly for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs is a plus. RF experience is helpful.Array

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC Timing: Full chip and block level timing closure/constraints ownership throughout the entire project. You will be working with other specialists that are members of the SoC Design, SoC Design Verification, DFT, Architecture and Physical Design teams. Working with CAD and Flow teams to define and improve front-end design methodologies. Develop and maintain methodology and flows related to timing analysis. Strong fundamentals in the area of Digital design Familiarity with ASIC design timing concepts Proficient in scripting languages (TCL, Python and Perl) Exposure to STA tools (Primetime) , writing timing constraints and knowledge of timing corners / modes is a plus Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks Self-starter and highly motivated Ability to communicate optimally across all internal groups Bachelors Degree + 0 Years of Experience.

Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables.As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.Strong fundamentals in the area of Digital design Self-starter and highly motivated Proficient in scripting languages (TCL and Perl) Familiarity with ASIC design timing concepts Exposure in STA tools (Primetime) is a plus Familiarity with front end tools and methodologies such as Synthesis, Logic equivalence checks Familiarity in Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable but not required Knowledge of timing corners/modes, process variations and signal integrity related issues is a plus Ability to commnicate optimally across all internal groups Array

Job Category: Information Technology Time Type: Full time Minimum Clearance Required to Start: TS/SCI with Polygraph Employee Type: Regular Percentage of Travel Required: None Type of Travel: None * * * **The Opportunity:** consistent, repeatable, high-quality experience for users across all Mission environments. The Engineer will work with the customer to define their CMDB & Configuration Item (CI) needs, will train teams to deploy, configure, and ultimately troubleshoot their MID deployments, and provides support for the overall workload and execution of Operations and Maintenance (O&M) tasks on the production instance of ServiceNow. This position does not require shift work but may require being on-call on a scheduled rotation for call-in support and occasional off-hour assignments. In this role you will coordinate with Mission Partners, Service Providers, Service Owners, and Architects to design, implement, and configure ServiceNow Information Technology Operations Management (ITOM) capabilities, working on ServiceNow Discovery and ServiceNow mapping. **Responsibilities:** + In-depth knowledge of CMDB concepts, methodologies, and best practices.-Responsible for developing methods and strategies essential to realizing the Customer's Configuration Item (CI) Discovery and Enterprise Configuration Management Database (eCMDB) vision-Collaborates with Government Program Management Office (GPMO), System Owners, and technical points of contact to deploy MID Servers across 1200+ Systems, and communicate the status of those deployments to executive leadership-Serves as the CI Discovery Subject Matter Expert (SME) responsible for training System Custodian' technical teams to deploy, configure, and ultimately troubleshoot their MID deployments Proactively plans capacity of ServiceNow MID servers and maintains and configures appropriately.-Must be able to manage MID Server deployments for 20+ Systems and Technical Teams at any given time-Must be a self-motivated, self-learner, capable of researching and resolving complex/ multi-dimensional CI Discovery issues, regardless of technical platform Creates and maintains patterns, probes, and sensors to accommodate discovery requirements.-Works with the Solutions Architect, Configuration Management SMEs, and vendors to develop and recommend solutions to the government, System Owner, and System Custodian on any issues/concerns-Interacts and communicates with customers to rectify alerts and issues, escalates problems as required, and resolves significant matters by exercising independent judgment within established support practices.-Coordinates with deployment team for approved release packages and break-fix solutions on ServiceNow in accordance with Configuration, Change, and Release Management policies and procedures-Develops installation instructions and supporting documentation to affect system design deployments-Works with a team to provide technical input in the areas of system design, installation, configuration, tuning, capacity planning, troubleshooting, and problem resolution-Patches cloud servers and applications, configures software, responds to service outages, monitors system performance, and troubleshoots systems issues-Strong skills with MS Office tools (Excel, Word, Project, Visio) and SharePoint **Qualifications:** _Required:_ - An Active TS/SCI Clearance with Polygraph- Security+ or DoD 8570 IAT Level II Certification or be able to obtain certification within 3 months of hire- Bachelor's Degree in applicable field (computer science, engineering, cyber security, etc.) and 7+ years direct experience.- Experience with ServiceNow ITOM Discovery, CMDB, and Service Mapping capabilities- Excellent interpersonal and communication skills needed to work with business partners, engineering teams, and users requiring break fix actions- Strong analytical and strategic thinking skills with a service-oriented mindset- Team player with a strong willingness to participate and help others- Ability to prioritize in a fast-moving environment with ahigh sense of urgency and self-motivation _Desired:_ - Experience managing work tasks via ServiceNow- Experience with enterprise technologies such as Splunk and Amazon Cloud services- Experience with virtual infrastructure and containerization- ServiceNow Administrator experience- Asset Management experience- JavaScript/AngularJS experience- Splunk experience- RedHat Linux administration experience- Microsoft Windows Server technologies, specifically Active Directory experience- Scripting Skills such as Python, JavaScript, Bash, and/or PowerShell - **________________________________________________________________________________________** **What You Can Expect:** **A culture of integrity.** At CACI, we place character and innovation at the center of everything we do. As a valued team member, you'll be part of a high-performing group dedicated to our customer's missions and driven by a higher purpose - to ensure the safety of our nation. **An environment of trust.** CACI values the unique contributions that every employee brings to our company and our customers - every day. You'll have the autonomy to take the time you need through a unique flexible time off benefit and have access to robust learning resources to make your ambitions a reality. **A focus on continuous growth.** Together, we will advance our nation's most critical missions, build on our lengthy track record of business success, and find opportunities to break new ground - in your career and in our legacy. **Your potential is limitless.** So is ours. Learn more about CACI here. (************************************************ **________________________________________________________________________________________** **Pay Range** : There are a host of factors that can influence final salary including, but not limited to, geographic location, Federal Government contract labor categories and contract wage rates, relevant prior work experience, specific skills and competencies, education, and certifications. Our employees value the flexibility at CACI that allows them to balance quality work and their personal lives. We offer competitive compensation, benefits and learning and development opportunities. Our broad and competitive mix of benefits options is designed to support and protect employees and their families. At CACI, you will receive comprehensive benefits such as; healthcare, wellness, financial, retirement, family support, continuing education, and time off benefits. Learn more here (***************************************************** . The proposed salary range for this position is: $120,800 - $265,800 _CACI is_ _an Equal Opportunity Employer._ _All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, age, national origin, disability, status as a protected veteran, or any_ _other protected characteristic._

Ascentt is building cutting-edge data analytics & AI/ML solutions for global automotive and manufacturing leaders. We turn enterprise data into real-time decisions using advanced machine learning and GenAI. Our team solves hard engineering problems at scale, with real-world industry impact. We're hiring passionate builders to shape the future of industrial intelligence. Job Summary: We are seeking a motivated Junior BI Engineer to join our analytics team. The ideal candidate will be responsible for developing and maintaining business intelligence solutions, working closely with stakeholders to deliver actionable insights. This role involves building dashboards, writing SQL queries, supporting data models, and ensuring the accuracy and reliability of reporting solutions. Key Responsibilities: Develop and maintain BI dashboards and reports using tools such as Power BI or Tableau. Write, optimize, and maintain SQL queries to extract, clean, and analyze data from relational databases. Collaborate with business stakeholders to gather requirements and translate them into effective technical solutions. Support the design and implementation of data models, metrics, and KPIs. Assist in ETL processes and integrate data from multiple systems. Ensure accuracy, consistency, and quality of data and reporting deliverables. Participate in code reviews, QA testing, and documentation to maintain best practices and standards. Qualifications & Skills: Bachelor's degree in Computer Science, Information Systems, Data Analytics, or a related field. Hands-on experience with BI tools (Power BI, Tableau, or similar). Strong knowledge of SQL and relational databases. Basic understanding of ETL processes and data integration concepts. Good analytical and problem-solving skills with strong attention to detail. Ability to work collaboratively in a team environment and communicate effectively with stakeholders. Nice to Have: Exposure to cloud platforms (AWS, Azure, or GCP). Familiarity with version control (Git) and Agile methodologies. Knowledge of Python or R for data analysis.

A leading AI research company is seeking a privacy engineer in San Francisco. You will protect user data while ensuring AI system efficiency, employing techniques like differential privacy and federated learning. Responsibilities include designing privacy-preserving algorithms, investigating privacy-performance trade-offs, and developing documentation. Ideal candidates have experience with privacy technologies and deep learning. OpenAI promotes a diverse environment and offers relocation assistance. #J-18808-Ljbffr

A data consulting firm based in San Francisco is seeking a Palantir Foundry Consultant for a contract position. The ideal candidate should have strong experience in Palantir Foundry, SQL, and PySpark, with proven skills in data pipeline development and ETL automation. Responsibilities include building data pipelines, implementing interactive dashboards, and leveraging data analysis for actionable insights. This on-site role offers an excellent opportunity for those experienced in the field. #J-18808-Ljbffr

Title: CI/CD & Release Engineering SME Belong. Connect. Grow. with KBR! KBR's National Security Solutions team provides high-end engineering and advanced technology solutions to our customers in the intelligence and national security communities. In this position, your work will have a profound impact on the country's most critical role - protecting our national security. Why Join Us? Innovative Projects: KBR's work is at the forefront of engineering, logistics, operations, science, program management, mission IT and cybersecurity solutions. Collaborative Environment: Be part of a dynamic team that thrives on collaboration and innovation, fostering a supportive and intellectually stimulating workplace. Impactful Work: Your contributions will be pivotal in designing and optimizing defense systems that ensure national security and shape the future of space defense. Role summary KBR is seeking a highly experienced Senior Software Engineer to join our team in Beavercreek, OH. The ideal candidate will be a CI/CD & Release Engineering SME with a DoW Top Secret clearance and SCI eligibility. Key responsibilities Own the delivery pipeline for platform and simulation applications-connected and air‑gapped Implement repeatable, compliant CI/CD, artifact management, and promotion (dev→stage→prod), supporting canary/blue‑green rollouts and secure supply‑chain practices Design GitOps workflows (Argo CD/Flux) and CI pipelines (GitHub Actions/Tekton/Argo Workflows) for containers, Helm/Kustomize Build promotion pipelines with environment gates, automated tests, policy checks, and Istio traffic shifting (VirtualService/DestinationRule) Manage artifact registries, image relocation, and SBOM generation (CycloneDX/SPDX); implement SLSA‑aligned provenance Enable air‑gap packaging/delivery: bundle charts/images/manifests; automate offline installs/updates and verification Establish compliance automation: supply‑chain scanning, signing (cosign), CVE triage, audit trails Work Environment: Location: On-site/Hybrid Travel Requirements: 15% Working Hours: Standard Qualifications: Required: 12+ years of Software Engineering experience with 5-7+ years in DevSecOps/Release Engineering; strong Kubernetes CI/CD, GitOps, and Helm/Kustomize background Experience with policy-as-code (OPA/Gatekeeper/Kyverno) and secure pipeline orchestration Familiar with SBOMs, container signing, image mirroring/relocation; registry operations Active DoW Top Secret clearance with SCI eligibility Desired: Operating CI/CD in disconnected/secure networks; automated air‑gap workflows Performance‑aware rollouts, canary analysis, and automated rollback Demonstrated ability to meet DoD compliance controls Ready to Make a Difference? If you're excited about making a significant impact in the field of space defense and working on projects that matter, we encourage you to apply and join our team at KBR. Let's shape the future together. KBR Benefits KBR offers a selection of competitive lifestyle benefits which could include 401K plan with company match, medical, dental, vision, life insurance, AD&D, flexible spending account, disability, paid time off, or flexible work schedule. We support career advancement through professional training and development. Belong, Connect and Grow at KBR At KBR, we are passionate about our people and our Zero Harm culture. These inform all that we do and are at the heart of our commitment to, and ongoing journey toward being a People First company. That commitment is central to our team of team's philosophy and fosters an environment where everyone can Belong, Connect and Grow. We Deliver - Together. KBR is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, disability, sex, sexual orientation, gender identity or expression, age, national origin, veteran status, genetic information, union status and/or beliefs, or any other characteristic protected by federal, state, or local law.