Design Verification Engineer jobs at Synaptics - 89 jobs

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network‑on‑Chip (NoC), and cutting‑edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal‑based verification environments at both block and SoC‑level to achieve first‑pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre‑Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: Lead the verification of high‑speed Crypto, Network‑on‑Chip (NoC), cutting‑edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. Architect, develop, and use simulation and/or formal‑based verification environments at IP and SoC‑level. Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. Develop and execute comprehensive verification plans, including testbenches and test cases. Collaborate with design, architecture, and software teams to define and implement verification strategies. Utilize advanced verification methodologies, including UVM, formal verification, and assertion‑based verification. Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analysed and verified system‑level Performance and QoS (Quality of Service) requirements. Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. Require strong understanding of state of the art of verification techniques, including assertion and coverage‑driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high‑performance IP and/or VLSI designs is a plus. Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. Experience with gate‑level simulation, power‑aware verification is a plus. Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's “Responsible AI Policy” is available here. This posting is for an existing vacancy. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an “out of the box” thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle “how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power”. Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. Consult DV engineers in describing features, outlining test plans, and closing on coverage Assist DV engineers to debug functional, performance or power test failures Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading technology company in Santa Clara seeks an experienced ASIC Design Engineer specializing in GPU/ML Shader Core. In this role, you will define micro-architecture, implement RTL, and collaborate with various engineering teams. Ideal candidates will have experience in micro-architecture and an undergraduate degree in Computer Engineering or Electrical Engineering. Enjoy a vibrant culture that fosters innovation and teamwork, while pushing the boundaries of next-generation computing. This role does not offer visa sponsorship. #J-18808-Ljbffr

- Physical layout design including Synthesis, Place & Route, Physical verification, Static Timing Check, Power Verification, AC implementation, ... - Design and develop the overall architecture of the platform - Ensure the platform is scalable, flexible, and meets the performance requirements - Collaborate with related teams to finish design within defined schedule. - Working with team to achieve project. Qualifications - At least 5 years experience in semiconductor design, Physical Layout design. - Proven experience in platform architecture, design, and implementation - Solid knowledge in using EDA tool (Synopsys, Cadence, ...). - Experience with software development languages, such as C-Shell, Perl, Tcl or Python. - Good written and oral communication (in English) & interpersonal skills. - Strong team-oriented working and good relationship-building with others. - Good communication skills as well as problem solving skills. - A passion for working with platforms and a desire to contribute to the development Additional Information We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.' At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people's lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let's Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. #J-18808-Ljbffr

A technology company in San Jose is seeking a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs. The role requires expertise in RTL ownership, complex timing constraints, and EDA tools, alongside strong communication skills. Candidates should have a Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. This is a non-remote role requiring in-person presence, and does not offer visa sponsorship. #J-18808-Ljbffr

A leading semiconductor company in California is seeking a Design Verification Engineer to join a high-performance design team. The role involves developing verification environments, designing verification components, and analyzing simulation failures. Candidates should have over 12 years of experience and a Bachelor's degree in a relevant field. Strong knowledge of System Verilog and UVM is required. Competitive salary and benefits offered. #J-18808-Ljbffr

Hardware support specialist for NFC Point-Of-Sale, IoT and WireLess Charging domains Supporting FAEs and Tier1 customers over JIRA ticketing system by answering questions, conducting design reviews and evaluating prototypes Design PCBs with microcontrollers and NFC antennas for internal prototypes and for certified Evaluation Kits Develop full-scale NFC wireless charging solutions from Antenna to Battery Be TechLead and take ownership of customer projects and internal development programs Performing measurements with RF lab equipment (in-house and at external laboratories) Perform EMC tests and troubleshooting, maintain documentation repository Write and maintain application notes, articles and presentations Create technical trainings for customers and internal staff Qualifications You bring a MSc in Electrical Engineering and several years of experience in wireless communications and PCB design You are familiar with Altium Designer (a Renesas company) You have hands‑on skills for re‑work, bring‑up and troubleshooting using EE lab equipment You have solid EMC theory knowledge and practical problem‑solving skills You have skills with EE simulation tools like Cadence, LTSpice, Qucs and CST Studio You have experience in NFC/RFID protocols, standards and products You have basic skills for Firmware updates, interface sniffing and protocol debugging You are open for customer inputs, self‑reflective and self‑critical personality, good at talking and writing to customers You can work independently and as part of a team You are willing to share your expert know‑how within the team as well as with customers You have sound knowledge of English Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting‑edge technologies including self‑driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi‑billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi‑cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast‑growing data economy‑related markets such as infrastructure and data center and strengthening our presence the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what's next in electronics. Additional Information This position is subject to the Collective Agreement of the Electrical and Electronics Industry, employment group H (******************************************************************************* The monthly salary is paid 14 times a year. However, we offer a higher salary depending on your experience and qualifications. Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.' As the industry's leading expert in embedded processing with unmatched quality and system‑level know‑how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power‑efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.' At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people's lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people‑first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let's Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. #J-18808-Ljbffr

A leading tech company in Silicon Valley seeks a Staff Silicon Design Verification Engineer. In this role, you will lead verification efforts for advanced designs including high-speed Crypto and DRAM Controllers, utilizing cutting-edge technologies. Ideal candidates will have strong leadership skills, a background in verification methodologies, and experience with UVM and simulation tools. This position offers opportunities for professional growth and impacts the future of computing, aiming for first-pass silicon success. #J-18808-Ljbffr

A leading semiconductor solutions provider in San Francisco is seeking an experienced semiconductor design engineer. This key role involves physical layout design, developing platform architecture, and collaborating with teams to deliver projects within deadlines. The ideal candidate has over 5 years of relevant experience and is proficient in EDA tools and software development languages. This role promotes a flexible hybrid work environment. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Together, we advance your career. SMTS SoC Architect THE ROLE We are seeking a SoC Architect to join our adaptive SoC Architecture team. This role is pivotal in defining and driving architecture for next‑generation Adaptive SoCs, with Processor subsystems, Interconnect, AI, GPU, video processing pipelines, and memory systems. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems. You thrive in collaborative environments and bring a system‑level mindset to solving architectural challenges. You are passionate about performance, power, and scalability, and have a strong grasp of silicon design trade‑offs. You communicate effectively across engineering disciplines and influence architectural decisions with clarity and technical rigor. KEY RESPONSIBILITIES Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC Define and optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. Drive early‑stage architectural analysis, modeling, and specification development. Contribute to architectural innovation for Adaptive SoC Use‑cases in AI, GPU, video, and IO domains. Collaborate with planning, software and hardware cross‑functional teams to develop architecture solution. Collaborate with subsystem architects to ensure cohesive integration and system‑level performance. PREFERRED EXPERIENCE Proven experience in SoC architecture with Processor, Interconnects, and Memory subsystem. Expertise in AI accelerators, GPU integration, video processing pipelines, and IO subsystems. Expertise in SoC control bus design, reset architecture, clocking, and power management techniques. Experience with modeling and automation using Python, SystemC, or equivalent. Knowledge of advanced process technologies and associated design challenges. ACADEMIC & EXPERIENCE REQUIREMENTS BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. Demonstrated success in delivering high‑performance, low‑power SoC solutions. Benefits offered are described: AMD benefits at a glance. Equal Opportunity Employment AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a self‑motivated senior design engineer to be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry‑leading technologies to market. As a key contributor, you will focus on RTL design and validation of high‑speed interfaces such as chip‑to‑chip interconnect, both on system and on package, and highly configurable multi‑protocol PHYs. Continuous technical innovation to increase productivity, to heighten quality of results, and to foster career development is integral to the role. THE PERSON: You have a passion for digital design. You are a team player. You have strong analytical and problem‑solving skills. You are willing to learn and ready to take ownership of problems. KEY RESPONSIBILITIES: Perform RTL design of the digital components. Develop and validate timing constraints involving multiple clock domains while working with physical design to harden IP. Help lead and mentor other engineers to achieve project goals and organizational growth. Work with a functional (design) verification team to meet coverage and quality standards. Analyze/fix lint and CDC/RDC errors of the components. Guarantee quality/timely deliverables meeting project's schedule. Help to improve and automate design process. Support post‑silicon product bring‑up/debug. PREFERRED EXPERIENCE: Strong experience in designing digital components for high performance, low power SOC/FPGA. Design of digital circuits and components using Verilog/System Verilog. Creating and maintaining of timing constraints for complex multi‑clock designs. Debugging in digital and mixed‑signal simulation environment. Power optimization of digital designs. Multi‑clock domain designs. Experience/knowledge of high‑speed SerDes/Physical layer is a plus. Logic synthesis, timing closure, logical equivalence checking and ECOs. Scripting languages such as Perl, Tcl, or Python. Collaboration with verification team. Excellent verbal and interpersonal communication skills. Excellent technical communications. Ability to produce technical documentation. Exhibit strong ownership of tasks and responsibilities. ACADEMIC CREDENTIALS: Bachelors or Masters degree in Electrical Engineering with relevant industry experience. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading semiconductor company is looking for a Hardware Support Specialist to provide support for NFC Point-Of-Sale and IoT projects. The role involves designing PCBs, developing wireless charging solutions, and leading customer projects. Candidates should have a Master's in Electrical Engineering and expertise in PCB design and wireless communications. The company offers a flexible hybrid work model and fosters a diverse and inclusive work environment. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Senior Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: * Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, DDR5) designs, ensuring the highest standards of quality and performance. * Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. * Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. * Develop and execute comprehensive verification plans, including testbenches and test cases. * Collaborate with design, architecture, and software teams to define and implement verification strategies. * Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. * Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: * Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. * Proven track record on driving strategies and successful verification execution of NoC, Crossbar switches, analyzed and verified system-level Performance and QoS (Quality of Service) requirements. * Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. * Require strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. * Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. * Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. * Experience with gate-level simulation, power-aware verification is a plus. * Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: * BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success. THE PERSON: The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality. Key Responsibilities: * Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance. * Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level. * Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs. * Develop and execute comprehensive verification plans, including testbenches and test cases. * Collaborate with design, architecture, and software teams to define and implement verification strategies. * Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification. * Mentor and guide junior engineers, fostering a collaborative and innovative team environment. PREFERRED EXPERIENCE: * Proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs. * Experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. * Strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus. * Familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management. * Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus. * Experience with gate-level simulation, power-aware verification is a plus. * Experience with silicon debug at the tester and board level, is a plus. ACADEMIC CREDENTIALS: * BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science. This role is not eligible for visa sponsorship. #LI-CJ2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative Design Verification (DV) engineer to join our growing PLL team. As a key contributor, you will be part of a leading team that drives and improves AMD's ability to deliver the highest quality, industry-leading technologies to the market. The Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: * The successful candidate will possess: * Excellent analytical and critical thinking skills along with attention to details * Must be an initiative-taker, able to drive tasks independently and efficiently to completion * Strong/effective communication skills * Enthusiastic team-first mentality * Ability to provide mentorship and guidance to junior engineers * Relevant academic background (M.Sc. degree preferred) and at least 8 years of progressive experience KEY RESPONSIBILITIES: * Analyze complex verification and digital design problems and propose verification / micro-architecture solutions * Develop RTL and Firmware validation. * Drive/develop ASIC verification flows and scripts. * Create Verification architecture. * Work with the RTL Design team to ensure functional correctness and coverage. * Support silicon bring-up and diagnostics. * Support Post-silicon debug, root cause bug, provide solution or workaround. PREFERRED EXPERIENCE: * Proven experience in design verification from specification to successful silicon. * Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES. * Experience in designs with multiple power domains. * Experience in designs with multiple clock domains. * Experience in behavior modeling for Analog Circuits. * Experience in industry-standard ASIC CAD tools for verification, simulation, synthesis, STA, CDC, UPF, power estimation, etc. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: * Folsom, CA This role is not eligible for visa sponsorship. #LI-SL3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available. We are seeking a Design Verification Engineer to join our talented team. Supporting and ensuring IP quality through verification processes. THE PERSON: The successful candidate will play a key role in developing verification strategies, and collaborating across departments to ensure the highest quality standards. KEY RESPONSIBILITIES: * Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc.. * Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies. * Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations. * Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities. PREFERRED EXPERIENCE: * Design verification and simulation, model checking, and theorem proving applied to complex IP or systems. * Proficiency in design verification tools * Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python). ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA This role is not eligible for visa sponsorship #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. You will participate in design verification methodology definition as well as contribute to design verification infrastructure that facilitates maximum re-use of components, improves productivity, and guarantees to the maximum extent possible, bug-free designs. THE PERSON: You have a passion for digital design and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems KEY RESPONSIBILITIES: * Collaborate with architects, hardware and firmware engineers to understand the features to be verified * Take ownership of different verification tasks * Define test plans, test benches, and tests using System Verilog and UVM * Debug RTL simulations and work with HW and FW development teams to verify fixes * Review functional and code coverage metrics to meet the coverage requirements * Develop and improve existing verification flows and environments * Provide technical support to other teams PREFERRED EXPERIENCE: * Proficient in IP level ASIC verification * Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills * Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE) * Working knowledge of Formal Verification methods and apps ( FPV, CC, Sequence equivalence, etc.) * Proficient in debugging firmware and RTL code using simulation tools * Proficient in using UVM testbenches and working in Linux and Windows environments * Experienced with Verilog, System Verilog, C, and C++ * Developing UVM based verification frameworks and testbenches, processes and flows * Automating workflows in a distributed compute environment. * Good understanding and hands-on experience in the UVM concepts and SystemVerilog language * Good to have : prior experience with USB / PCIE / UFS Controllers. ACADEMIC CREDENTIALS: * Bachelors or Masters degree in Computer Engineering/Electrical Engineering LOCATION: Santa Clara, Folsom, CA #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. : The ASIC Product Division in Broadcom, a leading supplier of state-of-the-art SoC and embedded IP, is looking for qualified individuals to work in SoC and IP development programs. The candidate will be joining a high performance design team responsible for state-of-the-art subsystem development to meet customer requirements. The engineer will be responsible for a variety of advanced verification tasks such as: verification environment development using modern verification techniques (System Verilog and UVM); designing verification components such as UVM agents, and behavioral models; implementing coverage and assertions using System Verilog; and developing random & directed test cases against the specification. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing coverage results. Candidate must be a highly productive individual contributor with a demonstrated technical capability in system and sub-block level verification. Job Requirements: A Bachelor's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent 12+ year's relevant industry work experience. Experience in verifying designs at system level and block level. Fluent knowledge of RTL verification methodologies including System Verilog. Strong experience in ASIC design verification flows and DV methodologies Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills. Strong and independent design debugging capability. Strong verbal and written communication skills. Must be comfortable working in a team environment with verification team and design team members. Demonstrated ability to analyze and resolve complex verification trade-off scenarios. Must have legal authorization to work in the US The candidate should have expertise in some (or preferably all) of the following areas: Experience with hardware design and debug, C++/SystemC and other programming languages are a strong plus. Experience working with Emulators and FPGA based prototyping is a plus. Familiarity with overall chip design methodologies and tools Knowledge of CPU, DDR, Bus Protocol, Network Protocol or DSP design preferred Additional Job Description: Compensation and Benefits The annual base salary range for this position is $141,300 - $226,000 This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence. Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law. If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring multiple physical blocks and over 300 clock domains. The candidate's responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred. THE PERSON: High energy candidates with strong written and verbal communication skills, and structured, well-organized work habits will be successful. Team and goal oriented are essential. KEY RESPONSIBILITIES: * Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff * Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency. * Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA checks. * collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows. * Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts) PREFERRED EXPERIENCE: * Worked with EDA tools that enable RTL quality checks * Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. * Experience with analyzing the timing reports and identifying both the design and constraints related issues. * Ability to multitask, grasp new flows/tools/ideas. * Experience in improving the methodologies. * Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. * Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT) * Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters * Strong analytical and problem-solving skills ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: San Jose, CA This role is not eligible for visa sponsorship. #LI-DW1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.