Principal Engineer jobs at Philips - 669 jobs

A leading technology company in California seeks an IP Logic Design Engineer with a Bachelor's degree in relevant fields and at least 3 years of experience in IP design. The role includes designing, integrating, and validating silicon solutions while collaborating with architecture teams. Preferred qualifications include experience with scripting, hardware validation, and industry protocols. This position allows for remote work with competitive compensation ranging from $164,470 to $232,190 USD annually. #J-18808-Ljbffr

A leading technology firm in Santa Clara is seeking a passionate Principal Hardware Engineer to lead product performance and power initiatives. This pivotal role requires extensive experience in silicon power management, where you'll architect advanced power features and collaborate with multi-functional teams to deliver cutting-edge products. Ideal candidates have over 15 years of experience, a strong educational background, and a deep understanding of market dynamics. The position offers a competitive salary and the opportunity to drive innovation in the technology industry. #J-18808-Ljbffr

A leading technology company in California is seeking a Senior Mask Layout Design Engineer to perform physical layout for digital and mixed-signal functions. You'll collaborate with multi-disciplinary teams and have a significant role in mentoring junior mask designers. Ideal candidates should have a BS in Electrical Engineering and over 7 years of layout design experience with expertise in Cadence tools. This position offers a competitive salary and a hybrid work model. #J-18808-Ljbffr

A leading technology company is seeking a GPU Physical Design Engineer to drive advanced clocking solutions. The role involves high-speed clock distribution and collaboration with cross-functional teams. Applicants should have a Bachelor's degree with significant industry experience, strong skills in circuit simulations, and experience in SOC Clock Implementation. This position offers competitive compensation and a hybrid work model allowing flexibility between on-site and off-site work. #J-18808-Ljbffr

# **Welcome!**## .# **Job Details:**## :Job Description**Do Something Wonderful!**Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.or the links below!**WHO WE ARE:**We are a Custom IP and Silicon engineering team part of Intel's Silicon Engineering Group. The team works on design and verification of cutting edge IP and SoCs geared towards Intel's advanced Data center and AI SoCs. We look to drive major technological and methodological advancements across multiple areas of IP and SoC Design and Verification, looking to set a high bar across the organization and ensure that Intel has a competitive product in the market.**WHO YOU ARE:**As an IP Logic Design Engineer your responsibilities will include but are not limited to:* Designing and/or integrating IP for Intel's Custom Silicon solutions.* You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation.* Creating a design to produce key assets that help improve product KPIs for discrete graphics products.* Working with SoC Architecture and platform architecture teams to establish silicon requirements.* Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.* Creating micro architectural specification document for the design.* Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.* Driving vendor's methodology to meet world class silicon design standards.* Architecting area and power efficient low latency designs with scalabilities and flexibilities.* Power and Area efficient RTL logic design and DV support.* Running tools to ensure lint-free and CDC/RDC clean design, VCLP.* Synthesis and timing constraints.* Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience- or -Master's degree in the same fields with 2+ years of relevant experience- or -PhD in the same fields.Relevant work experience should be of the following:* Experience with complex IP/ASIC/SOC Design Implementation.* Experience in system and processor architecture.* Experience with System Verilog/SOC development environment.Preferred Qualifications:* Experience in scripting languages (i.e. PERL, TCL, or Python).* Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).* Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.* Experience in leading small team of engineers.* Experience with Industry standard protocols (i.e. PCIE, USB, DDR, etc).* Experience with interaction of computer hardware with software.* Experience with Low power/UPF implementation/verification techniques.* Experience with Formal verification techniques.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:Virtual US## Additional Locations:## Business group:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. \* Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 12/31/2027\*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr

A leading technology firm is seeking an IP Logic Design Engineer to design and integrate IP for custom silicon solutions. The role requires a Bachelor's degree in a relevant field with 3+ years of experience or a Master's with 2+ years. Key responsibilities include architecture and design implementation, working with cross-functional teams, and vendor collaboration. Competitive compensation, with an annual salary range of $164,470-232,190, is offered along with a strong benefits package. #J-18808-Ljbffr

# **Welcome!**## .GPU Physical Design Engineer page is loaded## GPU Physical Design Engineerlocations: US, California, Folsom: US, California, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR0279213# **Job Details:**## Job Description:Are you interested in working in a fast-paced, leading-edge environment with endless possibilities of innovating and learning, then our Graphics Hardware IP Team (GHI) team has an opportunity for you. In GHI we are passionate about delivering best-in-class visual experiences that enable users to immerse themselves in a new visual future. Within GHI you will be part of a Special Circuits Horizontal team that is responsible for local and global clocking of large designs like GFX Imaging processors, Peripheral subsystems like PCIe, Type-C, Display, Media and SOCs etc. We are looking for Graphics Hardware Clocking/Engineer to join the team.**The primary responsibilities for this role will include, but are not limited to:*** Ownership of complex highspeed global and local clock distribution network to meet the Power and Performance targets of these differentiating designs.* Work with Architects, PnP and Execution teams to identify right solutions in a timely manner.## **Qualifications:****A successful candidate will have proven experience demonstrating the following skills and behavioral traits:*** Team player with good problem-solving skills.* Strong written and verbal communication skills.**Minimum Qualifications**:Minimum qualifications are required to be initially considered for this position.* Bachelor's in Electrical/ Electronics/Computer Engineering, Computer Science or related field with at least 10 years of industry experience. Or a Master's degree in the same fields with at least 8 years of industry experience.* Advanced knowledge of Spice level circuit simulations.* Advanced experience in global and local clocking topologies.* 6+ years of hands on SOC Clock Implementation experience.* Basic understanding of RV and FEV flows.* Basic Scripting knowledge.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, California, Folsom## Additional Locations:US, California, Santa Clara## Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Benefits:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:Annual Salary Range for jobs which could be performed in the US: $161,230.00-227,620.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr

A technology industry leader in California is seeking a Product Definition Engineer to evaluate and optimize pre-production silicon. The successful candidate will work with multi-functional teams, driving new feature initiatives and designing performance-critical product features. Ideal candidates will have significant engineering experience and collaborative skills. The role offers a salary range of 168,000 - 264,500 USD depending on level, alongside equity and benefits. #J-18808-Ljbffr

NVIDIA is seeking an outstanding engineer in conversational AI to join our AI for Games team. We are developing next-generation gaming solutions enriched with AI Assistants, Actors, and Agents, and we are looking for outstanding engineers to help us achieve this vision. If you are passionate about generative AI, language models, conversational pipelines, and their applications in games, this is the opportunity for you. Collaborating with other teams across the company, you will productize promising research and develop new features through your own work. What you'll be doing: Use AI to solve product challenges in gaming and other interactive experiences. Build upon the latest research to create world-class conversational pipelines for AI assistants and agents. Improve and fine-tune language models and retrieval-augmented generation solutions for accuracy and performance. Build prototypes to demonstrate real-life applications of your ideas and to accelerate productization. Collaborate with NVIDIA's internal and external teams, including AI/DL researchers, hardware architects, and software engineers. Participate in technology transfers to and from teams across NVIDIA. What we need to see: PhD or Master's degree in Computer Science/Engineering, Machine Learning, AI, or related fields; or equivalent experience. 12+ years of work experience with last 5+ years focused on language models, AI assistants, and agents. Proficiency in C, C++, and Python, with the ability to write high-performance production code. Experience with GPU programming, CUDA, and system optimizations is a significant plus. A track record of proven research excellence, demonstrated through presentations, demos, or publications at leading venues such as GDC, ICCV/ECCV, SIGGRAPH, or other research artifacts such as software projects or significant product development. AI-powered machines can learn, reason, and interact with people, thanks to GPU deep learning. We offer competitive salaries and great benefits as a top tech employer with leading talent. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 272,000 USD - 431,250 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 13, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA is looking for engineers for our core AI Frameworks (Megatron Core and NeMo Framework) team to design, develop and optimize diverse real world workloads. Megatron Core and NeMo Framework are open-source, scalable and cloud-native frameworks built for researchers and developers working on Large Language Models (LLM) and Multimodal (MM) foundation model pretraining and post-training. Our GenAI Frameworks provide end-to-end model training, including pretraining, reasoning, alignment, customization, evaluation, deployment and tooling to optimize performance and user experience. In this critical role, you will expand Megatron Core and NeMo Framework's capabilities, enabling users to develop, train, and optimize models by designing and implementing the latest in distributed training algorithms, model parallel paradigms, model optimizations, defining robust APIs, meticulously analyzing and tuning performance, and expanding our toolkits and libraries to be more comprehensive and coherent. You will collaborate with internal partners, users, and members of the open source community to analyze, design, and implement highly optimized solutions. What you'll be doing: Develop algorithms for AI/DL, data analytics, machine learning, or scientific computing Contribute and advance open source Megatron Core and NeMo Framework Solve large-scale, end-to-end AI training and inference challenges, spanning the full model lifecycle from initial orchestration, data pre-processing, running of model training and tuning, to model deployment. Work at the intersection of compter-architecture, libraries, frameworks, AI applications and the entire software stack. Innovate and improve model architectures, distributed training algorithms, and model parallel paradigms. Performance tuning and optimizations, model training and finetuning with mixed precision recipes on next-gen NVIDIA GPU architectures. Research, prototype, and develop robust and scalable AI tools and pipelines. What we need to see: MS, PhD or equivalent experience in Computer Science, AI, Applied Math, or related fields and 10+ years of industry experience. Experience with AI Frameworks (e.g. PyTorch, JAX), and/or inference and deployment environments (e.g. TRTLLM, vLLM, SGLang). Proficient in Python programming, software design, debugging, performance analysis, test design and documentation. Consistent record of working effectively across multiple engineering initiatives and improving AI libraries with new innovations. Strong understanding of AI/Deep-Learning fundamentals and their practical applications. Ways to stand out from the crowd: Hands-on experience in large-scale AI training, with a deep understanding of core compute system concepts (such as latency/throughput bottlenecks, pipelining, and multiprocessing) and demonstrated excellence in related performance analysis and tuning. Expertise in distributed computing, model parallelism, and mixed precision training Prior experience with Generative AI techniques applied to LLM and Multi-Modal learning (Text, Image, and Video). Knowledge of GPU/CPU architecture and related numerical software. Contributions to open source deep learning frameworks. NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people on the planet working with us. If you're creative and autonomous, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 272,000 USD - 431,250 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 13, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

**Introduction** A career in IBM Software means you'll be part of a team that transforms our customer's challenges into industry-leading solutions. We are an infinitely curious team, always seeking new possibilities, and dedicated to creating the world's leading AI-powered, cloud-native software solutions. Our renowned legacy creates endless global opportunities for our network of IBMers. We are a team of deep product experts, ensuring exceptional client experiences, with a focus on delivery, excellence, and obsession over customer outcomes. This position involves contributing to HashiCorp's offerings, now part of IBM, which empower organizations to automate and secure multi-cloud and hybrid environments. You will join a team managing the lifecycle of infrastructure and security, enhancing IBM's cloud solutions to ensure enterprises achieve efficiency, security, and scalability in their cloud journey. **Your role and responsibilities** The Principal Engineer for Terraform Core Platform and Providers is a senior technical leadership position tasked with solving the most ambitious, complex technical and organizational challenges related to the foundation of Terraform's open source project and its provider ecosystem. You will act as a force multiplier, operating with an intentionally broad and flexible mandate to define and guide the evolution of the Terraform Core engine, the configuration language (HCL), the state management system, and the Provider Protocol This role requires a blend of deep domain expertise in infrastructure-as-code (IaC) principles, highly scalable distributed systems, and the ability to define the technical standards for millions of Terraform users and thousands of integrations Key Responsibilities As a Principal Engineer, your engagement will be dynamic, utilizing the six roles defined in the Principal Engineer Engagement Framework (IPG). Your core responsibilities, mapped to the engagement model, include: Role Category Focus Area Description Setting Strategic Direction (Sponsor & Catalyst) Core Engine Strategy Lead and own the delivery and architectural definition of major shifts in Terraform's core functionality, such as new language features, provider extensibility models, or cross-product standards. Drive new, ambiguous ideas for core performance improvements or architectural refactoring from concept to organizational buy-in. Providing Architectural Guidance (Guide & Advisor) Protocol and API Design Serve as a deep domain expert on Terraform's internals, providing sustained, ongoing architectural guidance to multiple Core and Provider teams. Produce exemplary technical artifacts and RFCs that define the future of the Provider Protocol and Terraform's interaction model. Ensuring Execution Quality (Catcher & Participant) Stability and Performance Quickly analyze and rescue troubled projects related to core stability, state management bugs, or performance regressions under tight deadlines. Actively contribute hands-on when necessary, engaging in coding, detailed design reviews, and unsticking highly complex technical blockers within the Terraform CLI. **Required technical and professional expertise** * Experience: Extensive experience in software development, architecture, and distributed systems, with a proven track record of shipping complex, large-scale projects. * Technical Depth: Deep expertise in systems programming (e.g., Go), compiler design or language parsing (e.g., HCL), and low-level IaC concepts, including state management and distributed consensus patterns. * Leadership: Demonstrated ability to lead technical strategy, mentor senior engineers, and influence product and engineering leadership across multiple teams. * Communication: Exceptional communication skills, capable of translating complex technical concepts into clear, strategic roadmaps for both technical and non-technical audiences. **Preferred technical and professional experience** * Familiarity with HashiCorp/IBM products and services IBM is committed to creating a diverse environment and is proud to be an equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

**Introduction** A career in IBM Software means you'll be part of a team that transforms our customer's challenges into industry-leading solutions. We are an infinitely curious team, always seeking new possibilities, and dedicated to creating the world's leading AI-powered, cloud-native software solutions. Our renowned legacy creates endless global opportunities for our network of IBMers. We are a team of deep product experts, ensuring exceptional client experiences, with a focus on delivery, excellence, and obsession over customer outcomes. This position involves contributing to HashiCorp's offerings, now part of IBM, which empower organizations to automate and secure multi-cloud and hybrid environments. You will join a team managing the lifecycle of infrastructure and security, enhancing IBM's cloud solutions to ensure enterprises achieve efficiency, security, and scalability in their cloud journey. **Your role and responsibilities** The Principal Engineer for Terraform Core Platform and Providers is a senior technical leadership position tasked with solving the most ambitious, complex technical and organizational challenges related to the foundation of Terraform's open source project and its provider ecosystem. You will act as a force multiplier, operating with an intentionally broad and flexible mandate to define and guide the evolution of the Terraform Core engine, the configuration language (HCL), the state management system, and the Provider Protocol This role requires a blend of deep domain expertise in infrastructure-as-code (IaC) principles, highly scalable distributed systems, and the ability to define the technical standards for millions of Terraform users and thousands of integrations Key Responsibilities As a Principal Engineer, your engagement will be dynamic, utilizing the six roles defined in the Principal Engineer Engagement Framework (IPG). Your core responsibilities, mapped to the engagement model, include: Role Category Focus Area Description Setting Strategic Direction (Sponsor & Catalyst) Core Engine Strategy Lead and own the delivery and architectural definition of major shifts in Terraform's core functionality, such as new language features, provider extensibility models, or cross-product standards. Drive new, ambiguous ideas for core performance improvements or architectural refactoring from concept to organizational buy-in. Providing Architectural Guidance (Guide & Advisor) Protocol and API Design Serve as a deep domain expert on Terraform's internals, providing sustained, ongoing architectural guidance to multiple Core and Provider teams. Produce exemplary technical artifacts and RFCs that define the future of the Provider Protocol and Terraform's interaction model. Ensuring Execution Quality (Catcher & Participant) Stability and Performance Quickly analyze and rescue troubled projects related to core stability, state management bugs, or performance regressions under tight deadlines. Actively contribute hands-on when necessary, engaging in coding, detailed design reviews, and unsticking highly complex technical blockers within the Terraform CLI. **Required technical and professional expertise** * Experience: Extensive experience in software development, architecture, and distributed systems, with a proven track record of shipping complex, large-scale projects. * Technical Depth: Deep expertise in systems programming (e.g., Go), compiler design or language parsing (e.g., HCL), and low-level IaC concepts, including state management and distributed consensus patterns. * Leadership: Demonstrated ability to lead technical strategy, mentor senior engineers, and influence product and engineering leadership across multiple teams. * Communication: Exceptional communication skills, capable of translating complex technical concepts into clear, strategic roadmaps for both technical and non-technical audiences. **Preferred technical and professional experience** * Familiarity with HashiCorp/IBM products and services IBM is committed to creating a diverse environment and is proud to be an equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

**Introduction** A career in IBM Software means you'll be part of a team that transforms our customer's challenges into industry-leading solutions. We are an infinitely curious team, always seeking new possibilities, and dedicated to creating the world's leading AI-powered, cloud-native software solutions. Our renowned legacy creates endless global opportunities for our network of IBMers. We are a team of deep product experts, ensuring exceptional client experiences, with a focus on delivery, excellence, and obsession over customer outcomes. This position involves contributing to HashiCorp's offerings, now part of IBM, which empower organizations to automate and secure multi-cloud and hybrid environments. You will join a team managing the lifecycle of infrastructure and security, enhancing IBM's cloud solutions to ensure enterprises achieve efficiency, security, and scalability in their cloud journey. **Your role and responsibilities** The Principal Engineer for Terraform Core Platform and Providers is a senior technical leadership position tasked with solving the most ambitious, complex technical and organizational challenges related to the foundation of Terraform's open source project and its provider ecosystem. You will act as a force multiplier, operating with an intentionally broad and flexible mandate to define and guide the evolution of the Terraform Core engine, the configuration language (HCL), the state management system, and the Provider Protocol This role requires a blend of deep domain expertise in infrastructure-as-code (IaC) principles, highly scalable distributed systems, and the ability to define the technical standards for millions of Terraform users and thousands of integrations Key Responsibilities As a Principal Engineer, your engagement will be dynamic, utilizing the six roles defined in the Principal Engineer Engagement Framework (IPG). Your core responsibilities, mapped to the engagement model, include: Role Category Focus Area Description Setting Strategic Direction (Sponsor & Catalyst) Core Engine Strategy Lead and own the delivery and architectural definition of major shifts in Terraform's core functionality, such as new language features, provider extensibility models, or cross-product standards. Drive new, ambiguous ideas for core performance improvements or architectural refactoring from concept to organizational buy-in. Providing Architectural Guidance (Guide & Advisor) Protocol and API Design Serve as a deep domain expert on Terraform's internals, providing sustained, ongoing architectural guidance to multiple Core and Provider teams. Produce exemplary technical artifacts and RFCs that define the future of the Provider Protocol and Terraform's interaction model. Ensuring Execution Quality (Catcher & Participant) Stability and Performance Quickly analyze and rescue troubled projects related to core stability, state management bugs, or performance regressions under tight deadlines. Actively contribute hands-on when necessary, engaging in coding, detailed design reviews, and unsticking highly complex technical blockers within the Terraform CLI. **Required technical and professional expertise** * Experience: Extensive experience in software development, architecture, and distributed systems, with a proven track record of shipping complex, large-scale projects. * Technical Depth: Deep expertise in systems programming (e.g., Go), compiler design or language parsing (e.g., HCL), and low-level IaC concepts, including state management and distributed consensus patterns. * Leadership: Demonstrated ability to lead technical strategy, mentor senior engineers, and influence product and engineering leadership across multiple teams. * Communication: Exceptional communication skills, capable of translating complex technical concepts into clear, strategic roadmaps for both technical and non-technical audiences. **Preferred technical and professional experience** * Familiarity with HashiCorp/IBM products and services IBM is committed to creating a diverse environment and is proud to be an equal-opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, gender, gender identity or expression, sexual orientation, national origin, caste, genetics, pregnancy, disability, neurodivergence, age, veteran status, or other characteristics. IBM is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. As a Senior Content Pipeline Engineer, you will drive the design and productization of content and data pipelines, SDKs, and APIs that power next‑generation experiences for our platforms (physical AI, robotics, SDG, etc.), and partners. You will operate across multiple teams and initiatives, helping transform technology into robust, developer‑friendly solutions used at scale. What you'll be doing: Lead and coordinate multiple engineering initiatives and workstreams related to content pipelines, tools, and runtime integration. Architect, implement, and productize SDKs, APIs, Blueprints, and reference pipelines to make complex workflows reliable, scalable, and easy for external developers to adopt. Collaborate closely with internal product, platform, and research teams to translate prototype technology into production‑quality developer offerings. Work directly with Product Managers, Developer Relations, and Solution Architects to understand external partner and customer requirements and feed them into the roadmap. Define technical standards and documentation for content ingestion, transformation, validation, and deployment. Build high‑quality, maintainable software with a focus on performance, adaptability, and observability in production environments. Provide technical leadership and mentorship to engineering teams, guiding design reviews, code reviews, and planning. Drive project execution end‑to‑end: requirements gathering, scoping, planning, risk management, and cross‑team alignment. Partner with robotics and simulation teams (where applicable) to ensure pipelines meet real‑time, safety, and reliability requirements for robotic systems. What we need to see: B.S. (or equivalent experience) with 8+ years of professional software development experience in production environments. Strong programming skills in C++, Python, USD, validated experience building robust libraries, tools, or SDKs. Experience crafting and shipping software systems, ideally involving data or content pipelines, asset workflows, or engine/tooling integration. Experience coordinating work across teams, with strong project management skills (planning, prioritization, execution tracking). Track record of working with external team members (partners, customers, or developers) to capture requirements and deliver solutions that meet real‑world needs. Ways To Stand Out From The Crowd: Background in robotics, simulation, or real‑time systems (e.g., experience with robotic software stacks, sim‑to‑real workflows, or NVIDIA robotics platforms like Jetson or Isaac). Experience building and productizing content or data pipelines for game engines, 3D tools, or digital twins. Familiarity with NVIDIA SDKs, APIs, or developer tools, and prior collaboration with DevRel or solutions engineering teams. Experience leading engineering teams or large multi‑stakeholder initiatives in a senior or tech‑lead capacity. Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family *********************** Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 270,250 USD for Level 4, and 200,000 USD - 322,000 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 25, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. **Key Responsibilities** **Memory IP Technical Support & Integration** + Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues + Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution + Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance **Technical Content Development & Training** + Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams + Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs + Develop best practice guidelines for memory integration across advanced process technologies and customer applications **Memory Design Methodology & Problem Solving** + Lead debugging and problem-solving activities in collaborative team environments + Provide technical expertise on memory compiler design, generation, and optimization + Support customers through complex memory design challenges and advanced integration requirements + Drive methodology improvements to enhance memory design productivity and reliability **Customer Engagement & Technical Excellence** + Deliver customer-facing technical support with focus on memory design and integration solutions + Ensure maximum customer satisfaction through expert guidance on memory IP implementation + Support aerospace, defense, and government customers with specialized memory requirements and security considerations **Core Competencies** + Self-driven and results-oriented with capability to effectively manage multiple complex tasks + Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates **Minimum Qualifications** + US Citizenship required + Ability to obtain a US Government Security Clearance + Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study + 3+ years of experience with Memory design or Memory Compiler development and implementation **Preferred Qualifications:** + Active US Government Security Clearance with a minimum of Secret level + Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study + Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles + Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification + Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST + Experience with IP development is a strong plus + Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus + Experience in ASIC or SoC development **What We Offer** + Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications + Direct customer engagement and technical leadership in advanced memory design + Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio + Competitive compensation + Professional development in memory design methodologies and foundry services + Direct impact on national security through advanced memory semiconductor solutions **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Arizona, Phoenix **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. Key Responsibilities Memory IP Technical Support & Integration * Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues * Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution * Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance Technical Content Development & Training * Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams * Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs * Develop best practice guidelines for memory integration across advanced process technologies and customer applications Memory Design Methodology & Problem Solving * Lead debugging and problem-solving activities in collaborative team environments * Provide technical expertise on memory compiler design, generation, and optimization * Support customers through complex memory design challenges and advanced integration requirements * Drive methodology improvements to enhance memory design productivity and reliability Customer Engagement & Technical Excellence * Deliver customer-facing technical support with focus on memory design and integration solutions * Ensure maximum customer satisfaction through expert guidance on memory IP implementation * Support aerospace, defense, and government customers with specialized memory requirements and security considerations Core Competencies * Self-driven and results-oriented with capability to effectively manage multiple complex tasks * Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications * US Citizenship required * Ability to obtain a US Government Security Clearance * Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study * 3+ years of experience with Memory design or Memory Compiler development and implementation Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study * Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles * Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification * Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST * Experience with IP development is a strong plus * Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus * Experience in ASIC or SoC development What We Offer * Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications * Direct customer engagement and technical leadership in advanced memory design * Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio * Competitive compensation * Professional development in memory design methodologies and foundry services * Direct impact on national security through advanced memory semiconductor solutions Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Job Details:Job Description: Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. Key Responsibilities Memory IP Technical Support & Integration Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance Technical Content Development & Training Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs Develop best practice guidelines for memory integration across advanced process technologies and customer applications Memory Design Methodology & Problem Solving Lead debugging and problem-solving activities in collaborative team environments Provide technical expertise on memory compiler design, generation, and optimization Support customers through complex memory design challenges and advanced integration requirements Drive methodology improvements to enhance memory design productivity and reliability Customer Engagement & Technical Excellence Deliver customer-facing technical support with focus on memory design and integration solutions Ensure maximum customer satisfaction through expert guidance on memory IP implementation Support aerospace, defense, and government customers with specialized memory requirements and security considerations Core Competencies Self-driven and results-oriented with capability to effectively manage multiple complex tasks Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications US Citizenship required Ability to obtain a US Government Security Clearance Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study 3+ years of experience with Memory design or Memory Compiler development and implementation Preferred Qualifications: Active US Government Security Clearance with a minimum of Secret level Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST Experience with IP development is a strong plus Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus Experience in ASIC or SoC development What We Offer Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications Direct customer engagement and technical leadership in advanced memory design Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio Competitive compensation Professional development in memory design methodologies and foundry services Direct impact on national security through advanced memory semiconductor solutions Job Type:Experienced HireShift:Shift 1 (United States of America) Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. Key Responsibilities Memory IP Technical Support & Integration * Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues * Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution * Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance Technical Content Development & Training * Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams * Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs * Develop best practice guidelines for memory integration across advanced process technologies and customer applications Memory Design Methodology & Problem Solving * Lead debugging and problem-solving activities in collaborative team environments * Provide technical expertise on memory compiler design, generation, and optimization * Support customers through complex memory design challenges and advanced integration requirements * Drive methodology improvements to enhance memory design productivity and reliability Customer Engagement & Technical Excellence * Deliver customer-facing technical support with focus on memory design and integration solutions * Ensure maximum customer satisfaction through expert guidance on memory IP implementation * Support aerospace, defense, and government customers with specialized memory requirements and security considerations Core Competencies * Self-driven and results-oriented with capability to effectively manage multiple complex tasks * Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications * US Citizenship required * Ability to obtain a US Government Security Clearance * Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study * 3+ years of experience with Memory design or Memory Compiler development and implementation Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study * Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles * Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification * Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST * Experience with IP development is a strong plus * Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus * Experience in ASIC or SoC development What We Offer * Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications * Direct customer engagement and technical leadership in advanced memory design * Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio * Competitive compensation * Professional development in memory design methodologies and foundry services * Direct impact on national security through advanced memory semiconductor solutions Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. **Key Responsibilities** **Memory IP Technical Support & Integration** + Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues + Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution + Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance **Technical Content Development & Training** + Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams + Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs + Develop best practice guidelines for memory integration across advanced process technologies and customer applications **Memory Design Methodology & Problem Solving** + Lead debugging and problem-solving activities in collaborative team environments + Provide technical expertise on memory compiler design, generation, and optimization + Support customers through complex memory design challenges and advanced integration requirements + Drive methodology improvements to enhance memory design productivity and reliability **Customer Engagement & Technical Excellence** + Deliver customer-facing technical support with focus on memory design and integration solutions + Ensure maximum customer satisfaction through expert guidance on memory IP implementation + Support aerospace, defense, and government customers with specialized memory requirements and security considerations **Core Competencies** + Self-driven and results-oriented with capability to effectively manage multiple complex tasks + Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates **Minimum Qualifications** + US Citizenship required + Ability to obtain a US Government Security Clearance + Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study + 3+ years of experience with Memory design or Memory Compiler development and implementation **Preferred Qualifications:** + Active US Government Security Clearance with a minimum of Secret level + Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study + Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles + Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification + Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST + Experience with IP development is a strong plus + Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus + Experience in ASIC or SoC development **What We Offer** + Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications + Direct customer engagement and technical leadership in advanced memory design + Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio + Competitive compensation + Professional development in memory design methodologies and foundry services + Direct impact on national security through advanced memory semiconductor solutions **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Arizona, Phoenix **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.