Research And Development Engineer jobs at Philips - 336 jobs

A leading technology company is seeking a GPU Physical Design Engineer to drive advanced clocking solutions. The role involves high-speed clock distribution and collaboration with cross-functional teams. Applicants should have a Bachelor's degree with significant industry experience, strong skills in circuit simulations, and experience in SOC Clock Implementation. This position offers competitive compensation and a hybrid work model allowing flexibility between on-site and off-site work. #J-18808-Ljbffr

# **Welcome!**## .GPU Physical Design Engineer page is loaded## GPU Physical Design Engineerlocations: US, California, Folsom: US, California, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR0279213# **Job Details:**## Job Description:Are you interested in working in a fast-paced, leading-edge environment with endless possibilities of innovating and learning, then our Graphics Hardware IP Team (GHI) team has an opportunity for you. In GHI we are passionate about delivering best-in-class visual experiences that enable users to immerse themselves in a new visual future. Within GHI you will be part of a Special Circuits Horizontal team that is responsible for local and global clocking of large designs like GFX Imaging processors, Peripheral subsystems like PCIe, Type-C, Display, Media and SOCs etc. We are looking for Graphics Hardware Clocking/Engineer to join the team.**The primary responsibilities for this role will include, but are not limited to:*** Ownership of complex highspeed global and local clock distribution network to meet the Power and Performance targets of these differentiating designs.* Work with Architects, PnP and Execution teams to identify right solutions in a timely manner.## **Qualifications:****A successful candidate will have proven experience demonstrating the following skills and behavioral traits:*** Team player with good problem-solving skills.* Strong written and verbal communication skills.**Minimum Qualifications**:Minimum qualifications are required to be initially considered for this position.* Bachelor's in Electrical/ Electronics/Computer Engineering, Computer Science or related field with at least 10 years of industry experience. Or a Master's degree in the same fields with at least 8 years of industry experience.* Advanced knowledge of Spice level circuit simulations.* Advanced experience in global and local clocking topologies.* 6+ years of hands on SOC Clock Implementation experience.* Basic understanding of RV and FEV flows.* Basic Scripting knowledge.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, California, Folsom## Additional Locations:US, California, Santa Clara## Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Benefits:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:Annual Salary Range for jobs which could be performed in the US: $161,230.00-227,620.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr

A leading technology company in California is seeking a Senior Mask Layout Design Engineer to perform physical layout for digital and mixed-signal functions. You'll collaborate with multi-disciplinary teams and have a significant role in mentoring junior mask designers. Ideal candidates should have a BS in Electrical Engineering and over 7 years of layout design experience with expertise in Cadence tools. This position offers a competitive salary and a hybrid work model. #J-18808-Ljbffr

A leading technology firm is seeking an IP Logic Design Engineer to design and integrate IP for custom silicon solutions. The role requires a Bachelor's degree in a relevant field with 3+ years of experience or a Master's with 2+ years. Key responsibilities include architecture and design implementation, working with cross-functional teams, and vendor collaboration. Competitive compensation, with an annual salary range of $164,470-232,190, is offered along with a strong benefits package. #J-18808-Ljbffr

# **Welcome!**## .# **Job Details:**## :Job Description**Do Something Wonderful!**Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.or the links below!**WHO WE ARE:**We are a Custom IP and Silicon engineering team part of Intel's Silicon Engineering Group. The team works on design and verification of cutting edge IP and SoCs geared towards Intel's advanced Data center and AI SoCs. We look to drive major technological and methodological advancements across multiple areas of IP and SoC Design and Verification, looking to set a high bar across the organization and ensure that Intel has a competitive product in the market.**WHO YOU ARE:**As an IP Logic Design Engineer your responsibilities will include but are not limited to:* Designing and/or integrating IP for Intel's Custom Silicon solutions.* You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation.* Creating a design to produce key assets that help improve product KPIs for discrete graphics products.* Working with SoC Architecture and platform architecture teams to establish silicon requirements.* Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.* Creating micro architectural specification document for the design.* Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.* Driving vendor's methodology to meet world class silicon design standards.* Architecting area and power efficient low latency designs with scalabilities and flexibilities.* Power and Area efficient RTL logic design and DV support.* Running tools to ensure lint-free and CDC/RDC clean design, VCLP.* Synthesis and timing constraints.* Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.## **Qualifications:****Minimum Qualifications:**Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 3+ years of relevant experience- or -Master's degree in the same fields with 2+ years of relevant experience- or -PhD in the same fields.Relevant work experience should be of the following:* Experience with complex IP/ASIC/SOC Design Implementation.* Experience in system and processor architecture.* Experience with System Verilog/SOC development environment.Preferred Qualifications:* Experience in scripting languages (i.e. PERL, TCL, or Python).* Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification).* Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller.* Experience in leading small team of engineers.* Experience with Industry standard protocols (i.e. PCIE, USB, DDR, etc).* Experience with interaction of computer hardware with software.* Experience with Low power/UPF implementation/verification techniques.* Experience with Formal verification techniques.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:Virtual US## Additional Locations:## Business group:At the Data Center Group (DCG), we're committed to delivering exceptional products and delighting our customers. We offer both broad-market Xeon-based solutions and custom x86-based products, ensuring tailored innovation for diverse needs across general-purpose compute, web services, HPC, and AI-accelerated systems. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership. Join us as we transform the data center segment through workload driven leadership products and close collaboration with our partners.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the .Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. \* Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 12/31/2027\*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr

NVIDIA continues to reinvent itself. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. Are you passionate about working at the groundbreaking of technology? Make the choice to join us today. Our System Level Product Engineering team works on groundbreaking innovations involving crafting creative solutions for system level diag, verification and post-silicon validation of some of the industry's most complex semiconductor chips. What you'll be doing: Solve complex testing challenges and develop new methodologies for reliable testing of chips at SLT Key responsibilities include characterization, yield enhancement and spec validation. Partner with other engineering groups including ASIC, DFT, ATE, silicon validation, fab process, software and quality teams to coordinate efforts and resolve silicon issues. Initiate and drive process improvements/preventative actions through root cause analysis. The ideal candidate will always look to improve workflows, products, functions and methodologies while working multi-functionally to achieve the company goals. What we need to see: BSEE or MSEE degree (or equivalent experience). 8+ years of relevant product engineering work experience or similar hardware systems background. Self-motivated with strong technical, interpersonal, written/oral communication skills Problem solving experience/ability. Be able to quickly become a strong contributor both as an individual and as a member of highly productive team. Software skills needed for large scale data analysis such as Python. Experience with HBM/GDDR memory, Power/Speed/Noise/Thermal characterization is a plus. NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most talented people in the world working for us. If you're creative and autonomous, we want to hear from you. You can do your life's work here! Join us! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 258,750 USD for Level 4, and 200,000 USD - 322,000 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 13, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA's NPI Operations Team is looking for a highly motivated System Product Development Engineer to lead the development and productization of DGX products through mass production ramp. This role focuses on DGX systems and L11 rack-scale AI supercomputer reference platforms-some of the most advanced computing systems in the world for Artificial Intelligence. These products form the foundation for training and deploying industry-leading LLMs and represent NVIDIA's fastest-growing business segment and largest market opportunity. What you'll be doing: Drive development and productization of NVIDIA's DGX datacenter products and L11 systems. Lead debug efforts for L11 rack-level integration, creating and applying tools/scripts for failure identification and root cause analysis. Provide clear, actionable guidance to factories to resolve issues quickly and implement corrective actions that improve manufacturing quality and efficiency. Develop and document robust, stable recipes-including diagnostics, firmware, and software-for mass production ramp. Review and provide feedback on test plans and factory acceptance criteria, focusing on yield, quality, and efficiency. Collaborate with development, validation, and manufacturing test engineering teams to understand diagnostic and firmware release plans and their impact on system stability and quality. Influence test engineering and diagnostic teams to enhance test methodology, telemetry, and debug capabilities for precise FRU identification and isolation of firmware/test issues and to improve test coverage with the goal of preventing downstream escapes. Partner with product development teams to ensure designs are optimized for manufacturing. Present NPI status updates and critical issues to executive management. What we need to see: Expertise in server platform architecture, CPU/GPU baseboards, and high-speed interfaces with proven system-level debug skills and exceptional diagnostic instincts. Strong knowledge of BMC, firmware architecture, and manufacturing diagnostics. Familiarity with L11 integration processes. Excellent communication skills to articulate problems and deliver clear recommendations. Strong analytical skills to synthesize complex information and provide actionable guidance. Leadership skills to manage factory operations and drive issue resolution. Collaborative mindset to work seamlessly with cross-functional teams and external partners. Results-driven approach to achieving optimal outcomes across all aspects of NPI operations. 12+ years in system engineering, debug, or equivalent relevant experience BS or higher in Electrical Engineering, Computer Engineering or equivalent experience With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world's most desirable employers; we have some of the most forward-thinking and hardworking people in the world working for us and, due to unparalleled growth, best-in-class teams are rapidly growing. If you're creative and autonomous with a real passion for your work, we want to hear from you! Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 200,000 USD - 322,000 USD. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until January 13, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Change the world. Love your job. In your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI, and set you up for long-term career success. Within this program, we also offer function-specific technical training and on-the-job learning opportunities that will encourage you to solve problems through a variety of hands-on, meaningful experiences from your very first day on the job. The TMG Development program is a 12-month program for new college graduates in the TMG organization. Are you looking to grow your career in manufacturing product introduction and production at one of the leading semiconductor companies in the world? TI's Manufacturing Engineers are technical leaders who get to work in the world's most advanced manufacturing facilities. We bring the company's breakthrough innovations to life by manufacturing technologies that are literally changing the world. At Texas Instruments (TI), as a Manufacturing Product Engineer, you will interface with design, process, test, reliability and manufacturing engineering to solve product issues and production problems, as well as developing process improvements to reduce production costs and increase yields. Manufacturing Product Engineers also manage new product introduction and production support engineering for a specific product or group of products after they have been transferred from design to in-house or outsourced production. Responsibilities include: * Support daily production issues at test floor and wafer probe. This includes low yield analysis and disposition, and setup failure debug/analysis and resolution (both hardware and software) * Provide detailed analytical study on above issues, and liaise with business units; product engineering team for improvement (test program, hardware, setup, etc.) * Engage in productivity improvement projects, including yield improvement, test time reduction, test insertion removal, legacy tester conversion, etc * Support new product release from development site. Perform vigorous buyoff for new test systems (program/hardware) per manufacturing requirements * Lead and support introduction of new tool/equipment/test processes to manufacturing from new product releases, leading the entire qualification and change management approval within TI Electronic Marketing (TIEM) * Interface with various modules, in addition to yield, product and integration teams, to resolve issues that limit yield performance. Minimum Requirements: * Masters degree in Computer Engineering, Electrical & Computer Engineer, Electrical Engineering, Engineering Physics, Physics or related * Cumulative 3.0/4.0 GPA or higher * Experience with VLSI design and development technologies Preferred Qualifications: * Knowledge of Wafer fabrication, Device Physics, Circuit Analysis and Data Analysis * Strong verbal and written communication skills * Demonstrated strong analytical, critical thinking, and problem solving skills * Ability to work in teams and collaborate effectively with people in different functions * Ability to take the initiative and drive for results * Strong time management skills that enable on-time project delivery * Ability to work effectively in an interrupt-driven, fast-paced and rapidly changing environment * Demonstrated ability to build strong, influential relationships * Problem solving skills, including meticulous attention to details * Ability to communicate effectively across functional boundaries and with upper management * Ability to work in stressful situations and arrive at creative and effective solutions * Ability to think strategically Minimum Requirements: * Masters degree in Computer Engineering, Electrical & Computer Engineer, Electrical Engineering, Engineering Physics, Physics or related * Cumulative 3.0/4.0 GPA or higher * Experience with VLSI design and development technologies Preferred Qualifications: * Knowledge of Wafer fabrication, Device Physics, Circuit Analysis and Data Analysis * Strong verbal and written communication skills * Demonstrated strong analytical, critical thinking, and problem solving skills * Ability to work in teams and collaborate effectively with people in different functions * Ability to take the initiative and drive for results * Strong time management skills that enable on-time project delivery * Ability to work effectively in an interrupt-driven, fast-paced and rapidly changing environment * Demonstrated ability to build strong, influential relationships * Problem solving skills, including meticulous attention to details * Ability to communicate effectively across functional boundaries and with upper management * Ability to work in stressful situations and arrive at creative and effective solutions * Ability to think strategically

Change the world. Love your job. In your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI, and set you up for long-term career success. Within this program, we also offer function-specific technical training and on-the-job learning opportunities that will encourage you to solve problems through a variety of hands-on, meaningful experiences from your very first day on the job. The TMG Development program is a 12-month program for new college graduates in the TMG organization. Are you looking to grow your career in manufacturing product introduction and production at one of the leading semiconductor companies in the world? TI's Manufacturing Engineers are technical leaders who get to work in the world's most advanced manufacturing facilities. We bring the company's breakthrough innovations to life by manufacturing technologies that are literally changing the world. At Texas Instruments (TI), as a Manufacturing Product Engineer, you will interface with design, process, test, reliability and manufacturing engineering to solve product issues and production problems, as well as developing process improvements to reduce production costs and increase yields. Manufacturing Product Engineers also manage new product introduction and production support engineering for a specific product or group of products after they have been transferred from design to in-house or outsourced production. Responsibilities include: Support daily production issues at test floor and wafer probe. This includes low yield analysis and disposition, and setup failure debug/analysis and resolution (both hardware and software) Provide detailed analytical study on above issues, and liaise with business units; product engineering team for improvement (test program, hardware, setup, etc.) Engage in productivity improvement projects, including yield improvement, test time reduction, test insertion removal, legacy tester conversion, etc Support new product release from development site. Perform vigorous buyoff for new test systems (program/hardware) per manufacturing requirements Lead and support introduction of new tool/equipment/test processes to manufacturing from new product releases, leading the entire qualification and change management approval within TI Electronic Marketing (TIEM) Interface with various modules, in addition to yield, product and integration teams, to resolve issues that limit yield performance. Minimum Requirements: Masters degree in Computer Engineering, Electrical & Computer Engineer, Electrical Engineering, Engineering Physics, Physics or related Cumulative 3.0/4.0 GPA or higher Experience with VLSI design and development technologies Preferred Qualifications: Knowledge of Wafer fabrication, Device Physics, Circuit Analysis and Data Analysis Strong verbal and written communication skills Demonstrated strong analytical, critical thinking, and problem solving skills Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery Ability to work effectively in an interrupt-driven, fast-paced and rapidly changing environment Demonstrated ability to build strong, influential relationships Problem solving skills, including meticulous attention to details Ability to communicate effectively across functional boundaries and with upper management Ability to work in stressful situations and arrive at creative and effective solutions Ability to think strategically

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel About the team and organization: Compact Device Modeling Group (CDMG) is part of Intel's Design Technology Platform (DTP) organization. DTP is a key pillar in enabling Intel to deliver design, development and manufacturing services that allow Intel Foundry customers to deliver winning products to the marketplace. Your work will directly enable design teams to get to the market faster with leadership products based on innovative technologies. As a member of CDMG you will be at the forefront of co-optimizing Intel's state-of-the-art process technology which allows customers with diverse design needs to enable best-in-class products for data-centric applications. As a semiconductor device modeling engineer, you will be playing a key role to support compact modeling activities for Intel's new technologies. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications * Bachelor's degree in Electrical Engineering or a related discipline and 5+ or Master's degree in Electrical Engineering or a related discipline and at least 3 years of industry experience in the semiconductor field; or Ph.D. in Electrical Engineering or a related discipline. * Graduate coursework or research experience in semiconductor device physics or 5+ years of work experience in Semiconductor device physics. * 1+ years' experience Python scripting for data analysis, automation and documentation. Preferred Qualifications * Ph.D. in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field. * Proficiency with extraction tools (e.g., ICCAP, MBP) and commercial simulators such as HSPICE, Spectre, etc. * Hands-on experience with BSIM-CMG and other compact models for transistor modeling at advanced nodes (e.g., FinFET, GAA) including experience in one or more of the following areas: * Experience developing Layout-dependent effects (LDE) for FinFET or GAAFET technologies and their impact on circuit performance. * Development of methodologies for device targeting (e.g., transistors) and benchmarking circuits (e.g., ring oscillators), including corners and statistical variation models. * Modeling using Open Model Interface (OMI). * Strong understanding of process flow, layout, and basic circuit design/simulation. * Modeling self-heating effects and their influence on device and circuit performance. * Proven capability to collaborate across multiple teams and geographies. * Experience with machine learning algorithms and their application is data analysis and compact model development. Benefits at Intel Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, California, Santa Clara Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Job Details:Job Description: About MDCE Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development. Position Overview As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications. Key Responsibilities • Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring • Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements • Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications • Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing • Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities • Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms • Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability • Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers • Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies. Ideal candidate must demonstrate: • Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs • Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions • Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment • Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization Qualifications: Minimum Qualifications • Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development. The years of experience must include: • Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. • Experience in scribe line layout design and process monitoring structure development. • Proficiency in design rule development, validation, and waiver management processes. • Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design. Preferred Qualifications • Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development • Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization • Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation. • Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs • Experience with design rule checker (DRC) development and physical verification flows • Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures • Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization • Knowledge of mask generation including Boolean/OPC Job Type:Experienced HireShift:Shift 1 (United States of America) Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Job Details:Job Description: Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. Key Responsibilities Memory IP Technical Support & Integration Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance Technical Content Development & Training Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs Develop best practice guidelines for memory integration across advanced process technologies and customer applications Memory Design Methodology & Problem Solving Lead debugging and problem-solving activities in collaborative team environments Provide technical expertise on memory compiler design, generation, and optimization Support customers through complex memory design challenges and advanced integration requirements Drive methodology improvements to enhance memory design productivity and reliability Customer Engagement & Technical Excellence Deliver customer-facing technical support with focus on memory design and integration solutions Ensure maximum customer satisfaction through expert guidance on memory IP implementation Support aerospace, defense, and government customers with specialized memory requirements and security considerations Core Competencies Self-driven and results-oriented with capability to effectively manage multiple complex tasks Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications US Citizenship required Ability to obtain a US Government Security Clearance Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study 3+ years of experience with Memory design or Memory Compiler development and implementation Preferred Qualifications: Active US Government Security Clearance with a minimum of Secret level Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST Experience with IP development is a strong plus Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus Experience in ASIC or SoC development What We Offer Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications Direct customer engagement and technical leadership in advanced memory design Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio Competitive compensation Professional development in memory design methodologies and foundry services Direct impact on national security through advanced memory semiconductor solutions Job Type:Experienced HireShift:Shift 1 (United States of America) Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About MDCE Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development. Position Overview As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications. Key Responsibilities * Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring * Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements * Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications * Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing * Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities * Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms * Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability * Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers * Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies. Ideal candidate must demonstrate: * Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs * Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions * Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment * Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization Qualifications: Minimum Qualifications * Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development. The years of experience must include: * Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. * Experience in scribe line layout design and process monitoring structure development. * Proficiency in design rule development, validation, and waiver management processes. * Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design. Preferred Qualifications * Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development * Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization * Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation. * Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs * Experience with design rule checker (DRC) development and physical verification flows * Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures * Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization * Knowledge of mask generation including Boolean/OPC Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, Oregon, Hillsboro Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Job Details:Job Description: About MDCE Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development. Position Overview As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications. Key Responsibilities • Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring • Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements • Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications • Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing • Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities • Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms • Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability • Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers • Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies. Ideal candidate must demonstrate: • Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs • Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions • Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment • Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization Qualifications: Minimum Qualifications • Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development. The years of experience must include: • Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. • Experience in scribe line layout design and process monitoring structure development. • Proficiency in design rule development, validation, and waiver management processes. • Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design. Preferred Qualifications • Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development • Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization • Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation. • Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs • Experience with design rule checker (DRC) development and physical verification flows • Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures • Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization • Knowledge of mask generation including Boolean/OPC Job Type:Experienced HireShift:Shift 1 (United States of America) Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**About MDCE** Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development. **Position Overview** As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications. **Key Responsibilities** - Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring - Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements - Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications - Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing - Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities - Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms - Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability - Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers - Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies. **Ideal candidate must demonstrate:** - Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs - Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions - Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment - Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization **Qualifications:** **Minimum Qualifications** - Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development. The years of experience must include: - Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. - Experience in scribe line layout design and process monitoring structure development. - Proficiency in design rule development, validation, and waiver management processes. - Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design. **Preferred Qualifications** - Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development - Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization - Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation. - Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs - Experience with design rule checker (DRC) development and physical verification flows - Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures - Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization - Knowledge of mask generation including Boolean/OPC **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Santa Clara **Additional Locations:** US, Arizona, Phoenix, US, Oregon, Hillsboro **Business group:** Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About Intel Foundry Services Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. Position Overview The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. Key Responsibilities Memory IP Technical Support & Integration * Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues * Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution * Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance Technical Content Development & Training * Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams * Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs * Develop best practice guidelines for memory integration across advanced process technologies and customer applications Memory Design Methodology & Problem Solving * Lead debugging and problem-solving activities in collaborative team environments * Provide technical expertise on memory compiler design, generation, and optimization * Support customers through complex memory design challenges and advanced integration requirements * Drive methodology improvements to enhance memory design productivity and reliability Customer Engagement & Technical Excellence * Deliver customer-facing technical support with focus on memory design and integration solutions * Ensure maximum customer satisfaction through expert guidance on memory IP implementation * Support aerospace, defense, and government customers with specialized memory requirements and security considerations Core Competencies * Self-driven and results-oriented with capability to effectively manage multiple complex tasks * Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates Minimum Qualifications * US Citizenship required * Ability to obtain a US Government Security Clearance * Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study * 3+ years of experience with Memory design or Memory Compiler development and implementation Preferred Qualifications: * Active US Government Security Clearance with a minimum of Secret level * Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study * Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles * Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification * Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST * Experience with IP development is a strong plus * Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus * Experience in ASIC or SoC development What We Offer * Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications * Direct customer engagement and technical leadership in advanced memory design * Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio * Competitive compensation * Professional development in memory design methodologies and foundry services * Direct impact on national security through advanced memory semiconductor solutions Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Foundry Services** Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain. **Position Overview** The Aerospace, Defense & Government (ADG) Memory Design Application Engineer provides specialized technical support to Intel Foundry Services customers on memory compiler generation and integration challenges. This critical role ensures successful customer tape-outs by resolving complex memory IP integration issues, driving quality improvements in memory collaterals, and delivering comprehensive technical guidance on memory design methodologies for advanced semiconductor applications. **Key Responsibilities** **Memory IP Technical Support & Integration** + Provide comprehensive technical support to Intel Foundry Services customers on memory compiler generation and integration issues + Collaborate with internal Intel teams and external stakeholders including foundry customers' design teams, Memory IP providers, and EDA vendors on foundational IP integration issue resolution + Drive resolution of customer issues related to memory IP collaterals, ensuring seamless integration and optimal performance **Technical Content Development & Training** + Create application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams + Drive quality improvements in design kits, Memory IP collaterals, and documentation to remove barriers to successful customer design tape-outs + Develop best practice guidelines for memory integration across advanced process technologies and customer applications **Memory Design Methodology & Problem Solving** + Lead debugging and problem-solving activities in collaborative team environments + Provide technical expertise on memory compiler design, generation, and optimization + Support customers through complex memory design challenges and advanced integration requirements + Drive methodology improvements to enhance memory design productivity and reliability **Customer Engagement & Technical Excellence** + Deliver customer-facing technical support with focus on memory design and integration solutions + Ensure maximum customer satisfaction through expert guidance on memory IP implementation + Support aerospace, defense, and government customers with specialized memory requirements and security considerations **Core Competencies** + Self-driven and results-oriented with capability to effectively manage multiple complex tasks + Effective communicator with strong interpersonal and leadership capabilities, fostering collaboration across cross-functional teams and providing constructive feedback **Qualifications:** The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates **Minimum Qualifications** + US Citizenship required + Ability to obtain a US Government Security Clearance + Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study + 3+ years of experience with Memory design or Memory Compiler development and implementation **Preferred Qualifications:** + Active US Government Security Clearance with a minimum of Secret level + Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study + Proficient in common memory types, including SRAM, Register Files (RF), and ROM, with a solid understanding of CMOS digital circuit design principles + Knowledgeable in both behavioral and physical modeling of memory architectures, supporting accurate simulation and verification + Hands-on experience with customer support in at least one of the following domains: Memory Design, Memory Compiler Design, eFUSE and anti FUSE and MBIST + Experience with IP development is a strong plus + Proficient in scripting languages like Perl/Tcl/Python, and power-aware RTL and UPF flow is a plus + Experience in ASIC or SoC development **What We Offer** + Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications + Direct customer engagement and technical leadership in advanced memory design + Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio + Competitive compensation + Professional development in memory design methodologies and foundry services + Direct impact on national security through advanced memory semiconductor solutions **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, Arizona, Phoenix **Additional Locations:** US, California, Santa Clara, US, Oregon, Hillsboro **Business group:** The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

About MDCE Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development. Position Overview As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications. Key Responsibilities * Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring * Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements * Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications * Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing * Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities * Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms * Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability * Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers * Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies. Ideal candidate must demonstrate: * Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs * Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions * Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment * Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization Qualifications: Minimum Qualifications * Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development. The years of experience must include: * Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. * Experience in scribe line layout design and process monitoring structure development. * Proficiency in design rule development, validation, and waiver management processes. * Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design. Preferred Qualifications * Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development * Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization * Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation. * Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs * Experience with design rule checker (DRC) development and physical verification flows * Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures * Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization * Knowledge of mask generation including Boolean/OPC Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, California, Santa Clara Additional Locations: US, Arizona, Phoenix, US, Oregon, Hillsboro Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

**About MDCE** Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. MDCE Device org is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development. **Position Overview** As a device technologist, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, manage OPC/Mask requests and managing design rules and waivers for technologies currently in large volume manufacturing. The role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets including high performance compute, mobile, mixed signal, memory controllers, and other diverse applications. **Key Responsibilities** - Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoring - Collaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirements - Develop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applications - Create and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturing - Work with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilities - Drive the development of standardized test chip methodologies and scribe line layouts that are compatible with Intel's existing manufacturing processes and platforms - Analyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturability - Provide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customers - Stay updated with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategies. **Ideal candidate must demonstrate:** - Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs - Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions - Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment - Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization **Qualifications:** **Minimum Qualifications** - Master's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with focus on test chip design and device collateral development. The years of experience must include: - Demonstrated expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture. - Experience in scribe line layout design and process monitoring structure development. - Proficiency in design rule development, validation, and waiver management processes. - Strong understanding of DTCO skills including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration, Yield, Device and Design. **Preferred Qualifications** - Ph.D. degree in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral development - Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization - Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation. - Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs - Experience with design rule checker (DRC) development and physical verification flows - Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures - Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization - Knowledge of mask generation including Boolean/OPC **Job Type:** Experienced Hire **Shift:** Shift 1 (United States of America) **Primary Location:** US, California, Santa Clara **Additional Locations:** US, Arizona, Phoenix, US, Oregon, Hillsboro **Business group:** Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth. **Posting Statement:** All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. **Position of Trust** N/A **Benefits** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (*********************************************************************************** . Annual Salary Range for jobs which could be performed in the US: $190,650.00-269,150.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. **Work Model for this Role** This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.