Design/Applications Engineer jobs at Synopsys - 220 jobs

A leading technology company is seeking a GPU Physical Design Engineer to drive advanced clocking solutions. The role involves high-speed clock distribution and collaboration with cross-functional teams. Applicants should have a Bachelor's degree with significant industry experience, strong skills in circuit simulations, and experience in SOC Clock Implementation. This position offers competitive compensation and a hybrid work model allowing flexibility between on-site and off-site work. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Staff Power Module Design Engineer. You'll develop innovative power module products and collaborate with industry experts. The role requires a strong educational background in Power Electronics and significant experience in switching power converter design. This position offers competitive pay within a vibrant engineering team, fostering professional growth and mentorship opportunities. #J-18808-Ljbffr

# **Welcome!**## .GPU Physical Design Engineer page is loaded## GPU Physical Design Engineerlocations: US, California, Folsom: US, California, Santa Claratime type: Full timeposted on: Posted Todayjob requisition id: JR0279213# **Job Details:**## Job Description:Are you interested in working in a fast-paced, leading-edge environment with endless possibilities of innovating and learning, then our Graphics Hardware IP Team (GHI) team has an opportunity for you. In GHI we are passionate about delivering best-in-class visual experiences that enable users to immerse themselves in a new visual future. Within GHI you will be part of a Special Circuits Horizontal team that is responsible for local and global clocking of large designs like GFX Imaging processors, Peripheral subsystems like PCIe, Type-C, Display, Media and SOCs etc. We are looking for Graphics Hardware Clocking/Engineer to join the team.**The primary responsibilities for this role will include, but are not limited to:*** Ownership of complex highspeed global and local clock distribution network to meet the Power and Performance targets of these differentiating designs.* Work with Architects, PnP and Execution teams to identify right solutions in a timely manner.## **Qualifications:****A successful candidate will have proven experience demonstrating the following skills and behavioral traits:*** Team player with good problem-solving skills.* Strong written and verbal communication skills.**Minimum Qualifications**:Minimum qualifications are required to be initially considered for this position.* Bachelor's in Electrical/ Electronics/Computer Engineering, Computer Science or related field with at least 10 years of industry experience. Or a Master's degree in the same fields with at least 8 years of industry experience.* Advanced knowledge of Spice level circuit simulations.* Advanced experience in global and local clocking topologies.* 6+ years of hands on SOC Clock Implementation experience.* Basic understanding of RV and FEV flows.* Basic Scripting knowledge.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, California, Folsom## Additional Locations:US, California, Santa Clara## Business group:Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society.## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustN/A**Benefits:**We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:Annual Salary Range for jobs which could be performed in the US: $161,230.00-227,620.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. \* Job posting details (such as work model, location or time type) are subject to change. #J-18808-Ljbffr

A leading technology company is seeking a Physical IC Design Engineer in San Jose, California. The role involves executing various physical design tasks and requires a bachelor's degree in Electrical or Electronics Engineering with over 12 years of relevant experience. Strong scripting skills and expertise in EDA tools are essential. The position offers a competitive salary range of $141,300 - $226,000 along with comprehensive benefits including health insurance, 401(K) matching and more. #J-18808-Ljbffr

A leading technology company in San Jose is looking for a Physical IC Design Engineer to drive next-gen AI and ML ecosystems. The role requires 8+ years of experience and a Bachelor's degree in Electrical or Electronics Engineering. Responsibilities include execution of Physical Design, Synthesis, and collaborating with IC Design engineers. This position has a salary range of $120,000 - $192,000 and offers a comprehensive benefits package including health plans, 401(K) matching, and paid leave. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking a Physical IC Design Engineer to drive next-generation AI and ML ecosystems through PCIe Switch Products. This role requires a strong background in Physical Design, including execution of design, verification, and timing closure. The ideal candidate must have a Bachelor's degree in Electrical or Electronics Engineering and at least 8 years of experience. The position offers a competitive salary range of $120,000 to $192,000, along with comprehensive benefits. #J-18808-Ljbffr

A leading technology firm located in San Jose is seeking a Physical IC Design Engineer to drive innovation in Artificial Intelligence and Machine Learning through their products. This position focuses on executing the physical design and verification of chip architectures. Candidates should possess a Bachelor's degree in Electrical Engineering or Electronics Engineering and have over 8 years of relevant experience. The role offers a competitive salary ranging from $120,000 to $192,000, plus various benefits including medical and retirement plans. #J-18808-Ljbffr

A global semiconductor company in San Jose is seeking a Principal Power Module Design Engineer. This role involves new product development in power electronics, requiring at least a master's or Ph.D. in Power Electronics and 5+ years of experience in related design. Applicants should possess strong skills in switching power converter design and analog circuit design. The position offers competitive compensation, a collaborative environment, and opportunities for professional growth. #J-18808-Ljbffr

A leading semiconductor company in San Jose is seeking an experienced Physical IC Design Engineer to join their Data Center Solutions Group. You will drive advancements in AI/ML ecosystems and manage data centers. The ideal candidate will have over 12 years of experience in physical design and proficiency in TCL/PERL scripting. A Bachelor's degree in Electrical or Electronics Engineering is required. This position offers a competitive salary and comprehensive benefits package, including health insurance and 401(k) matching. #J-18808-Ljbffr

A leading technology firm in San Jose is seeking a Physical Design Engineer to focus on the implementation and optimization of IC layouts for advanced technologies. The ideal candidate has extensive experience in physical layout, strong scripting skills in TCL and Python, and a solid background in electrical engineering. This role offers a competitive salary, bonus potential, and comprehensive benefits. #J-18808-Ljbffr

A leading technology company in San Jose is seeking an experienced engineer to join their analog/mixed signal IP design team. This role involves designing next generation I/O interfaces, with a strong emphasis on mixed signal design and leading technical projects. The ideal candidate will possess a degree in Electrical Engineering and have hands-on experience with high speed designs and communication tools. This position offers competitive benefits and is not eligible for visa sponsorship. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next‑generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. The Role This role is an exciting opportunity in SBIO team to create FPGA hardware validation platforms and debugging complex issues involving both hardware and software. Collaborate with design and firmware teams to define validation plans and execute on FPGA prototyping platforms. This role requires a proven track record of successfully bringing complex FPGA designs from concept through production quality, with strong debugging and problem-solving capabilities. The Person Strong analytical and problem solving skills with a pronounced attention to detail Strong communication, mentoring and leadership skills Self-driven, Methodical and attention to detail in troubleshooting and problem-solving Can work well with cross functional teams Excellent verbal and written communication skills Responsibility Design, develop, and implement complex FPGA architectures using Xilinx devices (UltraScale, UltraScale+, Versal, etc.) Create RTL designs using Verilog/SystemVerilog for high-performance applications Perform FPGA prototype design, implementation, and bring‑up activities Create comprehensive design documentation, specifications, and technical reports Perform timing analysis, closure, and optimization using Vivado tools Conduct board-level bring‑up and system integration testing Debug complex hardware/firmware issues using logic analyzers, oscilloscopes, and other test equipment Validate FPGA designs against specifications and performance requirements Independently troubleshoot and resolve challenging technical issues Work closely with hardware, software, and systems engineering teams Participate in design reviews and technical discussions Communicate project status, risks, and technical challenges to stakeholders Preferred Skill Set & Experience Extensive experience in field of FPGA hardware prototyping Have worked with prototyping platforms such as Xilinx reference boards, Synopsys HAPS platforms etc Experience with Xilinx Versal ACAP or UltraScale+ devices Knowledge of FPGA synthesis tools and methodologies Familiarity with Python/TCL scripting for design automation Knowledge of FPGA-based system architecture and hardware/software co‑design Familiarity with board design and hardware debugging tools (logic analyzers, oscilloscopes, protocol analyzers) Fluent in System Verilog and a familiarity with simulation and debug Familiarity with industry standard high-speed protocols such as USB and PCIE is a plus EDUCATION BS (or higher) degree in Electrical or Computer Engineering desired LOCATION Santa Clara, CA This role is not eligible for visa sponsorship. #LI‑SC3 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading semiconductor company in Santa Clara is looking for an FPGA Hardware Validation Engineer to create and implement validation platforms while collaborating with design and firmware teams. Candidates should have extensive experience in FPGA prototyping and strong problem-solving skills, along with a BS in Electrical or Computer Engineering. The role involves complex architecture designs and debugging hardware/firmware issues. Join a culture of innovation driven by collaboration and inclusivity. #J-18808-Ljbffr

A leading electronic design automation company in California seeks an experienced SoC/ASIC Digital Design Engineer with a strong focus on Design for Test (DFT) methodologies. The ideal candidate will have substantial expertise in scan chain insertion, compression scan technologies, and automatic test pattern generation (ATPG), along with strong problem-solving skills and the ability to work collaboratively in a cross-functional team environment. This is a fantastic opportunity to contribute to essential technology projects. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. Drive PPA optimization and ensure scalability across roadmap and custom devices. Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. Analyze trade-offs for performance, power, reliability, and manufacturability. Influence strategies for security, safety, and reliability across CPF domains. Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. Experience with low-power design techniques, boot/reset flows, and power management. Knowledge of design methodologies, advanced process technologies, and associated challenges. Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS BS or MS or PhD in Electrical/Computer Engineering or related field. Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr

A leading semiconductor company in San Jose seeks a Senior Engineer in Product Engineering to manage new product introductions and production support. Candidates should have a Master's degree in Electrical Engineering and two years of relevant experience. Responsibilities include interfacing with manufacturing, conducting failure analyses, and implementing process improvements. This role offers competitive pay and benefits, including healthcare coverage and a performance-based bonus. #J-18808-Ljbffr

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The candidate will join a highly visible team of physical interface experts concentrated on SERDES interfaces across AMD products. The team works across a large swath of AMD teams and is instrumental in the delivery of leading-edge, high-speed interface capabilities. THE PERSON: The ideal candidate is self-motivated to work independently as well as collaboratively with engineers across a variety of AMD design, verification, and validation teams. KEY RESPONSIBILITIES: * Excellent working knowledge of RTL-based design flows * Strong knowledge of firmware and hardware interaction * FPGA design and prototyping for various MAC or PCS functionalities * Working knowledge of the entire FPGA or ASIC design process and tool flow * Work with internal and external teams to develop transceivers solutions for various applications * Hands-on experience with various lab equipment for silicon bring-up and validation PREFERRED EXPERIENCE: * Familiar with industry standards such as Ethernet and PCIe is a plus * Strong analytical and problem-solving skills with pronounced attention to details ACADEMIC CREDENTIALS: * BS or MS in Electrical or Computer Engineering preferred LOCATION: San Jose, CA #LI-DP1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here. This posting is for an existing vacancy.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is eligible to apply: Please ONLY consider applying if you are a Physical Designer and (IMPORTANT) who has been out of the workforce for caregiving for a period of at least two years and have a minimum of three years of Physical Design work experience. This role is not open to new college grads or interns. Please check our career site for those roles. Cadence is offering an opportunity to qualified candidates who meet our eligibility criteria to participate in a 16-week paid returnship program. You will be entered in a tailored program designed to jump start your skills through training, hands on projects and customer interaction. You will have an opportunity to update your resume, build connections and participate in fun events as you re-enter the workforce. In this program, you will work with best in class EDA tools, collaborate with R&D and the Sales team in a dynamic, innovative environment. Learn processes that are in the forefront of technology, how a company like Cadence works as well as experience how teams solve problems. We are seeking individuals with experience in Digital Synthesis, Place and Route and Signoff Analysis. Where is this returnship located: San Jose, CA What opportunity is offered: Candidates will find opportunities to be in the Application Engineering field spanning across Digital Synthesis, Place and Route and Signoff Analysis. How long is this returnship: 16 weeks Company Description: At Cadence, our core values are more than just words, they are the way we work, laugh, debate, care, question, and innovate together. We are One Cadence-One Team. Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation (EDA) company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Our team's shared passion for solving the world's toughest technical challenges and drive to do meaningful work makes us proud to be part of Cadence. Our unique culture has been recognized on FORTUNE Magazine's 100 Best Companies to Work For list and garnered accolades from the Great Place To Work Institute around the globe. #LI-MA1 The annual salary range for California is $59,500 to $110,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We're doing work that matters. Help us solve what others can't.

Category Engineering Hire Type Employee Job ID 13730 Base Salary Range $112000-$168000 Remote Eligible No Date Posted 14.12.2025 We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.You Are: You are an enthusiastic engineering professional who thrives on solving complex technical challenges and enjoys working directly with customers to make a tangible impact. You bring a deep understanding of fluid mechanics, computational fluid dynamics, and thermodynamics, paired with hands-on experience in deploying simulation software for real-world engineering problems. Your background in the Electronics Industry segment allows you to quickly identify and address customer requirements, seamlessly integrating Ansys solutions into their workflows. As a strong communicator, you are comfortable presenting technical concepts to diverse audiences, including senior business managers and C-level executives. Your curiosity drives you to stay ahead of industry trends, and your collaborative nature means you work effectively within multidisciplinary teams. You have a passion for knowledge sharing, whether that's through authoring conference presentations, leading training sessions, or supporting field and digital marketing initiatives. Your organizational skills and sense of urgency ensure projects are delivered on time and to a high standard. You are proactive, adaptable, and committed to continuous learning, ready to travel up to 25-50% of the time to build strong customer relationships and support business growth. What You'll Be Doing: * Lead technical activities throughout the sales opportunity lifecycle, including technical discovery, negotiating success criteria, and delivering product presentations, demonstrations, and evaluations. * Engage directly with customers to analyze their product design needs and engineering workflows, articulating the value proposition of Ansys products and platforms. * Design and deploy differentiating simulation solutions using Ansys software, integrating them into customer workflows for maximum impact. * Act as a subject matter expert, developing deep industry knowledge and sharing best practices both internally and externally. * Collaborate with product development teams to translate customer requirements into new product features and test new releases on industrial problems. * Author conference presentations, support marketing initiatives, and deliver consulting services and training classes to enhance customer success. The Impact You Will Have: * Accelerate customer adoption of Ansys solutions, driving innovation in engineering design and simulation. * Enhance customer satisfaction by delivering tailored solutions that address real-world engineering challenges. * Influence future Ansys product development by providing vital feedback and identifying emerging industry needs. * Elevate Synopsys' reputation as a trusted technical advisor and industry thought leader. * Facilitate knowledge transfer within the team and across the organization, supporting a culture of continuous improvement. * Contribute to revenue growth and business expansion through successful technical engagements and consulting services. What You'll Need: * Mechanical Engineering degree with applicable work experience (MS or PhD preferred) * Required minimum years of professional experience in an engineering software environment: BS+5, MS+3, or PhD+0 * Strong foundation in fluid mechanics, computational fluid dynamics, and thermodynamics. * Demonstrated experience with Ansys software or other commercial CAE, CAD, EDA, PLM tools; industry experience in the Electronics segment preferred. * Proficiency in Python programming for simulation automation and workflow integration. * Ability to travel up to 25% (with flexibility up to 50% for customer-facing roles). Who You Are: * Logical problem-solver who thrives in fast-paced, dynamic environments. * Excellent communicator, able to explain complex concepts to both technical and non-technical audiences. * Collaborative team player who values diversity of thought and perspective. * Strong organizational and time management skills, with a drive for excellence and a sense of urgency. * Professional, business-savvy, and committed to personal and professional growth. The Team You'll Be A Part Of: You'll join the Ansys Customer Excellence team-a group of passionate engineers dedicated to empowering customers through leading-edge simulation solutions. This team thrives on collaboration, innovation, and knowledge sharing, working closely with product development, sales, and marketing to deliver transformative results and shape the future of engineering design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.