Design Verification Engineer remote jobs

Electrical Design Engineer (MEP) Houston, Texas $90,000 - $110,000 + Training + Career Progression + Support to Gain PE License + Bonus + Fantastic Benefits + Tuition Reimbursement + Work-From-Home Fridays! Are you an electrical engineer looking to work on exciting commercial MEP projects, with excellent training and a clear progression pathway to becoming a PE? This is an excellent opportunity to be the go-to electrical engineer on various technical construction projects, with the chance to progress into a Project Management position and gain your PE license. This growing company specializes in designing MEP systems for commercial projects. Due to their long-term expansion plans, they are looking for an Electrical Engineer to serve as a technical expert on diverse projects. They will also fund your PE license, granting you the opportunity to further advance your career. In this role, you will be based in the office, where you will be responsible for designing construction documents, producing electrical schematics and drawings, handling RFI documents, and liaising with clients and architects to meet project requirements. This is a great opportunity for an electrical engineer who wants to obtain their PE license and advance within a company that actively invests in its employees while working on technically challenging commercial projects. The Role: Serve as the technical expert for MEP systems in commercial projects Design electrical systems, liaise with site staff, and conduct site visits Office-based The Person: Electrical Engineer Degree in a relevant field Aspires to become a Professional Engineer

Description Ventana is building the highest-performance RISC-V CPUs on the planet-designed for data center, AI, and edge workloads, with real silicon, not slideware.Our second-generation Veyron core (V2) is on track to ship early next year, featuring an aggressive wide-issue pipeline and built in 4nm. Development on Veyron V3 is ramping now, with even greater performance and deep AI platform integration. This is your opportunity to work alongside engineers who built iconic processors like the AMD K6 and the first 64-bit ARM server processor (X-Gene at AppliedMicro)-bringing decades of CPU innovation to a clean-slate, open-standards future. You can check us out here: Ventana Micro - YouTubePrincipal CPU Design Verification Engineer:We are seeking an experienced verification engineer to lead verification efforts of complex CPU and related subsystems based on the open-source RISC-V architecture. The right candidate will have deep technical expertise combined with exceptional leadership skills.Responsibilities: Lead end-to-end verification from complex CPU sub-units up to CPU clusters, partnering with architecture and design teams Develop verification infrastructure components including test-benches, scoreboards, and stimulus generators Develop and execute comprehensive verification plans for units and features Implement functional coverage models Debug designs in simulation, prototyping platforms, and silicon Continuously drive methodology improvements to improve efficiency Lead senior and junior engineers as a team to accomplish successful projects Minimum Qualifications: Bachelors or Masters degree in electrical, computer engineering or related field BS+10 years or MS+12 years of industry experience successfully delivering CPU implementations Skills & Qualifications Required: SystemVerilog verification development experience Testbench construction using UVM or analogous methodologies Scoreboards and stimulus generators for complex units Strong background in one or more common CPU ISAs. x86, ARM, MIPS, RISC-V, etc. Strong background in processor coherency and MP programming Project ownership throughout the project lifecycle Demonstrated team leadership experience with outstanding communication skills Highly motivated self-starter with strong execution mindset and collaborative approach Post-silicon debug experience strongly preferred BASE SALARY RANGE $105,000 TO $260,000 per year EEOE Ventana is an Equal Employment Opportunity Employer. We value diversity and uphold an inclusive environment where all people feel that they are equally respected and valued. Qualified applicants will receive consideration without regard to race, color, creed, religion, sex, sexual orientation, national origin or nationality, ancestry, age, disability, gender identity or expression, marital status, veteran status, or any other category protected by law.COVID-19 Ventana encourages all employees to be fully vaccinated (and boosted, if eligible) against COVID-19. We do require Proof of vaccination (or proof of a negative PCR test) to work in the office or meet with customers/business partners NOTICE: External Recruiters/ Staffing Agencies: Ventana Micro instructs agencies not to engage with its employees to present candidates. Employees are not authorized to enter into any agreement regarding the placement of candidates. All unsolicited resumes received as gratuitous submissions. We reserve the right to directly contact any candidate speculatively submitted by a third party. Such contact will not constitute acceptance of any contractual arrangement between Ventana and the agency, and Ventana will not be liable for any fees should it choose to engage the candidate's services. All external recruiters and staffing agencies are required to have a valid contract executed by Ventana's CFO.Please Note: Fraudulent job postings/job scams are increasingly common. Our open positions can be found through the careers page on our website.

Ethernovia is fundamentally changing how cars of the future are built by unifying in-vehicle networks into an end-to-end Ethernet system. Founded in 2018, we're inventing the future of automobile's communication! We are transforming automobiles' communication network to enable the autonomous driving, electrical vehicle (EV) and software defined revolutions. Our breakthrough compute, communication, and software virtualization ushers in a new era of car connectivity and capabilities. We bring together, accelerate, and unify the car's cameras/sensors, compute, and outside world to enable new advanced driver assistance features and services. Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds' leading technology investors, having secured $64m in Series A funding. (Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire). Our financial backers include Porsche SE, Qualcomm, AMD, and Western Digital Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025. January 2024: Our CEO Ramin Shirani Named MotorTrend Software-Defined Vehicle Innovator Awards Winner (ethernovia.com) September 2023: Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news With talented employees on 4 continents, we have filed > 50 patents to date. Join Ethernovia's team to make a lasting impact on the future of mobility. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive their design from concept to silicon to their next car. Senior ASIC Design Verification Engineer Summary: As a Senior ASIC Design Verification Engineer, you will be responsible for all aspects of digital SoC verification. You will work the architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems. You will contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics. This position is located in: United States - Remote Key Qualifications: BS and/or MS in Electrical Engineering, Computer Science, or related field Minimum 10+ years of ASIC verification experience Strong understanding of ASIC verification fundamentals and industry standard methodologies Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++ Experience with the full verification flow, from spec to coverage analysis to gate level sim Debugging failures in simulation to root cause problems Self-motivated and able to work effectively both independently and in a team Additional Success Factors: Experience in any of the following areas: Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols) Video standards, protocols, processing Digital signal processing filters Third party IP (SerDes, controllers, processors, etc.) Modular and Reusable Testbench architecture Design for re-use of pre and post silicon tests and infrastructure Automation of testbench creation, tests, regression, or EDA tools Knowledge of SystemC and/or DPI Personal Skills: Excellent communication/documentation skills. Attention to details. Collaboration across multidisciplinary and international teams. What You Can Expect from Ethernovia: Technology depth and breadth expansion that can't be found in a large company Opportunity to grow your career as the company grows Pre IPO stock options Cutting edge technology World class team Competitive base salary Flexible hours Medical, dental and vision insurance for employees Salary Range: The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $200,000 - $300,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits. #LI-Remote

Condor Computing is a brand-new member of the RISC-V revolution. Condor is aiming to fly high by building the industry's highest performance licensable RISC-V core. Our team of highly experienced CPU designers will create a new benchmark for power efficiency in high performance open-source computing. We are pleased to announce that Condor is seeking a skilled and personable Sr. DV Engineer to become a valuable member of our team. In this position, you will have the opportunity to investigate innovative strategies to enhance the performance of our high-performance RISC-V processors, with a focus on all functions within the CPU core and memory systems. You will work collaboratively with a talented team, including engineers from RTL design, verification, and software groups, to propose enhancements, optimizations, and features based on performance assessments and PPA impact. Here is what you will do: Architect and implement testbenches utilizing UVM-based methodologies Design and develop Verification Components using UVM-based techniques Conduct block-level verification to ensure optimal block performance and compliance with requirements Generate and execute verification plans based on specifications Define, implement, and analyze coverage metrics Architect and implement Formal Verification processes Create automation tools to streamline testing Perform testing for design performance evaluation Here is the background we hope you have: A Master's or Bachelor's degree in Electronic/Electrical Engineering or Computer Science 8+ years of experience in Verification Proven industry experience in developing testbenches and verification components with SystemVerilog and UVM from inception In-depth knowledge of event-driven simulator-based modeling techniques Experience with low-power implementation (UPF) Familiarity with scripting languages such as Python, Ruby, or Perl A comprehensive understanding of chip and/or computer architecture These would be nice to have but are not required: Strong written and verbal communication abilities Exceptional collaboration skills across sites and functions Condor Computing is an equal opportunity and affirmative action employer. It ensures equal employment opportunity without discrimination or harassment based on race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity or expression, age, disability, national origin, marital or domestic/civil partnership status, genetic information, citizenship status, veteran status, or any other characteristic protected by law. We look forward to reviewing your application!

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for. Responsibilities & Skills We are seeking an experienced HDL design/verification engineer to design, develop, and enhance the simulation capabilities within Lattice Radiant - Lattice Semiconductor's official FPGA design tool. You'll be part of the Lattice Software Radiant team working closely with the hardware developers and QA teams to support simulation flows, help validate new features and ensure seamless integration of simulation engines with Radiant's toolchain. Key Responsibilities： Enable and support simulation workflows for Verilog, VHDL, and SystemVerilog across various Lattice FPGA families. Assist in diagnosing and resolving simulation issues reported by internal developers or users. Validate and test simulation features, waveform viewers, and debug interfaces within Radiant. Contribute to automation scripts and testbench generation tools. Maintain simulation documentation, troubleshooting guides, and user tutorials. Required Qualification: Bachelor's or Master's degree in Electronics Engineering, or related field Solid experience with hardware description languages (HDLs) and simulation tools (e.g., Modelsim, Synopsis VCS) Solid understanding of HDL simulation concepts: elaboration, scheduling, waveform generation Solid experience in EDA tool development or FPGA simulation frameworks Familiarity with Lattice Radiant Software, FPGA architectures, and configuration flows Industrial experience in similar field for > 5 years. Preferred Skillsets: Strong analysis and debugging capabilities. Excellent communication and cross-disciplinary collaboration skills. What We Offer: Direct impact on the evolution of FPGA development tools and methodology. Competitive compensation and comprehensive benefits. A highly collaborative and intellectually driven team environment. Supportive cross-geo team environment and technical mentorship.

JOB TITLE: FPGA Design/Verification Engineer - REMOTE PAY RATE: $87.19/hour We are a national aerospace and defense staffing agency seeking highly qualified candidates for a position with a top-tier client. Job Details: Job Type: Contract (12 months with potential for extension) Industry: Aerospace / Defense / Aviation Benefits: Medical, dental, and vision (Cigna) Perks: Bonus potential + Priority access via Tier 1 supplier Openings Nationwide: Thousands of opportunities across the U.S. Qualifying Questions: Are you a U.S. person as defined under ITAR regulations? Do you meet the educational and experience requirements for this role? Can you commute to the job location or relocate if necessary? Summary: Designing, testing, and integrating FPGA platforms, including work with COTS-based control platforms and embedded processors. Collaborate across disciplines with Software and Hardware teams to develop high-speed, cutting-edge systems for future aerospace applications. Design, simulate, and integrate FPGA/ASIC-based systems Support development with Microchip FPGAs and toolsets Automate and develop scripts to streamline FPGA development Collaborate with software and hardware engineering teams Support testing and debugging in a high-speed, space-rated environment Requirements: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field. Note: Candidates at Level 2, 3, or 4 will be considered based on experience and skills. Microchip FPGA development Proficiency with Microchip tools and processes FPGA platform integration and testing Experience with embedded processors on FPGAs Scripting for development automation RTG4 design and debugging High-speed interface design and testing Must be a U.S. Person (as defined by ITAR). About Us: The Structures Company is a premier national aerospace and defense staffing agency specializing in contract, contract-to-hire, and direct hire placements. We deliver expert workforce solutions across engineering, IT, production, maintenance, and support roles. As trusted partners to major aerospace OEMs and Tier 1 suppliers, we connect professionals with opportunities to grow and excel in the aviation and aerospace industries. Eligibility Requirements: Must be a U.S. Citizen, lawful permanent resident, or protected individual under 8 U.S.C. 1324b(a)(3) to comply with ITAR regulations. Keywords: aerospace, aviation, engineering, maintenance, aircraft design, defense Take your career to new heights-apply today!

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC products for vision processing, aerospace FPGAs, medical electronics, RISC-V based SoC, ARM based peripherals, and mixed signal DSPs. Successful candidates for this role will support verification of advanced CPU/GPU based SOCs. Correct Designs is NOT the typical contracting, staff augmentation firm. Our engineers have respected long term roles with generous hourly rates in excellent team environments. A typical contract may last 3 years, although we have shorter and even longer term work available. We are well respected in the Design Verification community with clients always seeking new CDI engineers. If you need a few months off between contracts you can take that break and know there will be plenty of work available when you return. If you like the stability of always working, simply move to the next contract with little time off. Correct Designs does provide health care and retirement plan benefits. We are based in Austin, Texas with clients throughout the US. There are opportunities for both in-person and remote work. Our current positions are filled but we have clients looking for skilled CDI engineers on a regular bases. Please submit your resume so we can match you up with upcoming projects. Whether you are an experienced veteran looking for new challenges, or a talented engineer seeking to broaden your experience, we can offer exciting options for your career. Correct Designs uses E-Verify to confirm work status eligibility. RESPONSIBILITIES: Verify complex design blocks using equally complex SV/UVM verification environments Develop and execute pre-silicon verification test plans Develop directed and random verification tests to validate block and IP functionality Develop verification components and tools Develop verification functional coverage using industry standard coverage analysis tools/methods Debug regression fails Replicate functional issues found in external environments or post-silicon; review/enhance tests to verify bug fixes REQUIRED SKILLS AND EXPERIENCE: 3 or more years of proven verification experience in a hardware development setting Strong background in SystemVerilog and UVM verification methodologies Strong debug skills and experience with debug tools such as DVE/Verdi Proficiency in Object Oriented programming, computer architecture and data structures Strong analytical/problem solving skills and pronounced attention to details Strong interpersonal and communication skills Must be comfortable working across geographies DESIRED SKILLS: Experience architecting/developing verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar Experience in other related domains such as formal verification, RTL design, or software development EDUCATION: Bachelor or Master's in Electrical Engineering, Computer Engineering, or Computer Science

Senior Design Verification Engineer Remote / work from home US Citizen or US Permanent Resident preferred Full-time/employee + Bonus, Benefits, 401k, Stock Options Responsibilities: Develop and execute verification plans for digital designs using SystemVerilog and UVM Create and maintain testbenches, test cases, and test vectors Contribute to the development of novel methodologies and verification techniques Run simulations to verify design against specifications and analyze results, identify issues, and debug designs Implement coverage tracking and metrics Document plans, environments, test cases, and all results for a comprehensive record of all verification strategies Your primary responsibilities will include developing test plans, writing testbenches and tests, and debugging any bugs found with the RTL team. Required Skills & Experience: BSEE/MSEE with 5-15 years of hands-on experience in SoC verification using UVM Experience in Gate Level Simulation (GLS) setup and process corner failure analysis Experience with digital design concepts and ASIC development flow Experience writing and debugging RTL using SystemVerilog Programming experience using C, C++, and/or Python/Perl Ability to work collaboratively across teams and communicate effectively Experience using Synopsys verification tools such as VCS, Verdi, and Spyglass Ability to multi-task and prioritize in a fast-paced environment; managing multiple complex, multidisciplinary tasks and projects Preferred Skills: Experience verifying RISC-V based systems Experience with emulation or FPGA prototyping Experience with formal verification methodologies Experience with the Chisel hardware description language Experience verifying high-speed interfaces such as PCIe and DDR Experience with version control systems (e.g., Git) and Continuous Integration/Continuous Deployment (CI/CD) pipelines

Join Our Team as an ASIC & FPGA Design Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: • Denver CO or Highlands Ranch CO • Sunnyvale CA • King of Prussia PA You will work a flexible 9x80 schedule in the office full-time. What does this role look like? The Silicon Solutions team of Lockheed Martin Space is building the best ASIC/FPGA team in the world, and are seeking a highly talented and motivated ASIC & FPGA Design Engineer who has a passion for microchip design and space. Key activities you will accomplish in this role: • Build and maintain strong technical relationships with multiple programs, serving as their trusted advisor and technical point of contact. • Lead a high-performing team of up to 7 people, prioritizing and allocating daily tasks to ensure successful project execution across multiple concurrent initiatives. • Develop and execute comprehensive project plans, delivering results within +/- 10% of schedule and budget while meeting agreed-upon quality metrics, and adapting Agile and Waterfall methodologies as needed to ensure successful outcomes. • Proactively monitor and manage team member workloads, tracking progress against assigned tasks and labor capacity, while collaborating with project engineers and managers as needed to ensure clear communication regarding the teams execution. • Foster a culture of technical excellence by providing guidance, mentorship, and expertise to team members on architecture, code, best practices, and command media, helping them to grow and develop their skills. • Balance hands-on technical work with other leadership responsibilities, ensuring that technical tasks do not compromise ability to fulfill responsibilities such as team leadership, mentoring, and project oversight. • Be responsible for the review and release of all work products to agreed quality standards. • Collaborate with teams to identify, scope and plan new opportunities and support completed work. • Perform advance chip architecture work for new programs and opportunities. • Prepare regular status and loading reports as well as materials and data for operations reviews • Assist manager in: o Reviewing and approving project plans o Technical proposal development, including scope capture and schedule development o Provide performance assessment input of individuals on your team o Program communication, issue de-escalation and risk mitigation o Determining team load capacity To be effective in this role, you will need: • 8+ years professional experience. • While no clearance is needed to start this position, you will need to obtain and maintain a TS/SCI clearance, thus US Citizenship is required. Basic Qualifications • Bachelor of Science or higher from an accredited college in Computer Engineering, Electrical Engineering or related discipline, or equivalent experience/combined education. • Experience in the design, debug and/or verification of any of the following: - FPGAs - Digital ASICs - Mixed-signal ASICs • HDL programming experience with VHDL, Verilog, and/or SystemVerilog. • Linux development environment Desired skills • Experience in leading or managing ASIC or FPGA projects. • Demonstrated self-starter and voracious learner • High EQ (Emotional Intelligence). • Space system design experience. • Understanding of system and hardware requirements related to space. • Microsoft Project or equivalent. • Microsoft Office. • Atlassian JIRA or equivalent. • Experience being a Control Accounts Manager (CAM) using Earned Value Management System (EVMS). • Customer-facing communication experience (product/services sales, marketing, field, etc.). • Ability to obtain a TS/SCI clearance. Why Lockheed Martin? Our employees play an active role in strengthening the quality of life where we live and work by volunteering more than 850,000 hours annually. Learn more about Lockheed Martin's comprehensive benefits package. At Space we value your skills, training, and education. We believe that by applying the highest standards of business ethics and visionary thinking, everything is within our reach - and yours as a Lockheed Martin Space employee… join us to experience your future! Let's do Space! Lockheed Martin is an equal opportunity employer. Qualified candidates will be considered without regard to legally protected characteristics. The application window will close in 90 days; applicants are encouraged to apply within 5 - 30 days of the requisition posting date in order to receive optimal consideration. * At Lockheed Martin, we use our passion for purposeful innovation to help keep people safe and solve the world's most complex challenges. Our people are some of the greatest minds in the industry and truly make Lockheed Martin a great place to work. With our employees as our priority, we provide diverse career opportunities designed to propel, develop, and boost agility. Our flexible schedules, competitive pay, and comprehensive benefits enable our employees to live a healthy, fulfilling life at and outside of work. We place an emphasis on empowering our employees by fostering an inclusive environment built upon integrity and corporate responsibility. If this sounds like a culture you connect with, you're invited to apply for this role. Or, if you are unsure whether your experience aligns with the requirements of this position, we encourage you to search on Lockheed Martin Jobs, and apply for roles that align with your qualifications. Other Important Information By applying to this job, you are expressing interest in this position and could be considered for other career opportunities where similar skills and requirements have been identified as a match. Should this match be identified you may be contacted for this and future openings. Ability to work remotely Onsite Full-time: The work associated with this position will be performed onsite at a designated Lockheed Martin facility. Work Schedule Information Lockheed Martin supports a variety of alternate work schedules that provide additional flexibility to our employees. Schedules range from standard 40 hours over a five day work week while others may be condensed. These condensed schedules provide employees with additional time away from the office and are in addition to our Paid Time off benefits. Security Clearance Information This position requires a government security clearance, you must be a US Citizen for consideration. Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $145,200 - $255,990. For states not referenced above, the salary range for this position will reflect the candidate's final work location. Please note that the salary information is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Life Insurance, Short-Term Disability, Long-Term Disability, 401(k) match, Flexible Spending Accounts, EAP, Education Assistance, Parental Leave, Paid time off, and Holidays. (Washington state applicants only) Non-represented full-time employees: accrue at least 10 hours per month of Paid Time Off (PTO) to be used for incidental absences and other reasons; receive at least 90 hours for holidays. Represented full time employees accrue 6.67 hours of Vacation per month; accrue up to 52 hours of sick leave annually; receive at least 96 hours for holidays. PTO, Vacation, sick leave, and holiday hours are prorated based on start date during the calendar year. This position is incentive plan eligible. Pay Rate: The annual base salary range for this position in most major metropolitan areas in California, Massachusetts, and New York is $167,000 - $289,340. For states not referenced above, the salary range for this position will reflect the candidate's final work location. Please note that the salary information is a general guideline only. Lockheed Martin considers factors such as (but not limited to) scope and responsibilities of the position, candidate's work experience, education/ training, key skills as well as market and business considerations when extending an offer. Benefits offered: Medical, Dental, Vision, Life Insurance, Short-Term Disability, Long-Term Disability, 401(k) match, Flexible Spending Accounts, EAP, Education Assistance, Parental Leave, Paid time off, and Holidays. This position is incentive plan eligible.

Cooperidge Consulting Firm is seeking a Senior Analog/Mixed Signal ASIC Design Engineer. This position offers the opportunity to take ownership of the full lifecycle of integrated circuit design - from concept and architecture through detailed design, implementation, verification, and delivery. The engineer will contribute to innovative hardware solutions, collaborate across multiple domains, and provide technical leadership on complex projects. In this role, you will Design and simulate circuits at the transistor level Develop system-level concepts and optimize hardware for performance, power, and cost Assess feasibility of advanced requirements and algorithms Create and review design specifications and block-level implementations Guide verification, test planning, and chip-level design activities Mentor less experienced engineers and share best practices Contribute to proposals and technical development efforts Requirements Qualifications Proficiency in integrated circuit design, semiconductors, and computer architecture Hands-on experience with circuit design, simulation, and layout practices Ability to write detailed design specifications and manage small technical teams Excellent analytical and mathematical skills Strong organizational skills, attention to detail, and ability to meet deadlines Effective verbal and written communication skills Strong problem-solving skills with the ability to adapt to changing requirements Demonstrated ability to prioritize tasks and lead solutions for complex problems Education Bachelor's degree in Engineering or related field required Master's degree preferred Experience requirements: 5-7 years with BS, OR 3-5 years with MS, OR 0-2 years with PhD in ASIC Hardware Engineering or related Must be eligible to obtain and maintain a U.S. government security clearance Benefits Health Care Plan (Medical, Dental & Vision) Retirement Plan (401k, IRA) Life Insurance (Basic, Voluntary & AD&D) Paid Time Off (Vacation, Sick & Public Holidays) Family Leave (Maternity, Paternity) Short Term & Long Term Disability Training & Development Work From Home

Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world's most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. Cornelis Networks is hiring talented Sr. ASIC Design Engineers with deep experience in one or more of the key areas required to build the world-class SoCs to be deployed in high performance computing, high performance data analytics, and artificial intelligence interconnect solutions. A good candidate will have 15+ years of ASIC design experience, with 10+ years of relevant experience in networking hardware design, proven expertise in 50G, 100G, 400G Ethernet MAC/PCS protocols, TCP/IP, RDMA/RoCE, IPSec. and their application in high-speed data processing/networking. Key Responsibilities: * Design and implement advanced Ethernet protocols for next-generation Ethernet switch ASICs, focusing on RTL development. * Develop microarchitecture specifications for Ethernet protocol blocks. * Implement Ethernet protocols such as Priority Flow Control, TCP, UDP, RoCEv2, VLAN, ECMP, DCQCN, ECN, and Security in Transmit and Receive pipelines using Verilog/System Verilog. * Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage. * Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure. * Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues. * Contribute to performance optimization and power-aware design strategies for Ethernet subsystems. Minimum Qualifications: * B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field. * 10+ years of industry experience in digital design with proficiency in Verilog and System Verilog. * Experience in RTL design for Ethernet protocols relevant to adapters and switches. * Familiarity with timing closure and modern physical design methodologies. * Proven ability in system-level debug and root cause analysis of technical issues. * Strong verbal and written communication skills. Preferred Qualifications: * Deep knowledge of Ethernet architecture and networking protocols (L2/L3/L4 layers). * Prior experience with Ethernet MAC integration and development of L2/L3/L4 protocols for ASICs, including system debug. * Expertise in multiple clock domain designs and asynchronous interfaces. * 10+ years of experience with scripting languages such as TCL, Python, or Perl. * Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime. Location: This is a remote position for employees residing within the United States. We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. In addition to your base pay, you'll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

The application window is expected to close on: 12/31/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three day per week at our Maynard, MA or San Jose, CA office. Meet the Team You will work with a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Mechanical Engineering, Optics, and manufacturing Process Engineering teams. Your Impact You will be key member of Acacia's Hardware Team. The Power Design Engineer will lead the design of DC-DC switch-mode power supplies and component selection. The successful candidate will work across disciplines to assure power supply designs meet the power, thermal, and safety requirements of the system specification. You will work closely with Acacia's multi-disciplinary engineering and manufacturing teams to understand the system requirements and contribute or lead the specification, design, and debug of complex power delivery systems for our products. * Architecture: Lead and contribute to power delivery system architecture and specifications. * Design: Design, analysis, and simulation of high current and low noise power delivery circuits. Debug: Contribute to system bring up, debug, and validation in the lab. * Verification: Write and execute test and DVT plans. Minimum Qualifications: * Bachelors + 8 years of related experience, or Masters +6 years of related experience, a PhD + 1 year of experience. 5 + years of direct Power supply design experience * Experience with high efficiency DC-DC power conversion design, analysis, circuit simulation, control loops, and stabilization. * Experience with phase and gain margins * Experience with power design component selection and trade-offs * Experience with Spice, LTspice, TI WorkBench, and circuit simulators * Experience in both high current low voltage multi-phase ()100W) as well as ultra-low noise power delivery circuitry * Experience with power supply layout and thermal design rules * Experience with Technical leadership of PCB layout with respect to various grounding and low noise etch techniques * Experience with power-up sequencing in multi-power supply systems * Experience in quickly grasping the existing designs and able to work independently with minimal supervision * Experience presenting technical information to technical and non-technical audiences. Preferred Qualification: * Experience with power supply layout and thermal design rules * Experience with Technical leadership of PCB layout with respect to various grounding and low noise etch techniques * Experience with power-up sequencing in multi-power supply systems * Expertise with AC and DC Power Integrity Simulation tools * Experience in power supply design for leading edge high speed communication devices * Experience in power supply design for sensitive optical components * Experience with power efficiency optimization schemes * Experience with Cadence Allegro and DxDesigner tools Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada: The starting salary range posted for this position is $168,800.00 to $241,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: * 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees * 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco * Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees * Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) * 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next * Additional paid time away may be requested to deal with critical or emergency issues for family members * Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: * .75% of incentive target for each 1% of revenue attainment up to 50% of quota; * 1.5% of incentive target for each 1% of attainment between 50% and 75%; * 1% of incentive target for each 1% of attainment between 75% and 100%; and * Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $168,800.00 - $277,400.00 Non-Metro New York state & Washington state: $148,800.00 - $248,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Job Description Hardware Design/Test Engineer, Mid-level - FAA Function: Hardware Design and Testing Remote Work Option: Yes Salary Range: $90- $130k Security Requirements Must be a US citizen or a legal resident for three of the past five years. Public Trust cannot be granted without meeting the residency requirement. Must meet eligibility requirements for a US Public Trust security clearance (moderate risk), including a soft credit check and criminal background check. Please refer to the criteria listed in 5 CFR 731.202 to understand the Public Trust suitability requirements. Culture Cobec is consistently breaking the current mold for delivering services to our government clients. What does that mean? That means believing in a “people first” mentality, building high performance teams and empowering people to make informed decisions without going through a large bureaucratic system. Cobec values the well-being of employees and bestows tremendous trust in those people to negotiate work and non-work obligations. Cobec is where someone can bring their whole self to work and be themselves, never having to compromise their authenticity just to fit in. Lastly, we believe in the work we do, the goals and missions of our customers and the interpersonal relationships we have with clients, stakeholders and our people. Values and Expectations The successful candidate for this role embodies the same values as Cobec. We realize experience is important, however; Cobec believes a person's abilities and skills that align with our values (Relationships, Leadership, Passion, Accountability, Integrity, Innovation, Quality, Teamwork, Diversity, Commitment, & Respect) are the most important drivers for success in this role. In addition to exhibiting our values, a successful candidate for this role is expected to be a high performer, organized, dynamic, and have a positive attitude. Job Summary This position will provide technical support to Federal Aviation programs through the development, validation, and deployment of mission-critical hardware systems. The role requires close coordination with engineering and operations teams to ensure designs are fully tested, field-ready, and installed without jeopardizing National Airspace System (NAS) safety or performance. Years of Relevant Experience The position requires 10+ equivalent years of experience in hardware development, implementation, configuration, installation, testing, and IT networking, preferably in FAA or aerospace environments. Essential Job Functions The following duties are normal for this position. The omission of specific statements of duties does not exclude them from this position if the work is similar, related, and/or a logical assignment for this position. Other duties may be required and assigned. Design, prototype, and validate hardware components for National Airspace System modernization efforts Develop and execute test plans to evaluate hardware performance in both lab and simulated operational settings Participate in planning discussions with FAA stakeholders to coordinate field implementation schedules that maintain NAS safety Analyze test data and provide recommendations for design refinements or field installation strategies Support configuration management processes and hardware documentation updates Advise field teams and system integrators during site deployments to ensure correct hardware implementation Individuals will be required to contribute effectively to working groups through oral and written communication and cooperative working relationships. Education Requirements Bachelor's degree required, preferably electrical, mechanical, or test engineering, or a related technical discipline. Skills Requirements Knowledge of FAA systems and requirements for field installation in operational NAS environments Strong analytical, diagnostic, and documentation skills Ability to communicate complex technical issues to multidisciplinary audiences Strong communication and reporting skills for collaboration across FAA regional teams High level of proficiency with MS Office Products. Strong analytical background and excellent communication and interpersonal skills. Travel Travel required as needed by client/s and/or company to various FAA field sites. EEO Cobec, Inc. is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, sex, age, sexual orientation, gender identity, national origin, disability, veteran status or any other status protected by federal, state and local law. EEO is the Law

We are seeking a highly skilled and motivated Layout Engineer to support the development of high-performance analog and mixed-signal integrated circuits. The ideal candidate will have hands-on experience in advanced CMOS technologies and a strong experience in physical layout verification and optimization of analog blocks. Responsibilities * Execute full-custom layout for analog and mixed-signal blocks including ADCs, DACs, PLLs, LDOs, comparators, and temperature sensors. * Collaborate with circuit designers to optimize layout for performance, area, and power. * Perform floorplanning, block-level routing, and macro-level assembly. * Conduct physical verification using tools like Cadence Virtuoso, Synopsys Custom Compiler, and Calibre. * Address DRC/LVS, EMIR, and DFM issues and ensure layout meets manufacturing and reliability standards. * Support tape-out activities and post-layout simulation reviews. * Document layout strategies and contribute to design reviews. Essential Skills * Minimum 4 years of experience in analog circuit layout in advanced CMOS technologies (2-3nm, gate-all-around). * Proficiency with layout tools such as Cadence Virtuoso and Calibre. * Understanding of analog layout techniques including matching, shielding, reliability, and parasitic optimization. Additional Skills & Qualifications * 5 overall years of experience in the field. * Experience with advanced FINFET and GAA is a plus. * No degree is required to be eligible for this role. * Candidates with only digital layout or older technology experience are not suitable. Work Environment The team focuses on designing and creating layouts for analog mixed signal circuits in advanced CMOS nodes (2-3nm) supporting data center processor development. The typical day involves 80% heads-down design/layout work and 20% in meetings. The environment emphasizes analog layout rather than custom digital, working on projects in advanced CMOS technology for in-house SoC designs. Job Type & Location This is a Contract position based out of Redmond, WA. Pay and Benefits The pay range for this position is $50.00 - $60.00/hr. Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following: • Medical, dental & vision • Critical Illness, Accident, and Hospital • 401(k) Retirement Plan - Pre-tax and Roth post-tax contributions available • Life Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term disability • Health Spending Account (HSA) • Transportation benefits • Employee Assistance Program • Time Off/Leave (PTO, Vacation or Sick Leave) Workplace Type This is a fully remote position. Application Deadline This position is anticipated to close on Dec 19, 2025. About Actalent Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law. If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.

Job Description We're seeking a talented Hardware Design Engineer to contribute to the development and verification of advanced digital designs. You'll work on cutting-edge ASIC and FPGA solutions, collaborating closely with cross-functional teams to bring next-generation technology to life. The position follows a flexible hybrid schedule. Responsibilities Participate in design architecture discussions and trade-off analysis. Write and verify RTL code for high-performance hardware components. Support hardware bring-up and provide technical assistance during customer engagements. Qualifications Proficient in SystemVerilog for digital design. Familiar with verification tools such as Questa, Incisive, or VCS. Experience with scripting (Python, Perl, Tcl) for process automation. Solid understanding of ASIC or FPGA logic design. Strong self-management, communication, and organizational skills. 5+ years of logic design experience and a BSEE degree. Preferred / Plus Experience with ASIC synthesis, timing constraints, CDC/RDC flows. Exposure to verification methodologies such as UVM. Familiarity with AMBA and AXI protocols.

Harness is a high-growth company that is disrupting the software delivery market. Our mission is to enable the 30 million software developers in the world to deliver code to their users reliably, efficiently, securely and quickly, increasing customers' pace of innovation while improving the developer experience. We offer solutions for every step of the software delivery lifecycle to build, test, secure, deploy and manage reliability, feature flags and cloud costs. The Harness Software Delivery Platform includes modules for CI, CD, Cloud Cost Management, Feature Flags, Service Reliability Management, Security Testing Orchestration, Chaos Engineering, Software Engineering Insights and continues to expand at an incredibly fast pace. Harness is led by technologist and entrepreneur Jyoti Bansal, who founded AppDynamics and sold it to Cisco for $3.7B. We're backed with $425M in venture financing from top-tier VC and strategic firms, including J.P. Morgan, Capital One Ventures, Citi Ventures, ServiceNow, Splunk Ventures, Norwest Venture Partners, Adage Capital Partners, Balyasny Asset Management, Gaingels, Harmonic Growth Partners, Menlo Ventures, IVP, Unusual Ventures, GV (formerly Google Ventures), Alkeon Capital, Battery Ventures, Sorenson Capital, Thomvest Ventures and Silicon Valley Bank As a Staff Growth Designer at Harness, you'll design experiences that accelerate adoption, retention, and expansion across the customer journey. You'll uncover where users lose momentum, design moments that re-engage them, and apply behavioral design principles to shape motivation, ability, and triggers. Every interaction should help users progress toward value naturally and intuitively. This role blends high-craft design with disciplined experimentation. You'll design and validate flows that feel intuitive and connected, using interaction, motion, and transitions to guide users seamlessly across states and surfaces. You'll partner closely with Product, Growth Marketing, and Engineering to uncover friction, form hypotheses, and translate behavioral insights into experiences that are fluid, purposeful, and outcome-driven. About the Role Design for impact: Create experiences that improve activation, retention, and expansion across key journeys Experiment and learn: Design, launch, and analyze A/B and multivariate tests to validate ideas and accelerate learning Collaborate across teams: Partner with Product, Growth, and Engineering to prioritize and deliver work that aligns user value with business outcomes Use data with intent: Define success metrics with analytics partners and translate findings into actionable design decisions Prototype rapidly: Build interactive prototypes and production-ready designs that bring growth ideas to life Enhance onboarding: Identify and remove friction in setup and education, ensuring users experience value early and often Drive Crossflow: Design cohesive transitions that reveal how our products work together and help users realize the full value of the platform. Scale design learning: Capture insights, build playbooks, and share patterns that help the broader team design for growth About You 4+ years in growth design within SaaS or technology environments Proven ability to design and iterate based on experimentation and user behavior Strong understanding of growth funnels, behavioral design, and motivation frameworks such as the Fogg Behavior Model Skilled in Figma and rapid prototyping tools Experience with analytics and experimentation platforms like Mixpanel, Amplitude, or FullStory Strong communicator who connects design intent to measurable outcomes Experience collaborating across Product, Growth, and Marketing to drive adoption and retention Experience with developer tools, CI/CD, or AI-driven platforms Work Location Remote from within the U.S or Hybrid from one of our offices in New York City, San Francisco, Boston, or Dallas What You Will Have at Harness Competitive salary Comprehensive healthcare benefits Flexible Spending Account (FSA) Employee Assistance Program (EAP) Flexible Time Off and Parental Leave Quarterly Harness TGIF-Off / 4 days Monthly, quarterly, and annual social and team-building events Recharge & Reset Program Monthly internet reimbursement Commuter benefit The anticipated base salary range for this position is between $170,00 and $202000 annually. Salary is determined by a combination of factors including location, level, relevant experience, and skills. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. The compensation package for this position may also include equity, and benefits. More details about our company benefits can be found at the following link: *************************************** A valid authorization to work in the U.S. is required Pay transparency$170,000-$202,000 USDHarness in the news: Harness AI Tackles Software Development's Real Bottleneck After 'Vibe Coding' Comes 'Vibe Testing' (Almost) Startup Within a Startup: Empowering Intrapreneurs for Scalable Innovation - Jyoti Bansal (Harness) Jyoti Bansal, Harness | the CUBEd Awards Eight years after selling AppDynamics to Cisco, Jyoti Bansal is pursuing an unusual merger Harness snags Split.io, as it goes all in on feature flags and experiments Exclusive: Jyoti Bansal-led Harness has raised $150 million in debt financing All qualified applicants will receive consideration for employment without regard to race, color, religion, sex or national origin. Note on Fraudulent Recruiting/Offers We have become aware that there may be fraudulent recruiting attempts being made by people posing as representatives of Harness. These scams may involve fake job postings, unsolicited emails, or messages claiming to be from our recruiters or hiring managers. Please note, we do not ask for sensitive or financial information via chat, text, or social media, and any email communications will come from the domain @harness.io. Additionally, Harness will never ask for any payment, fee to be paid, or purchases to be made by a job applicant. All applicants are encouraged to apply directly to our open jobs via our website. Interviews are generally conducted via Zoom video conference unless the candidate requests other accommodations. If you believe that you have been the target of an interview/offer scam by someone posing as a representative of Harness, please do not provide any personal or financial information and contact us immediately at *******************. You can also find additional information about this type of scam and report any fraudulent employment offers via the Federal Trade Commission's website (********************************************* or you can contact your local law enforcement agency.

Job Title: Sr. Staff HW CAD Engineer Duties: Requiring limited supervision * Technical Lead for full chip integration activities * Manage development and deployment of methodologies for integration activities both internally and with ASIC design partner in leading technology nodes * Drive the overall Global Clock design including simulations and work closely with ASIC design partner in implementing the Global Clocks * Lead Sign-off activities like STA, EMIR, Physical Verification from defining the methodology to running these at block and full chip level * Manage the execution of blocks from Synthesis, P&R to Timing Sign-off, Physical Sign-off and Electrical Sign-off * Collaborate closely with the Microarchitecture/RTL team to help drive PPA improvements and resolve design issues. * Influence tools, flows and overall RTL to GDS2 physical design methodology with a data driven approach. * Will work remotely We offer competitive salaries and comprehensive benefits packages. Please email your resumes to ***************. On your resume, please clearly note ADV: [source] and job title. Groq is an equal opportunity employer. Salary Range: $270,000 - $280,000 Location: Santa Clara County #LI-DNI

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Senior/Staff CAD Engineer We are looking for an experienced Senior/Staff CAD Engineer to drive design environment management and automation for Product and TEG chip development. This role is pivotal in developing and maintaining CAD workflows, creating automation scripts, and collaborating with cross-functional teams to improve design efficiency. ESSENTIAL DUTIES AND RESPONSIBILITIES: Design Automation and Methodology Establishment: Develop and maintain Virtuoso and Customer Compiler interfaces and utilities using the SKILL/Python/TCL/PERL languages. Develop, optimize and enhance the CAD automation and methodology scripts/programs. PCell/PDK Support: Create and maintain Parameterized Cells (PCell) to boost schematic/layout productivity. Design Rule & Verification Support: Develop and maintain Design Rule Checking (DRC) runsets using Calibre. Develop and maintain Layout vs. Schematic (LVS) runsets using ICV Cross-Team Collaboration & Troubleshooting: Work closely with IT teams and design engineers to manage layout data and resolve system issues. Provide technical guidance and troubleshooting support for the CAD infrastructure. Communication: Communicate effectively with EDA vendors to leverage advanced methodologies and tools that benefit the project. Work closely with the design/layout teams to achieve project goals and meet schedules while fostering a collaborative environment. Qualifications REQUIRED: Experience: 3 to 5 years in VLSI CAD development for semiconductor design is required. Experience in team management is highly advantageous. Programming & Scripting: Proficiency in SKILL, TCL/TK, Perl, Python, C/C++ and C-Shell scripting. EDA Tools: Familiarity with Virtuoso, Customer Compiler, Calibre, ICV, str RC, P&R, ERC, EM/IR, PrimeSIM, Spectre, HSPICE or the other Simulation tools, etc. SKILLS: Soft Skills: Strong problem-solving abilities and proven experience working in a cross-functional, collaborative environment. Additional Information Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person's gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person's assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal” poster. Our pay transparency policy is available here. Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Based on our experience, we anticipate that the application deadline will be 02/07/2026 (3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline. #LI-RT1 Compensation & Benefits Details An employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future. You will be eligible to participate in Sandisk's Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Sandisk's Standard Terms and Conditions for Restricted Stock Unit Awards. We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan. Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company's sole discretion, consistent with the law.

At Gigamon, our purpose is to protect the hybrid networks and data of the largest, most complex organizations on the planet. Certified as a Great Place to Work, we offer a deep observability pipeline that efficiently delivers network-derived intelligence to cloud, security, and observability tools. This helps our customers to eliminate security blind spots, optimize network traffic, and dramatically reduce tool cost and complexity, enabling them to better secure and manage their hybrid cloud infrastructure. Gigamon has served more than 4,000 customers worldwide, including over 80 percent of Fortune 100 enterprises, 9 of the 10 largest mobile network providers, and hundreds of governments and educational organizations. As a Principal Hardware Engineer at Gigamon, you will play a critical role in designing and developing advanced board-level hardware for next-generation networking products. You will join a small, dynamic global team, collaborating closely with product management and engineering partners to deliver innovative solutions that meet evolving customer needs. Your expertise will drive the architecture, validation, and release of high-performance systems, while also mentoring junior engineers and supporting products throughout their lifecycle. What you'll do: * Define architecture and high-level concepts for new systems and board-level products. * Design, develop, and validate board and system-level circuits, including both digital and analog technologies. * Investigate, qualify, and release new optical communications technologies. * Lead conceptual design, parts selection, simulation, schematic capture, and provide PCB layout guidelines. * Collaborate with product management to translate customer requirements into system designs. * Manage prototype builds with contract manufacturers and JDM/ODM partners. * Support environmental testing and production entry for boards and systems. * Mentor and guide junior engineers. What you've done: * Earned a BS in Electrical Engineering or equivalent; MS preferred. * Accumulated 15+ years of experience designing networking products or equivalent hardware, with familiarity in Broadcom/Marvell solutions considered a strong plus. * Demonstrated deep expertise in high-speed (100G PAM4) board design, including signal integrity and power integrity considerations. * Designed low-noise, high-efficiency on-board power regulation circuits. * Developed strong board-level debug and verification skills, utilizing test equipment such as oscilloscopes and logic analyzers. * Authored product specifications, test plans, and test procedures. Who you are: * A self-starter who is eager to learn new skills and adapt to evolving technologies. * A collaborative team player who communicates effectively with colleagues, managers, and customers. * Organized and able to prioritize responsibilities to meet deadlines in a fast-paced environment. * Analytical and resourceful, able to identify problems, gather data, and present solutions clearly. * Committed to mentoring and supporting the growth of others within the team. The base salary compensation range targeted for this role, based at Gigamon's Santa Clara, CA, Headquarters office, is $208,000 to $260,000, with an opportunity to earn an annual bonus or commission (subject to the terms and conditions of the plan). This salary range is an estimate, and the actual salary may vary based on the Company's compensation practices #LI-HYBRID