Principal Design Engineer jobs at Intel

The application window is expected to close on: 12/31/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three day per week at our Maynard, MA or San Jose, CA office. Meet the Team You will work with a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Mechanical Engineering, Optics, and manufacturing Process Engineering teams. Your Impact You will be key member of Acacia's Hardware Team. The Power Design Engineer will lead the design of DC-DC switch-mode power supplies and component selection. The successful candidate will work across disciplines to assure power supply designs meet the power, thermal, and safety requirements of the system specification. You will work closely with Acacia's multi-disciplinary engineering and manufacturing teams to understand the system requirements and contribute or lead the specification, design, and debug of complex power delivery systems for our products. * Architecture: Lead and contribute to power delivery system architecture and specifications. * Design: Design, analysis, and simulation of high current and low noise power delivery circuits. Debug: Contribute to system bring up, debug, and validation in the lab. * Verification: Write and execute test and DVT plans. Minimum Qualifications: * Bachelors + 8 years of related experience, or Masters +6 years of related experience, a PhD + 1 year of experience. 5 + years of direct Power supply design experience * Experience with high efficiency DC-DC power conversion design, analysis, circuit simulation, control loops, and stabilization. * Experience with phase and gain margins * Experience with power design component selection and trade-offs * Experience with Spice, LTspice, TI WorkBench, and circuit simulators * Experience in both high current low voltage multi-phase ()100W) as well as ultra-low noise power delivery circuitry * Experience with power supply layout and thermal design rules * Experience with Technical leadership of PCB layout with respect to various grounding and low noise etch techniques * Experience with power-up sequencing in multi-power supply systems * Experience in quickly grasping the existing designs and able to work independently with minimal supervision * Experience presenting technical information to technical and non-technical audiences. Preferred Qualification: * Experience with power supply layout and thermal design rules * Experience with Technical leadership of PCB layout with respect to various grounding and low noise etch techniques * Experience with power-up sequencing in multi-power supply systems * Expertise with AC and DC Power Integrity Simulation tools * Experience in power supply design for leading edge high speed communication devices * Experience in power supply design for sensitive optical components * Experience with power efficiency optimization schemes * Experience with Cadence Allegro and DxDesigner tools **Why Cisco?** At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint. Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you'll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. **Message to applicants applying to work in the U.S. and/or Canada:** The starting salary range posted for this position is $168,800.00 to $241,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits. Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees are offered benefits, subject to Cisco's plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time. U.S. employees are eligible for paid time away as described below, subject to Cisco's policies: + 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees + 1 paid day off for employee's birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco + Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees + Exempt employees participate in Cisco's flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations) + 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next + Additional paid time away may be requested to deal with critical or emergency issues for family members + Optional 10 paid days per full calendar year to volunteer For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco's policies. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows: + .75% of incentive target for each 1% of revenue attainment up to 50% of quota; + 1.5% of incentive target for each 1% of attainment between 50% and 75%; + 1% of incentive target for each 1% of attainment between 75% and 100%; and + Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $168,800.00 - $277,400.00 Non-Metro New York state & Washington state: $148,800.00 - $248,200.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. ** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements. Cisco is an Affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today. The mixed-signal high-speed I/O group delivers innovative PHY designs that power the most powerful AI systems in the world today. Our portfolio includes PHY IPs and Chips for both copper and fiber channels, supporting NVIDIA's high-performance interconnect protocols: NVLINK, Ethernet, and InfiniBand. We recently delivered the industry's first 200G MRM-based silicon photonics chip, revolutionizing high-performance networking and enabling the era of Co-Packaged Optics (CPO) for NVIDIA. We enable groundbreaking technology that continually pushes the limits of wireline communication! What You'll Be Doing While engaged in frontend development, your responsibilities will include working on a wide range of high-speed, powerful DSPs, silicon photonics IPs, and chips. You will participate in chip-level features, programming model and application interface definitions. You will collaborate closely with analog designers and system architects to develop micro-architecture specifications, calibration and adaptation algorithms, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing closure. Evaluating PPA trade-offs based on synthesis and P&R feedbacks is a critical step toward the most optimized product. For post-silicon, you will actively participate in silicon bring-up, build testing scripts for debugging, characterization, performance tuning, and production. You will also work with cross-functional teams to ensure successful production. What We Need to See * B.S. or M.S. degree in Electrical Engineering or equivalent experience. * 5+ years of experience in high-speed digital design, proficient with front-end design flow and tools. * Deep understanding of Verilog or System Verilog, logic design concepts, and typical structures. * Good understanding of design for test, timing constraints, and static timing analysis. * Experience with industry verification methodologies, such as UVM. Ways to stand out from the crowd * Knowledge of optical transceiver devices and integrated components such as modulators, detectors, and TIAs. * Experience with SerDes architecture and building blocks such as CDR, DFE, CTLE, TXFIR. * Experience with digital assist analog designs, such as calibrations. * Familiarity with mixed-signal circuit design concepts and experience in behavior modeling of mixed-signal circuits. Knowledge of physical layer and communication protocols, such as Ethernet, InfiniBand, PCIe, and USB. * Understanding of on-chip microcontrollers and standard peripherals, with exposure to hardware and firmware co-design. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until September 12, 2025. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can take on, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today. The mixed-signal high-speed I/O group delivers innovative PHY designs that power the most powerful AI systems in the world today. Our portfolio includes PHY IPs and Chips for both copper and fiber channels, supporting NVIDIA's high-performance interconnect protocols: NVLINK, Ethernet, and InfiniBand. We recently delivered the industry's first 200G MRM-based silicon photonics chip, revolutionizing high-performance networking and enabling the era of Co-Packaged Optics (CPO) for NVIDIA. We enable groundbreaking technology that continually pushes the limits of wireline communication! What You'll Be Doing While engaged in frontend development, your responsibilities will include working on a wide range of high-speed, powerful DSPs, silicon photonics IPs, and chips. You will participate in chip-level features, programming model and application interface definitions. You will collaborate closely with analog designers and system architects to develop micro-architecture specifications, calibration and adaptation algorithms, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing closure. Evaluating PPA trade-offs based on synthesis and P&R feedbacks is a critical step toward the most optimized product. For post-silicon, you will actively participate in silicon bring-up, build testing scripts for debugging, characterization, performance tuning, and production. You will also work with cross-functional teams to ensure successful production. What We Need to See B.S. or M.S. degree in Electrical Engineering or equivalent experience. 5+ years of experience in high-speed digital design, proficient with front-end design flow and tools. Deep understanding of Verilog or System Verilog, logic design concepts, and typical structures. Good understanding of design for test, timing constraints, and static timing analysis. Experience with industry verification methodologies, such as UVM. Ways to stand out from the crowd Knowledge of optical transceiver devices and integrated components such as modulators, detectors, and TIAs. Experience with SerDes architecture and building blocks such as CDR, DFE, CTLE, TXFIR. Experience with digital assist analog designs, such as calibrations. Familiarity with mixed-signal circuit design concepts and experience in behavior modeling of mixed-signal circuits. Knowledge of physical layer and communication protocols, such as Ethernet, InfiniBand, PCIe, and USB. Understanding of on-chip microcontrollers and standard peripherals, with exposure to hardware and firmware co-design. #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until September 12, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. ASIC Physical Design Engineer THE ROLE: The position will involve working with a very experienced physical design team of AMD graphics core and is responsible for delivering the physical design of blocks to meet challenging goals for frequency, power and other design requirements for AMD next generation graphics processors in a fast-paced environment on cutting edge technology. THE PERSON: Physical design Engineer with strong analytical thinking and problem-solving skills with excellent attention to detail. The candidates should have excellent communication skills, very good team player and ability to drive, lead and mentor team of engineers for project execution. KEY RESPONSIBILITIES: Physical design of complex GPU multi-millions gate design and achieve required performance, area and power targets Work with RTL design to analyze potential bottlenecks for frequency, resolve LOL and timing issue upfront in the project cycle to achieve frequency targets Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Innovus, genus PREFERRED EXPERIENCE: 10+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in leading team of Engineers for design closure Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Experience in RTL design and LOL reduction is preferred Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. Proficient in perl, python, tcl etc ACADEMIC CREDENTIALS: Bachelors or Masters in Electronics/Electrical Engineering LOCATION: Orlando FL, Santa Clara CA, Folsom CA, Austin TX, Boston, #LI-PH1 Requisition Number: 176681 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

What you do at AMD changes everything At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies - building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. The Role: This is a great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as Sr. Staff Engineer / Principal Member of Technical Staff. KEY RESPONSIBILITIES: Senior level lead engineer driving PPA improvements in both pre-silicon and post-silicon design phase Drive cross-functional teams (technology, CAD tools, platform characterization , binning practices and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt Improve low voltage margining methodology and design practices to improve Vmin and performance/watt for low power GFXIP Drive design practices to improve boost frequency for GFXIP Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high performance Graphics IP PREFERRED EXPERIENCE: Over 18 years' experience with BSEE/BSCS or 15+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII Excellent analytical and problem-solving skills along with attention to details Strong RTL analysis skills including Verilog, Timing Analysis and library understanding Strong knowledge in design margining methodology, low voltage design, silicon - STA correlation Hands on experience in taping out 5nm, 7nm, 14nm and/or 16nm SOC Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics Strong communication, Time Management, and Presentation Skills Must be a self-starter, and be able to independently and efficiently drive tasks to completion Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player ACADEMIC CREDENTIALS: Bachelor's or Master's Degree in Electrical Engineering, Computer Science, or equivalent is preferred. #LI-PH1 Requisition Number: 181183 Country: United States State: California City: Santa Clara Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for a ASIC Design Engineer, GPU/ML Shader Core who are motivated to challenge the status quo. If you are excited about building the next generation GPU/MI shader core, our team is on the lookout for you! You will be part of a fast-paced team working on the Graphics shader design, a team of engineers of varied disciplines who are responsible for micro-architecting, designing, and delivering GPU and ML/AI shader IP for various products. Since we are the heart of GPU engine, we strive to challenge ourselves in exceeding area, power, and performance targets. No idea is too small; we welcome every initiative that makes our product better. THE PERSON: You are an "out of the box" thinker, motivated to absorb dynamic changes and thirsty to keep innovating. You will work on the sub-block inside programmable engine aka shader core of the GPU. The shader core plays a key role in running applications program, feeding, and consuming the data to/from GPU shader resources and computing mathematical operations. Collaborate with software, architect, micro-architect and logic design team members to define and tackle "how to efficiently own an application program with the least number of instructions and data transfer while consuming the least amount of power". Strong interpersonal skills and an excellent teammate. KEY RESPONSIBILITIES: * Collaborate with block architect, ASIC designers and verification engineers to define and document block micro-architecture and analyze architectural trade-offs based on features, performance requirements and system limitations * Responsible for owning full design cycle from defining micro-architecture, implementing RTL, and deliver fully verified and PD timing clean design. * Consult DV engineers in describing features, outlining test plans, and closing on coverage * Assist DV engineers to debug functional, performance or power test failures * Work with Physical Design team to close on timing, area and power requirements PREFERRED EXPERIENCE: * Experience in micro-architecture and RTL development (Verilog), focused on GPU/CPU/ML/AI pipelines, arbiters, scheduling, synchronization & bus protocols, interconnect networks and/or caches. * Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis. * Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, CMOS transistors and circuits is required. ACADEMIC CREDENTIALS: * Undergraduate degree required. Bachelors or Masters degree in Computer Engineering/Electrical Engineering preferred. LOCATION: * Santa Clara CA - San Diego CA - Folsom CA This role is not eligible for Visa sponsorship. #LI-BM1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The SOC RTG team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies. THE PERSON: Excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. Highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team. KEY RESPONSIBILITIES: * Integrate AMD internal IPs RTL/DV environments into SoC * Debug function/performance of Graphics, Display, SMU IPs * Engage with IP and SOC teams to drive closure to IP RTL deliverables * Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation * Drive design and methodology improvements across teams to improve overall program execution PREFERRED EXPERIENCE: * Proficiency with Verilog/VHDL RTL design languages * Knowledge of chip bus interfaces such as AHB, AXI and various standard peripherals & interfaces is required * ASIC DV experience in reusable verification methodology such as UVM * Have hands-on experience in SOC Design/Integration activities, involving IPs, padring and pinmuxing * Have knowledge of SOC design specification, architecture and micro-architecture,ASIC, SOC, and IP Verification. * Strong industry experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed designs. * CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python ACADEMIC CREDENTIALS: * Bachelor or Masters Degree in Electrical Engineering, Computer Engineering or Computer Science This role is not eligible for Visa Sponsorship. #LI-PA1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD is looking for an engineering leader passionate about driving the best Power, Performance, Area (PPA) of AMD's SoC coherent Interconnects Data Fabrics IPs for next generation AMD AI devices. The ideal candidate will have proven experience in developing scalable complex digital IP microarchitectures to deliver industry leading performance/area and performance/power. In this role the candidate will work with IP and SOC Architecture team, RTL design team, verification team, and physical design team to drive the RTL design and microarchitecture of modular network on chip IPs for AMD Data Center silicon SoCs. The candidate will drive new methodologies to build scalable, modular network on chips. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AMD Data Center SoCs. THE PERSON: The ideal candidate has passion for modern, complex microarchitecture, and efficient digital design. Should have demonstrated experience in developing complex highly scalable, modular microarchitectures for SOC with focus on coherent and non-coherent switch fabric IP and must possess leadership and technical skills to influence and drive SOC methodologies to enable delivery of multiple highly complex, high quality, SoCs in shorter time. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: * Technical Microarchitecture lead on AMD Data Fabric RTL design team focused on driving the best scalability, modularity, power, performance, and area * Explore and dive initiatives to achieve best switch fabric scalability, modularity, and reuse across multiple advanced Data Center AI acclerator SOCs * Develop technical relationship with broader AMD design community and peers * Stay informed on latest trends on innovations on switch fabric hardware architecture and implementation. * Close architecture, and micro-architecture requirements, drive technical specifications for Data Fabric IP to meet those requirements, and drive RTL execution * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop RTL and microarchitecture solutions to achieve requirements * Knowledge sharing and other contributions to AMD Data Fabric architecture and design * Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Experience with highly scalable, configurable switch fabrics (coherent and non-coherent) * Experience with modern heterogenous systems including CPU, GPU, and AI accelerators. * Experience with SOC and IP creation automation for different microarchitectures * Proven track record of defining and delivering complex IP and SOC microarchitectures. * Expert level ability in optimizing and performing tradeoff analysis across multiple domains including PPA, design, microarchitecture, and architecture, verification, and schedule. * Expert of RTL design, Verilog and SystemVerilog * Deep knowledge of front-end tools * experience with synthesis, static timing, DFT * Exposure to physical design and verification methods * Experience with scripting languages such as Perl, Python, Unix shells and Makefiles, and leveraging AI tools to improve improductivity. * Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-systems, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security * Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads * Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture and logic design * Excellent communication, management, and presentation skills. * Adept at collaboration among top-thinkers and senior architects and designers with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering preferred LOCATION: Santa Clara, Ca #LI-MR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

What you do at AMD changes everything We care deeply about transforming lives with AMD technology to enrich our industry, our communities and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. AMD together we advance_ Staff ASIC Design Engineer - AI Engineer- 152880 THE ROLE: AMD-Xilinx is seeking a capable and motivated RTL/ASIC design engineer to be part of front-end design team of next generation AI Engine/ML processors. THE PERSON: You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications. KEY RESPONISIBILITES: In this role you will: Define and specify micro-architecture of processor building blocks based on architecture requirements RTL design and debug of complex blocks in Verilog / System Verilog Analyze performance and make implementation choices to optimize timing Analyze and optimize design for power efficiency and power integrity Work with verification and physical design teams to achieve high quality design and successful tape out Solve customer problems through innovative enhancements to product architecture/ micro-architecture Design and implement underlying clocking infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory Collaborate with cross-functional teams to solve novel problems across multiple functional areas in development of clocking features and/or algorithms PREFERRED EXPERIECE: Strong experience in the following ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes Digital design and experience with RTL design in Verilog/System Verilog Circuit timing/STA, and practical experience with Prime Time or equivalent tools Low power digital design and analysis Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation Experience in following is highly desired Understanding of FPGA architecture and implementation flow TCL, Perl, Python scripting Version control systems such as Perforce, ICManage or Git Strong verbal and written communication skills Ability to organize and present complex technical information Fluent in working with Linux environment Needs to be manually updated. ACADEMIC CREDENTIALS BSEE or equivalent and 8 years of relevant work experience, or MSEE or equivalent with 6 years of experience LOCATION:San Jose, CA #LI-DA1 Requisition Number: 152880 Country: United States State: California City: San Jose Job Function: Design Benefits offered are described here. AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a SoC Architect to join our adaptive SoC Architecture team. This role is pivotal in defining and driving architecture for next-generation Adaptive SoCs, with on Processor subsystems, Interconnect, AI, GPU, video processing pipelines, and memory systems. THE PERSON You are a seasoned SoC architect with deep expertise in heterogeneous compute systems. You thrive in collaborative environments and bring a system-level mindset to solving architectural challenges. You are passionate about performance, power, and scalability, and have a strong grasp of silicon design trade-offs. You communicate effectively across engineering disciplines and influence architectural decisions with clarity and technical rigor. KEY RESPONSIBILITIES * Drive architecture of key IPs including their PPA tradeoffs, Interconnect, and integration into SoC * Define and optimize SoC control bus protocols, reset flows, clocking strategies, and power domains. * Drive early-stage architectural analysis, modeling, and specification development. * Contribute to architectural innovation for Adaptive SoC Use-cases in AI, GPU, video, and IO domains. * Collaborate with planning, software and hardware cross-functional teams to develop architecture solution. * Collaborate with subsystem architects to ensure cohesive integration and system-level performance. PREFERRED EXPERIENCE * Proven experience in SoC architecture with Processor, Interconnects, and Memory subsystem. * Expertise in AI accelerators, GPU integration, video processing pipelines, and IO subsystems. * Expertise in SoC control bus design, reset architecture, clocking , and power management techniques. * Experience with modeling and automation using Python, SystemC, or equivalent. * Knowledge of advanced process technologies and associated design challenges. ACADEMIC & EXPERIENCE REQUIREMENTS * BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field. * Demonstrated success in delivering high-performance, low-power SoC solutions. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: A senior technical contributor that drives end-to-end delivery of SerDes solution directly contributing to and coordinating implementation and optimization across multiple teams. The position will involve interfacing with software and hardware engineering teams and AMD partners to plan, develop and optimize use cases. This is an exciting opportunity to work on the cutting edge of SerDes Technology. THE PERSON: You are a subject matter expert and strong technical contributor with SerDes/PHY experience. You excel as part of a team where communication and team skills are highly valued. KEY RESPONSIBILITIES: As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: * Write microarchitecture and/or design specifications * Design, implement, and debug complex logic designs * Integrate complex IPs into the SOC * Work with other specialists that are members of the SOC Design - Verification, Emulation, STA, and Physical Design teams * Support all front end integration activities (Lint, CDC, Synthesis, and ECO) * Implement design automation via Python or other languages * Collaborate with software and systems teams to ensure a high quality system PREFERRED EXPERIENCE: * Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies * Writing specifications and converting them to design * Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs is highly desirable * Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks. * Experience in low-power design techniques such as clock- and power-gating is a plus * Ability to communicate effectively across all internal groups * Familiarity with scripting languages like Perl or Python or Tcl is a plus * Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) is a plus * Familiarity with security concepts is a plus * Familiarity with software and operating concepts is a plus * Excellent communication and collaboration skills ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: San Jose, CA, or anywhere in the US #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: AMD Serdes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS process. We are currently seeking an analog/mixed-signal design engineer to join our world-class team. THE PERSON: The candidate will be responsible for the design of high-speed ADC-based receivers, DAC-based transmitters, or silicon photonics transceivers. KEY RESPONSIBILITIES: * Define circuit architectures optimized for high bandwidth electrical and optical links * Perform link level simulation in Matlab and/or SPICE to prove the architecture * Perform design and modeling of on-die RF passive components (e.g., inductors and capacitors) and/or optical structures * Design circuit components (e.g., DAC, SAR-ADC, S/H, Analog Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process PREFERRED EXPERIENCE: * Strong background in analog and mixed-signal circuit design * Strong teamwork and communication skills * History of coming up with innovative circuit design/architecture is a plus ACADEMIC CREDENTIALS: * BS or MS or PhD in Electrical Engineering or Computer Engineering or related equivalent. LOCATION: San Jose, CA #LI-TB2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a seasoned Lead Design Verification Engineer with expertise in verifying networking chip. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead verification teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams, marketing, and business unit executives. THE PERSON: We are seeking an experienced and hands-on Lead Design Verification Engineer to drive the verification strategy, methodology, and execution for our next-generation high-performance networking chip. The ideal candidate will have deep expertise in SoC/ASIC verification, strong knowledge of networking protocols and architectures, and a proven ability to lead verification teams in a fast-paced environment. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: * Ownership of verification strategy for one or more major IP blocks or subsystems within a complex networking ASIC. * Architect and implement testbenches using UVM/SystemVerilog, ensuring maximum coverage and quality. * Develop and maintain test plans, coverage models, and scoreboards to ensure comprehensive verification of all design features. * Lead and mentor a team of DV engineers - drive reviews, define milestones, and ensure high-quality deliverables. * Collaborate closely with design, architecture, and software teams to define verification requirements and debug issues across the full chip. * Develop and maintain automation and regression infrastructure, including CI/CD integration. * Drive coverage closure and signoff for IP and SoC-level verification. * Contribute to methodology improvements, verification IP reuse, and best practices across the DV organization. * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Proven line management experience, including hiring, mentoring, and performance management of DV engineers. * Demonstrated ability to build and lead high-performing verification teams, setting goals and driving execution across projects. * Experience with chip-level verification for networking ASICs, switches, or routers. * Familiarity with traffic generators, packet-level verification, and network protocol stacks. * Knowledge of SystemC, C testbenches, or hardware/software co-verification. * Exposure to emulation or FPGA prototyping environments (e.g., Palladium, Veloce). * Prior experience leading cross-site or multi-IP verification efforts. * Strong communication, collaboration, and leadership skills with the ability to influence technical direction across disciplines. ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: Santa Clara, CA This role is not eligible for VISA sponsorship #LI-BW1 #LI-hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an experienced Verification Engineer to join our team as a Technical Lead for cutting-edge server memory products. This individual will be responsible for driving the verification efforts of DDR interfaces, including advanced memory protocols such as DFI, DDR5, and LPDDR5, across a range of DIMMs (Dual In-line Memory Modules). The ideal candidate will possess expert-level knowledge of SystemVerilog, UVM, C/C++, and scripting languages like Python/Perl, and will have a proven track record of multiple tape-out experiences and successful verification sign-offs in a high-performance server memory environment.. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: * Technical Leadership & Project Oversight: Lead and guide a team of verification engineers in the development and execution of verification strategies for DDR5, LPDDR5, and DFI memory systems in server products. * Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features of the memory interface. * Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements * Knowledge sharing and other contributions to verification methodology * As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests * Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs * Support Post-Si teams for Product Performance, Power and functional issues debug/resolution PREFERRED EXPERIENCE: * Developed and implemented SystemVerilog and UVM (Universal Verification Methodology) based testbenches, simulation environments, and functional coverage models for DDR5 and LPDDR5 systems. * Worked closely with hardware, firmware, and software teams to align on system-level memory architecture, identify potential integration issues, and define validation requirements early in the design phase. * Provided technical leadership across multiple teams, driving cross-functional collaboration to solve complex issues in memory systems, from firmware to hardware. * Built VIPs and BFMs for memory interfaces from scratch (preferrable) * GLS, NLP, XPROP simulation experience is required * Strong proficiency in system verilog assertions, constraints and coverage. * Worked in formal verification methods, with proven record of tool usage beyond the standard apps. * Working knowledge of DFT flows (preferrable) * Excellent communication, management, and presentation skills. * Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: * Bachelor's or Master's degree in related discipline preferred LOCATION: Santa Clara, CA #LI-SC3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available. We are seeking a highly skilled Formal Verification Expert to join our talented team as a Staff Engineer and technical lead. This role is crucial to ensuring IP quality through rigorous formal verification processes. THE PERSON: The successful candidate will play a key role in developing verification strategies, leading formal verification team, and collaborating across departments to ensure the highest quality standards. KEY RESPONSIBILITIES: * Lead formal verification team to ensure IP quality and project execution. * Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc.. * Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies. * Mentor and guide junior engineers in formal verification techniques and best practices. * Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations. * Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities. PREFERRED EXPERIENCE: * Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems. * Proficiency in formal verification tools such as VC-Formal or JasperGoal * Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python). ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering LOCATION: Santa Clara, CA This role is not eligible for visa sponsorship #LI-SL3 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE We are seeking a Senior Member of Technical Staff (SMTS) SoC Architect to join our SoC Architecture team. In this role, you will define and drive architecture for critical SoC functions across roadmap and custom devices. You will focus on chip pervasive components, while ensuring seamless integration with processor subsystems, interconnect, AI accelerators, and memory systems. THE PERSON You are passionate about complex SoC architecture and thrive in cross-functional environments. You have deep technical expertise, strong analytical skills, and the ability to balance performance, power, and area trade-offs. You communicate effectively across teams and are comfortable influencing architecture decisions for next-generation silicon. KEY RESPONSIBILITIES * Define and develop SoC architecture for CPF components, including Analog IPs, clocking/reset, and silicon monitors. * Collaborate with processor, interconnect, AI, and memory subsystem architects to ensure cohesive system-level design. * Specify architecture requirements, conduct early-stage analysis, and create detailed specifications. * Drive PPA optimization and ensure scalability across roadmap and custom devices. * Partner with design, verification, and physical implementation teams to ensure functional correctness and timing closure. * Analyze trade-offs for performance, power, reliability, and manufacturability. * Influence strategies for security, safety, and reliability across CPF domains. * Strong communication and leadership skills to influence cross-functional teams. PREFERRED EXPERIENCE * Strong background in SoC architecture, including processor subsystems, interconnect, memory systems, and AI accelerators. * Expertise in Analog IPs (IOs, PLLs, eFuses, monitors), clocking/reset architecture, and silicon lifecycle management. * Familiarity with SoC on-chip protocols (e.g., AXI) and system-level QoS. * Experience with low-power design techniques, boot/reset flows, and power management. * Knowledge of design methodologies, advanced process technologies, and associated challenges. * Proficiency in modeling and automation using Python, SystemC, or similar languages. ACADEMIC & EXPERIENCE REQUIREMENTS * BS or MS or PhD in Electrical/Computer Engineering or related field. * Proven track record in delivering architecture for high-performance, low-power SoCs. LOCATION: San Jose, California #LI-DR1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SENIOR SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: * Develop/Maintain tests for functional verification and performance verification at the core level * Build testbench components to support the next generation IP * Maintain or improve current test libraries to support IP level testing * Create hardware emulation build to verify the IP functional performance * Maintain and improve current hardware emulation environment to speed up the runtime performance and improve the debug facility * Provide technical support to other teams PREFERRED EXPERIENCE: * Good at C/C++ * Familiarity with SystemVerilog and modern verification libraries like UVM * Experience/Background on Computing/Graphics is a benefit * Experience with OpenGL/OpenCL/D3D programming is a benefit ACADEMIC CREDENTIALS: * Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-CJ2 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are seeking a highly motivated and experienced Senior Silicon Design Engineer to join our AECG SIT team. This role involves leading and contributing to the design, integration, and characterization of advanced silicon testchips for FPGA products across cutting-edge process nodes. THE PERSON: You are an expert in IC design and manufacturing including analog/digital IP integration, chip design, silicon process or packaging technologies. A good understanding of foundry technology PDK, device physics, reliability and silicon chip manufacturing is essential. The candidate must also demonstrate effective communication, good interpersonal skills, along with a strong interest in emerging technologies and innovation. KEY RESPONSIBILITIES: * Facilitate the design and seamless integration of custom digital and analog blocks. * Support functional, timing and EMIR verification of IP blocks in custom design flow. * Collaborate cross-functionally with layout designers, IC design teams, foundry partners, CAD engineers, and test teams to ensure seamless integration and execution. * Develop end-to-end test solutions, including board-level and system-level design, for advanced test vehicle initiatives. * Assist with the bring-up and debugging of testchip silicon in lab environments. PREFERRED EXPERIENCE: * Strong foundation in circuit design and semiconductor device physics and reliability. * Hands-on experience in designing and validating circuits across advanced technology nodes such as FinFET and Gate-All-Around. * Working knowledge of digital P&R design and verification. * Working knowledge of 2.5D and 3D stacked silicon and advanced package assembly technologies. * Experience with usage of major EDA tools for device model, layout, circuit simulation, parasitic extraction, and physical verification. * Working knowledge of PCB/package design and signal/power integrity (SI/PI) analysis. * Proficiency in C/C++ and Python for programming and scripting tasks. Exposure to AI-based coding tools (e.g., GitHub Copilot) is a plus. * Hands-on experience with silicon bring-up and lab bench test equipment. ACADEMIC CREDENTIALS: Preferably holds an advanced degree (PhD or MS) in electrical & electronics engineering or physical sciences; alternatively, a bachelor's degree with 5+ years of relevant industry experience is acceptable. LOCATION: San Jose, California #LI-DR1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

Intel Central Engineering Group is engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications, and they are completely dedicated to the success of its customers with full profit and loss responsibilities. Our Focus us to ensure the successful integration and adoption of Intel technologies by its original equipment manufacturers (OEMs), original design manufacturers (ODMs), and Design partners. This team serves as a critical technical interface, acting as the "voice of the customer" within Intel to drive product improvements and resolve issues throughout the entire product lifecycle. The Senior Silicon Design Engineer will be responsible for, but not limited to: * Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. * Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. * Conducts verification and signoff, including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. * Analyzes results and makes recommendations to fix violations for current and future product architecture. * Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools. * Optimizes design to improve product level parameters such as power, frequency, and area. * Participates in the development and improvement of physical design methodologies and flow automation. Qualifications: The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: * Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study. * 5+ years of experience with complex ASIC/SOC Implementation. * Experience in system and processor architecture. * Experience designing and implementing complex blocks like CPUs, GPU, Media blocks, and Memory controller. * Experience with System Verilog/SOC development environment. * Experience in scripting languages (i.e. PERL, TCL, or Python). * Experience with Hardware validation techniques (i.e. formal Verification, Test and Function Verification). Preferred Qualifications: * Post graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study. * Experience with Industry standard protocols (i.e. PCIE, USB, DRR, etc). * Experience with interaction of computer hardware with software. * Experience with Low power/UPF implementation/verification techniques. * Experience with Formal verification techniques. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro Business group: Intel makes possible the most amazing experiences of the future. You may know us for our processors. But we do so much more. Intel invents at the boundaries of technology to make amazing experiences possible for business and society, and for every person on Earth. Harnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. Leading on policy, diversity, inclusion, education and sustainability, we create value for our stockholders, customers, and society. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Benefits: We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: ********************************************************************************** Annual Salary Range for jobs which could be performed in the US: 139,710.00 USD - 262,680.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process. Work Model for this Role This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.